memory_mcs_attributes.xml

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<!-- $Source: src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml $ -->
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<attributes>
    <!-- MCS attribute array indexes are always [port][dimm] -->
    <attribute>
        <id>ATTR_MSS_VOLT_VDDR</id>
        <targetType>TARGET_TYPE_MCBIST</targetType>
        <description>
            DRAM Voltage, each voltage rail would need to have a value.
            Computed in mss_volt C code - in millivolts
            creator: mss_volt
            consumer: mss_eff_cnfg, others
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint32</valueType>
        <writeable/>
        <mssAccessorName>volt_vddr</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_MSS_VOLT_VPP</id>
        <targetType>TARGET_TYPE_MCBIST</targetType>
        <description>
            DRAM VPP Voltage, each voltage rail would need to have a value.
            Computed in mss_volt C code - in millivolts.  0V - DDR3, 2.5V - DDR4
            creator: mss_volt
            consumer: mss_eff_cnfg, others
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint32</valueType>
        <writeable/>
        <mssAccessorName>volt_vpp</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_MSS_FREQ_OVERRIDE</id>
       <targetType>TARGET_TYPE_MCBIST</targetType>
        <description>
          FOR LAB USE ONLY: Frequency override of this memory channel in MT/s
          comprising of up to three DIMMs.
          Set by config file or an attribute writing program.
          Consumed by mss_freq.
          The default of AUTO means mss_freq will find the best frequencies given the DIMMs plugged in and other rules.
          Otherwise, this is the system frequency.
        </description>
        <initToZero></initToZero>
        <valueType>uint64</valueType>
        <enum>AUTO = 0</enum>
        <writeable/>
        <mssAccessorName>freq_override</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_MSS_FREQ</id>
        <targetType>TARGET_TYPE_MCBIST</targetType>
        <description>
            Frequency of this memory channel in MT/s (Mega Transfers per second),
            comprising of three DIMMs.
            Computed in mss_freq
            creator: mss_freq
            consumer: mss_eff_cnfg, others
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint64</valueType>
        <!-- We rely on these being their actual MT/s for freq/time conversions -->
        <enum>
          MT1866 = 1866,
          MT2133 = 2133,
          MT2400 = 2400,
          MT2666 = 2666
        </enum>
        <writeable/>
        <mssUnits> MT/s </mssUnits>
        <mssAccessorName>freq</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_MSS_FREQ_BIAS_PERCENTAGE</id>
        <targetType>TARGET_TYPE_MCBIST</targetType>
        <description>
            Percentage to increase/decrease MEM frequency - two's complement number.
            Measured in 100's.  So the value of 100 is one percent increase.
            This frequency change comes from changing multipliers and dividers to  get the desired frequency.
            The supported frequencies come from Tim Diemoz.
            Creator: platform set this to 0.  Users can set this to a valid value.
            VALID Values: (TBD % to TBD %) (Tuleta) (TBD % to TBD %) (Glacier)
            Set by: PLL settings written by Dave Cadigan
        </description>
        <initToZero></initToZero>
        <valueType>uint32</valueType>
        <writeable/>
        <mssAccessorName>freq_bias_percentage</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_SPARE</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            Spare DRAM availability. Used in various locations and is computed in mss_eff_cnfg.
            creator: mss_eff_cnfg consumer: various firmware notes: load from spd
            OBSOLETE: Use ATTR_VPD_DIMM_SPARE
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>NO_SPARE = 0, LOW_NIBBLE = 1, HIGH_NIBBLE = 2, FULL_BYTE = 3</enum>
        <writeable/>
        <array> 2 2 4</array>
        <mssAccessorName>eff_dimm_spare</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_WR_VREF</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            DRAM Write Vref.
            Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination.
            creator: VPD(MT) or mss_eff_cnfg_termination
            consumer: various.C and initfile
            firmware notes: none
            This is the nominal value
            This is for DDR3
        </description>
        <initToZero></initToZero>
        <valueType>uint32</valueType>
        <enum>
            VDD420 = 420,
            VDD425 = 425,
            VDD430 = 430,
            VDD435 = 435,
            VDD440 = 440,
            VDD445 = 445,
            VDD450 = 450,
            VDD455 = 455,
            VDD460 = 460,
            VDD465 = 465,
            VDD470 = 470,
            VDD475 = 475,
            VDD480 = 480,
            VDD485 = 485,
            VDD490 = 490,
            VDD495 = 495,
            VDD500 = 500,
            VDD505 = 505,
            VDD510 = 510,
            VDD515 = 515,
            VDD520 = 520,
            VDD525 = 525,
            VDD530 = 530,
            VDD535 = 535,
            VDD540 = 540,
            VDD545 = 545,
            VDD550 = 550,
            VDD555 = 555,
            VDD560 = 560,
            VDD565 = 565,
            VDD570 = 570,
            VDD575 = 575
        </enum>
        <writeable/>
        <array> 2</array>
        <mssAccessorName>eff_dram_wr_vref</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_WR_VREF_SCHMOO</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            Enables for which VREF to use on the WR Schmoo.
            The LSB corresponds to the highest WR Vref
        </description>
        <initToZero></initToZero>
        <valueType>uint32</valueType>
        <writeable/>
        <array> 2</array>
        <mssAccessorName>eff_dram_wr_vref_schmoo</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_WRDDR4_VREF_SCHMOO</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            Enables for which VREF to use on the WR Schmoo.
            The LSB corresponds to the highest WR Vref
        </description>
        <initToZero></initToZero>
        <valueType>uint32</valueType>
        <writeable/>
        <array> 2</array>
        <mssAccessorName>eff_dram_wrddr4_vref_schmoo</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_SIZE</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            DIMM Size, in GB Used in various locations and is computed in mss_eff_cnfg.
        </description>
        <initToZero></initToZero>
        <valueType>uint32</valueType>
        <enum>
          4GB = 4,
          8GB = 8,
          16GB = 16,
          32GB = 32,
          64GB = 64,
          128GB = 128,
          256GB = 256,
          512GB = 512
        </enum>
        <writeable/>
        <array> 2 2</array>
        <mssUnits>GB</mssUnits>
        <mssAccessorName>eff_dimm_size</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_CL</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            CAS Latency.
            Each memory channel will have a value.
            creator: mss_freq
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 </array>
        <mssAccessorName>eff_dram_cl</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_AL</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            Additive Latency.
            Used in various locations and is computed in mss_eff_cnfg_timing.
            Each memory channel will have a value.
            creator: mss_eff_cnfg_timing
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>DISABLE = 0, CL_MINUS_1 = 1, CL_MINUS_2 = 2</enum>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_dram_al</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_CWL</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            CAS Write Latency.
            Used in various locations and is computed in mss_eff_cnfg_timing.
            Each memory channel will have a value.
            creator: mss_eff_cnfg_timing
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_dram_cwl</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_RBT</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            Read Burst Type.
            Used in various locations and is computed in mss_eff_cnfg.
            Each memory channel will have a value.
            creator: mss_eff_cnfg
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>SEQUENTIAL = 0, INTERLEAVE = 1</enum>
        <writeable/>
        <array>2 2</array>
        <mssAccessorName>eff_dram_rbt</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_TM</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            Test Mode.
            Used in various locations and is computed in mss_eff_cnfg.
            Each memory channel will have a value.
            creator: mss_eff_cnfg
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>NORMAL= 0, TEST = 1</enum>
        <writeable/>
        <array>2 2</array>
        <mssAccessorName>eff_dram_tm</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_DLL_RESET</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            DLL Reset.
            Used in various locations and is computed in mss_eff_cnfg.
            Each memory channel will have a value.
            creator: mss_eff_cnfg
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>NO = 0, YES = 1</enum>
        <writeable/>
        <array>2 2</array>
        <mssAccessorName>eff_dram_dll_reset</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_DLL_PPD</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            DLL Precharge PD.
            Used in various locations and is computed in mss_eff_cnfg.
            Each memory channel will have a value.
            creator: mss_eff_cnfg
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>SLOWEXIT = 0, FASTEXIT = 1</enum>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_dram_dll_ppd</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_DLL_ENABLE</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            DLL Enable.
            Used in various locations and is computed in mss_eff_cnfg.
            Each memory channel will have a value.
            creator: mss_eff_cnfg
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>YES = 1, NO = 0</enum>
        <default>YES</default>
        <writeable/>
        <array>2 2</array>
        <mssAccessorName>eff_dram_dll_enable</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_WR_LVL_ENABLE</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            Write Level Enable.
            Used in various locations and is computed in mss_eff_cnfg.
            Each memory channel will have a value.
            creator: mss_eff_cnfg
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>DISABLE = 0, ENABLE = 1</enum>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_dram_wr_lvl_enable</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_OUTPUT_BUFFER</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            DRAM Qoff.
            Enables or disables DRAM output.
            Used in various locations and is computed in mss_eff_cnfg.
            Each memory channel will have a value.
            creator: mss_eff_cnfg
            consumer: various
            firmware notes: none</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>ENABLE = 0, DISABLE = 1</enum>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_dram_output_buffer</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_PASR</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            Partial Array Self-Refresh.
            Used in various locations and is computed in mss_eff_cnfg.
            Each memory channel will have a value.
            creator: mss_eff_cnfg
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>
            FULL = 0,
            FIRST_HALF = 1,
            FIRST_QUARTER = 2,
            FIRST_EIGHTH = 3,
            LAST_THREE_FOURTH = 4,
            LAST_HALF = 5,
            LAST_QUARTER = 6,
            LAST_EIGHTH = 7
        </enum>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_dram_pasr</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_ASR</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            Auto Self-Refresh.
            Used in various locations and is computed in mss_eff_cnfg.
            Each memory channel will have a value.
            creator: mss_eff_cnfg
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>SRT = 0, ASR = 1</enum>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_dram_asr</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_SRT</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            Self-Refresh Temperature Range.
            Used in various locations and is computed in mss_eff_cnfg.
            Each memory channel will have a value.
            creator: mss_eff_cnfg
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>NORMAL = 0, EXTEND = 1</enum>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_dram_srt</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_MPR_LOC</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            Multi Purpose Register Location.
            Used in various locations and is computed in mss_eff_cnfg.
            Each memory channel will have a value.
            creator: mss_eff_cnfg
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_mpr_loc</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_MPR_MODE</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            Multi Purpose Register Mode.
            Used in various locations and is computed in mss_eff_cnfg.
            Each memory channel will have a value.
            creator: mss_eff_cnfg
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>DISABLE = 0, ENABLE = 1</enum>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_mpr_mode</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_RC00</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            F0RC00: Global Features Control Word.For normal operation, output inversion is always enabled.
            For DIMM vendor test purpose, output inversion can be disabled.
            When disabled, register tPDM is not guaranteed to be met.
            NOTE: Default value - 0x00. Values Range from 0-8.
            00 - Normal Operation; 01 - Output Inversion Disabled; 02 - Weak Drive Enabled; 04 - A outputs disabled; 08 - B outputs disabled; So on.
            No need to calculate; User can override with desired experimental value.
            creator: mss_eff_cnfg
            consumer: mss_dram_init
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 2</array>
        <mssAccessorName>eff_dimm_ddr4_rc00</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_RC01</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            F0RC01 - Clock Driver Enable Control Word.1. Output clocks may be individually turned on or off to conserve power.
            The system must read the module SPD to determine which clock outputs are used by the module.
            The PLL remains locked on CK_t/CK_c unless the system stops the clock inputs to the DDR4RCD02 to enter the lowest power mode.
            Default value - 0x00. Values Range from 0-8. No need to calculate; User can override with desired experimental value.
            creator: mss_eff_cnfg
            consumer: mss_dram_init
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 2</array>
        <mssAccessorName>eff_dimm_ddr4_rc01</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_RC02</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            F0RC02: Timing and IBT Control Word; Default value - 0x00.
            Values Range from 0-8. No need to calculate;
            User can override with desired experimental value.
            creator: mss_eff_cnfg
            consumer: mss_dram_init
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 2</array>
        <mssAccessorName>eff_dimm_ddr4_rc02</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_RC03</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            F0RC03 - CA and CS Signals Driver Characteristics Control Word;
            Default value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 137, 1st Nibble for CS and CA.
            creator: mss_eff_cnfg
            consumer: mss_dram_init
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 2</array>
        <mssAccessorName>eff_dimm_ddr4_rc03</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_RC04</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            F0RC04 - ODT and CKE Signals Driver Characteristics Control Word;
            Default value - 0x05 (Moderate Drive).
            Values Range from 00 to 0F. Has to be picked up from SPD byte 137, 2nd Nibble for ODT and CKE.
            creator: mss_eff_cnfg
            consumer: mss_dram_init
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 2</array>
        <mssAccessorName>eff_dimm_ddr4_rc04</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_RC05</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            F0RC05 - Clock Driver Characteristics Control Word;
            Default value - 0x05 (Moderate Drive).
            Values Range from 00 to 0F. Has to be picked up from SPD byte 138, 2nd Nibble for CK.
            creator: mss_eff_cnfg
            consumer: mss_dram_init
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 2</array>
        <mssAccessorName>eff_dimm_ddr4_rc05</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_RC06_07</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            F0RC06: Command Space Control Word definition;
            Default value - 0xF0 (NOP). Values Range from 00 to F0. F0RC07 not used. RDIMM
            creator: mss_eff_cnfg
            consumer: mss_dram_init
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 2</array>
        <mssAccessorName>eff_dimm_ddr4_rc06_07</mssAccessorName>
        </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_RC08</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            F0RC06: Command Space Control Word definition;
            Default value - 0x03. Values Range from 00 to 08 decimal.
            Check the stack height and calculate dynamically;
            00 = Stack height_8; 01 = Stack height_4;
            02 = Stack height_2;
            creator: mss_eff_cnfg
            consumer: mss_dram_init
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 2</array>
        <mssAccessorName>eff_dimm_ddr4_rc08</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_RC09</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F0RC06: Command Space Control Word definition;  Default value - 0xF0 (NOP). Values Range from 00 to F0. No need to calculate; User can override with desired experimental value.
        creator: mss_eff_cnfg
        consumer: mss_dram_init
        firmware notes: none</description>
    <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 2</array>
        <mssAccessorName>eff_dimm_ddr4_rc09</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_RC0A</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>RDIMM Operating Speed;  Read from ATTR_MSS_FREQ; Default value - 00. Values Range from 00 to 09. No need to calculate; User can override with desired experimental value.
        creator: mss_eff_cnfg
        consumer: mss_dram_init
        firmware notes: none</description>
    <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 2</array>
        <mssAccessorName>eff_dimm_ddr4_rc0a</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_RC0B</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>Operating Voltage VDD and VrefCA Source Control Word; Read from ATTR_MSS_VOLT_VDDR. Default value - 14. Values Range from 00 to 15 decimal.  No need to calculate; User can override with desired experimental value.
        creator: mss_eff_cnfg
        consumer: mss_dram_init
        firmware notes: none</description>
    <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 2</array>
        <mssAccessorName>eff_dimm_ddr4_rc0b</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_RC0C</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F0RC0C - Training Control Word; Default value - 00. Values Range from 00 to 07 decimal.No need to calculate; User can override with desired experimental value.
        creator: mss_eff_cnfg
        consumer: mss_dram_init
        firmware notes: none</description>
    <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 2</array>
        <mssAccessorName>eff_dimm_ddr4_rc0c</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_RC0D</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F0RC0D - DIMM Configuration Control Word; Default value - 0B. Values Range from 00 to 15 decimal. Dynamically calculated using 4 bits[0:3] Bit 0 - Address Mirroring; Bit 1 - Rdimm(1)/Lrdimm (0) ; Bit 2 - N/A ; Bit 3 - CS Mode (Direct / Quad CS mode etc);
        creator: mss_eff_cnfg
        consumer: mss_dram_init
        firmware notes: none</description>
    <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 2</array>
        <mssAccessorName>eff_dimm_ddr4_rc0d</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_RC0E</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F0RC0E - Parity Control Word;  Default value - 00. Check from ATTR_EFF_CA_PARITY and assign; Values Range from 00 to 0F.
        creator: mss_eff_cnfg
        consumer: mss_dram_init
        firmware notes: none</description>
    <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 2</array>
        <mssAccessorName>eff_dimm_ddr4_rc0e</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_RC0F</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F0RC0F - Command Latency Adder Control Word;  Default value - 04. Values Range from 00 to 04. No need to calculate; User can override with desired experimental value.
        creator: mss_eff_cnfg
        consumer: mss_dram_init
        firmware notes: none</description>
    <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 2</array>
        <mssAccessorName>eff_dimm_ddr4_rc0f</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_RC_1x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F0RC1x - Internal VrefCA Control Word; Default value - 00. Values Range from 00 to 3F.No need to calculate; User can override with desired experimental value.
        creator: mss_eff_cnfg
        consumer: mss_dram_init
        firmware notes: none</description>
    <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 2</array>
        <mssAccessorName>eff_dimm_ddr4_rc_1x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_RC_2x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F0RC2x: I2C Bus Control Word; Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value.
        creator: mss_eff_cnfg
        consumer: mss_dram_init
        firmware notes: none</description>
    <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 2</array>
        <mssAccessorName>eff_dimm_ddr4_rc_2x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_RC_3x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F0RC3x - Fine Granularity RDIMM Operating Speed;  Default value = (Operating Freq - 1250)/20. Values Range from 00 to 61 Hex.
        creator: mss_eff_cnfg
        consumer: mss_dram_init
        firmware notes: none</description>
    <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 2</array>
        <mssAccessorName>eff_dimm_ddr4_rc_3x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_RC_4x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F0RC4x: CW Source Selection Control Word; Default value - 00. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value.
        creator: mss_eff_cnfg
        consumer: mss_dram_init
        firmware notes: none</description>
    <initToZero></initToZero>
       <valueType>uint8</valueType>
       <writeable/>
       <array> 2 2</array>
       <mssAccessorName>eff_dimm_ddr4_rc_4x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_RC_5x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F0RC5x: CW Destination Selection and Write/Read Additional QxODT[1:0] Signal High; Default value - 00. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value.
        creator: mss_eff_cnfg
        consumer: mss_dram_init
        firmware notes: none</description>
    <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 2</array>
        <mssAccessorName>eff_dimm_ddr4_rc_5x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_RC_6x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F0RC6x: CW Data Control Word;  Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value.
        creator: mss_eff_cnfg
        consumer: mss_dram_init
        firmware notes: none</description>
    <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 2</array>
        <mssAccessorName>eff_dimm_ddr4_rc_6x</mssAccessorName>
    </attribute>

    <attribute>
       <id>ATTR_EFF_DIMM_DDR4_RC_7x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F0RC7x: IBT Control Word; Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value.
        creator: mss_eff_cnfg
        consumer: mss_dram_init
        firmware notes: none</description>
    <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 2</array>
        <mssAccessorName>eff_dimm_ddr4_rc_7x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_RC_8x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F0RC8x: ODT Input Buffer/IBT, QxODT Output Buffer and Timing Control Word;  Default value - 00. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value.
        creator: mss_eff_cnfg
        consumer: mss_dram_init
        firmware notes: none</description>
    <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 2</array>
        <mssAccessorName>eff_dimm_ddr4_rc_8x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_RC_9x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F0RC9x1: QxODT[1:0] Write Pattern Control Word; Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value.
        creator: mss_eff_cnfg
        consumer: mss_dram_init
        firmware notes: none</description>
    <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 2</array>
        <mssAccessorName>eff_dimm_ddr4_rc_9x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_RC_Ax</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
          F0RCAx1: QxODT[1:0] Read Pattern Control Word; Default value - 00.
          Values Range from 00 to FF. No need to calculate;
          User can override with desired experimental value.
          creator: mss_eff_cnfg
          consumer: mss_dram_init
          firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 2</array>
        <mssAccessorName>eff_dimm_ddr4_rc_ax</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_RC_Bx</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
          F0RCBx: IBT and MRS Snoop Control Word;  Default value - 07.
          Values Range from 00 to FF. No need to calculate;
          User can override with desired experimental value.
          creator: mss_eff_cnfg
          consumer: mss_dram_init
          firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 2</array>
        <mssAccessorName>eff_dimm_ddr4_rc_bx</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_RCD_MIRROR_MODE</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
          RCD Mirroring. Used in mss_dram_init and is computed in mss_eff_cnfg.
            Each memory channel will have a value.
            creator: mss_eff_cnfg
            consumer: mss_dram_init
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>OFF = 0, ON = 1</enum>
        <writeable/>
        <array> 2 2</array>
        <mssAccessorName>eff_dimm_rcd_mirror_mode</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_SCHMOO_MODE</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>Specifies the schmoo mode to use during draminit_train_adv.</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>FAST = 0, ONE_SLOW = 1, QUARTER_SLOW = 2, HALF_SLOW = 3, FULL_SLOW = 4, ONE_CHAR = 5, QUARTER_CHAR = 6, HALF_CHAR = 7, FULL_CHAR = 8</enum>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_schmoo_mode</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_SCHMOO_ADDR_MODE</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>Specifies the schmoo mode to use during draminit_train_adv</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>FEW_ADDR= 0, QUARTER_ADDR = 1, HALF_ADDR = 2, FULL_ADDR = 3</enum>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_schmoo_addr_mode</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_SCHMOO_TEST_VALID</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>Specifies the schmoo test to run during draminit_train_adv. Bit wise.</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>
            NONE = 0x00,
            MCBIST = 0x01,
            WR_EYE = 0x02,
            RD_EYE = 0x04,
            WR_DQS = 0x08,
            RD_DQS = 0x10
        </enum>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_schmoo_test_valid</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_SCHMOO_PARAM_VALID</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>Specifies the schmoo parameters to use during draminit_train_adv. Bit wise.</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>
            PARAM_NONE = 0x00,
             DELAY_REG = 0x01,
             DRV_IMP = 0x02,
             SLEW_RATE = 0x04,
             WR_VREF = 0x08,
             RD_VREF = 0x10,
             RCV_IMP = 0x20
         </enum>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_schmoo_param_valid</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_SCHMOO_WR_EYE_MIN_MARGIN</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_schmoo_wr_eye_min_margin</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_SCHMOO_RD_EYE_MIN_MARGIN</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_schmoo_rd_eye_min_margin</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_SCHMOO_DQS_CLK_MIN_MARGIN</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_schmoo_dqs_clk_min_margin</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_SCHMOO_RD_GATE_MIN_MARGIN</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_schmoo_rd_gate_min_margin</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_SCHMOO_ADDR_CMD_MIN_MARGIN</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_schmoo_addr_cmd_min_margin</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_MEMCAL_INTERVAL</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>Specifies the memcal interval in clocks.</description>
        <initToZero></initToZero>
        <valueType>uint32</valueType>
        <enum>DISABLE = 0</enum>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_memcal_interval</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_ZQCAL_INTERVAL</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>Specifies the zqcal interval in clocks.</description>
        <initToZero></initToZero>
        <valueType>uint32</valueType>
        <enum>DISABLE = 0</enum>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_zqcal_interval</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_IBM_TYPE</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>Specifies the memory topology type. See centaur workbook.</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>
            UNDEFINED = 0,
            TYPE_1A = 1,
            TYPE_1B = 2,
            TYPE_1C = 3,
            TYPE_1D = 4,
            TYPE_2A = 5,
            TYPE_2B = 6,
            TYPE_2C = 7,
            TYPE_3A = 8,
            TYPE_3B = 9,
            TYPE_3C = 10,
            TYPE_4A = 11,
            TYPE_4B = 12,
            TYPE_4C = 13,
            TYPE_5A = 14,
            TYPE_5B = 15,
            TYPE_5C = 16,
            TYPE_5D = 17,
            TYPE_6A = 18,
            TYPE_6B = 19,
            TYPE_6C = 20,
            TYPE_7A = 21,
            TYPE_7B = 22,
            TYPE_7C = 23,
            TYPE_8A = 24,
            TYPE_8B = 25,
            TYPE_8C = 26
        </enum>
        <writeable/>
        <array> 2 2</array>
        <mssAccessorName>eff_ibm_type</mssAccessorName>
    </attribute>

    <attribute>
      <id>ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM</id>
      <targetType>TARGET_TYPE_MCS</targetType>
      <description>
        Specifies the number of master ranks per DIMM.
        Represents the number of physical ranks on a DIMM.
        From SPD spec JEDEC Standard No. 21-C: Page 4.1.2.L-4.
        Byte 12 (Bits 5~3) Number of package ranks per DIMM.
        Package ranks per DIMM refers to the collections of devices
        on the module sharing common chip select signals.
      </description>
      <initToZero></initToZero>
      <valueType>uint8</valueType>
      <enum>
        1R = 1, 2R = 2, 4R = 4, 8R = 8
      </enum>
      <writeable/>
      <array> 2 2</array>
      <mssAccessorName>eff_num_master_ranks_per_dimm</mssAccessorName>
    </attribute>

    <attribute>
      <id>ATTR_EFF_DIMM_RANKS_CONFIGED</id>
      <targetType>TARGET_TYPE_MCS</targetType>
      <description>
        Bit wise representation of master ranks in each DIMM that are used for reads and writes.
        Used by PRD.
      </description>
      <initToZero></initToZero>
      <valueType>uint8</valueType>
      <writeable/>
      <array> 2 2</array>
      <mssAccessorName>eff_dimm_ranks_configed</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_PRIM_DIE_COUNT</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>Specifies the number of DRAM dies per package.</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 2</array>
        <mssAccessorName>eff_prim_die_count</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_MSS_MEM_THROTTLED_N_COMMANDS_PER_PORT</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
          This is the throttled N commands per window
          of M DRAM clocks setting for cfg_nm_n_per_port.
        </description>
        <initToZero></initToZero>
        <valueType>uint16</valueType>
        <writeable/>
        <array>2</array>
        <mssAccessorName>mem_throttled_n_commands_per_port</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_MSS_MEM_PORT_POS_OF_FAIL_THROTTLE</id>
        <targetType>TARGET_TYPE_SYSTEM</targetType>
        <description>
          This is the fapi position of the port that failed to calculate
          memory throttles given the passed in watt target and or utilization
        </description>
        <initToZero></initToZero>
        <valueType>uint64</valueType>
        <writeable/>
        <mssAccessorName>mem_port_fail_throttle</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_MSS_MEM_M_DRAM_CLOCKS</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
          This is the throttled M DRAM clocks setting for cfg_nm_m.
          creator: mss_eff_cnfg
          consumer: mss_eff_config_thermal
          firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint32</valueType>
        <writeable/>
        <array>2</array>
        <mssAccessorName>mem_m_dram_clocks</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_MSS_MEM_THROTTLED_N_COMMANDS_PER_SLOT</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>This is the throttle numerator setting for cfg_nm_n_per_slot</description>
        <initToZero></initToZero>
        <valueType>uint16</valueType>
        <writeable/>
        <array>2</array>
        <mssAccessorName>mem_throttled_n_commands_per_slot</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_MSS_MEM_WATT_TARGET</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
          Total memory power used to throttle for each dimm
          Used to compute the throttles on the channel and/or dimms for OCC
          OCC sets after IPL
          creator: mss_eff_config
          consumer: mss_bulk_pwr_throttle, mss_utils_to_throttle
          firmware notes: none.
        </description>
        <initToZero></initToZero>
        <mssUnit>cW</mssUnit>
        <valueType>uint32</valueType>
        <writeable/>
        <array>2 2</array>
        <mssAccessorName>mem_watt_target</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_MSS_TOTAL_PWR_SLOPE</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            VDDR+VPP Power slope value for dimm
            creator: mss_eff_config
            consumer: mss_bulk_pwr_throttles
        </description>
        <initToZero></initToZero>
        <valueType>uint16</valueType>
        <writeable/>
        <array> 2 2</array>
        <mssAccessorName>total_pwr_slope</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_MSS_TOTAL_PWR_INTERCEPT</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            VDDR+VPP Power intercept value for dimm
            creator: mss_eff_config
            consumer: mss_bulk_pwr_throttles
        </description>
        <initToZero></initToZero>
        <valueType>uint16</valueType>
        <writeable/>
        <array> 2 2</array>
        <mssAccessorName>total_pwr_intercept</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_MSS_DIMM_MAXBANDWIDTH_GBS</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>DIMM Max Bandwidth in GBs output from thermal procedures</description>
        <initToZero></initToZero>
        <valueType>uint32</valueType>
        <writeable/>
        <array> 2 2</array>
        <mssAccessorName>dimm_maxbandwidth_gbs</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_MSS_DIMM_MAXBANDWIDTH_MRS</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>DIMM Max Bandwidth in MRs output from thermal procedures</description>
        <initToZero></initToZero>
        <valueType>uint32</valueType>
        <writeable/>
        <array> 2 2</array>
        <mssAccessorName>dimm_maxbandwidth_mrs</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_MSS_CHANNEL_PAIR_MAXBANDWIDTH_GBS</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>Channel Pair Max Bandwidth in GBs output from thermal procedures</description>
        <initToZero></initToZero>
        <valueType>uint32</valueType>
        <writeable/>
        <array>2</array>
        <mssAccessorName>channel_pair_maxbandwidth_gbs</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_MSS_CHANNEL_PAIR_MAXBANDWIDTH_MRS</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>Channel Pair Max Bandwidth MRs output from thermal procedures</description>
        <initToZero></initToZero>
        <valueType>uint32</valueType>
        <writeable/>
        <array>2</array>
        <mssAccessorName>channel_pair_maxbandwidth_mrs</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_MSS_DIMM_MAXPOWER</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>DIMM Max Power output from thermal procedures</description>
        <initToZero></initToZero>
        <valueType>uint32</valueType>
        <writeable/>
        <array> 2 2</array>
        <mssAccessorName>dimm_maxpower</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_MSS_DATABUS_UTIL</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            Databus utilization per port limit used to calculate memory throttles and power limit
            creator: OCC
            consumer: mss_utils_to_throttle
        </description>
        <initToZero></initToZero>
        <valueType>uint32</valueType>
        <array>2</array>
        <writeable/>
        <mssAccessorName>databus_util</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_MSS_PORT_MAXPOWER</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>Channel Pair Max Power output from thermal procedures</description>
        <initToZero></initToZero>
        <valueType>uint32</valueType>
        <writeable/>
        <array>2</array>
        <mssAccessorName>port_maxpower</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_MSS_DIMM_THERMAL_LIMIT</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            DIMM Max Power based on a thermal limit
            Decoded from ATTR_MSS_MRW_THERMAL_POWER_LIMIT
        </description>
        <initToZero></initToZero>
        <valueType>uint32</valueType>
        <writeable/>
        <mssUnit>cW</mssUnit>
        <array> 2 2</array>
        <mssAccessorName>dimm_thermal_limit</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_MSS_RUNTIME_MEM_THROTTLED_N_COMMANDS_PER_PORT</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
          Runtime throttled N commands per
          M DRAM clocks setting for cfg_nm_n_per_port.
        </description>
        <initToZero></initToZero>
        <valueType>uint16</valueType>
        <writeable/>
        <array>2</array>
        <mssAccessorName>runtime_mem_throttled_n_commands_per_port</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_MSS_RUNTIME_MEM_M_DRAM_CLOCKS</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>Runtime for M DRAM clocks setting for cfg_nm_m</description>
        <initToZero></initToZero>
        <valueType>uint32</valueType>
        <writeable/>
        <array>2</array>
        <mssAccessorName>runtime_mem_m_dram_clocks</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_MSS_RUNTIME_MEM_THROTTLED_N_COMMANDS_PER_SLOT</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>Runtime throttle numerator setting for cfg_nm_n_per_slot</description>
        <initToZero></initToZero>
        <valueType>uint16</valueType>
        <writeable/>
        <array>2</array>
        <mssAccessorName>runtime_mem_throttled_n_commands_per_slot</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            A bit vector (per Dean's request) specifying if a DIMM is functional.
            DIMM attributes, such as SIZE, are qualified by this bit vector.
            The attribute ANDed 0x80 means port 0, DIMM 0 is functional, 0x40 means port 0, DIMM 1 is functional.
            0x08 means port 1, DIMM 0 is functional and 0x04 means port 1 DIMM 1 is functional.
            A fully populated system would have the value of 0xCC.
            Used in various locations and is computed in mss_eff_cnfg.
            Each memory channel will have a value. creator: mss_eff_cnfg consumer: various firmware notes: none
            This factors in functionality
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_dimm_functional_vector</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_LPASR</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            Low Power Auto Self-Refresh.
            This is for DDR4 MRS2.
            Computed in mss_eff_cnfg.
            Each memory channel will have a value.
            creator: mss_eff_cnfg
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>MANUAL_NORMAL =0, MANUAL_REDUCED = 1, MANUAL_EXTENDED = 2, ASR = 3</enum>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_dram_lpasr</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_MPR_PAGE</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            MPR Page Selection This is for DDR4 MRS3.
            Computed in mss_eff_cnfg.
            Each memory channel will have a value.
            creator: mss_eff_cnfg
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>PG0 = 0, PG1 = 1, PG2 = 2, PG3 = 3</enum>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_mpr_page</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_GEARDOWN_MODE</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            Gear Down Mode.
            This is for DDR4 MRS3.
            Computed in mss_eff_cnfg.
            Each memory channel will have a value.
            creator: mss_eff_cnfg
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>HALF =0, QUARTER=1</enum>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_geardown_mode</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_PER_DRAM_ACCESS</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            Per DRAM accessibility.
            This is for DDR4 MRS3.
            Computed in mss_eff_cnfg.
            Each memory channel will have a value.
            creator: mss_eff_cnfg
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>DISABLE = 0, ENABLE = 1</enum>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_per_dram_access</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_TEMP_READOUT</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            Temperature sensor readout.
            This is for DDR4 MRS3.
            Computed in mss_eff_cnfg.
            Each memory channel will have a value.
            creator: mss_eff_cnfg
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>DISABLE = 0, ENABLE = 1</enum>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_temp_readout</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_CRC_WR_LATENCY</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            write latency for CRC and DM. This is for DDR4 MRS3.
            Computed in mss_eff_cnfg.
            Each memory channel will have a value.
            creator: mss_eff_cnfg
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>4NCK = 4, 5NCK = 5, 6NCK = 6</enum>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_crc_wr_latency</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_MPR_RD_FORMAT</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            MPR READ FORMAT.
            This is for DDR4 MRS3.
            Computed in mss_eff_cnfg.
            Each memory channel will have a value.
            creator: mss_eff_cnfg
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>SERIAL = 0, PARALLEL = 1, STAGGERED = 2</enum>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_mpr_rd_format</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_MAX_POWERDOWN_MODE</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            Max Power down mode.
            This is for DDR4 MRS4.
            Computed in mss_eff_cnfg.
            Each memory channel will have a value.
            creator: mss_eff_cnfg
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>DISABLE = 0, ENABLE = 1</enum>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_max_powerdown_mode</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_INTERNAL_VREF_MONITOR</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            Internal Vref Monitor.
            This is for DDR4 MRS4.
            Computed in mss_eff_cnfg.
            Each memory channel will have a value.
            creator: mss_eff_cnfg
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>DISABLE = 0, ENABLE = 1</enum>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_internal_vref_monitor</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_CS_CMD_LATENCY</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            CS to CMD/ADDR Latency.
            This is for DDR4 MRS4.
            Computed in mss_eff_cnfg.
            Each memory channel will have a value.
            creator: mss_eff_cnfg
            consumer: various
            firmware notes: none
    </description>
    <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>DISABLE = 0, 3CYC = 3, 4CYC = 4, 5CYC = 5, 6CYC = 6, 8CYC = 8</enum>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_cs_cmd_latency</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_SELF_REF_ABORT</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            Self Refresh Abort.
            This is for DDR4 MRS4.
            Computed in mss_eff_cnfg.
            Each memory channel will have a value.
            creator: mss_eff_cnfg
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>DISABLE = 0, ENABLE = 1</enum>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_self_ref_abort</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_RD_PREAMBLE_TRAIN</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            Read Pre amble Training Mode. This is for DDR4 MRS4.
            Computed in mss_eff_cnfg. Each memory channel will have a value.
            creator: mss_eff_cnfg
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>DISABLE = 0, ENABLE = 1</enum>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_rd_preamble_train</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_RD_PREAMBLE</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            Read Pre amble. This is for DDR4 MRS4.
            Computed in mss_eff_cnfg. Each memory channel will have a value.
            creator: mss_eff_cnfg
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>1NCLK = 0, 2NCLK = 1</enum>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_rd_preamble</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_WR_PREAMBLE</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            Write Pre amble. This is for DDR4 MRS4.
            Computed in mss_eff_cnfg. Each memory channel will have a value.
            creator: mss_eff_cnfg
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>1NCLK = 0, 2NCLK = 1</enum>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_wr_preamble</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_CA_PARITY_LATENCY</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            C/A Parity Latency Mode. This is for DDR4 MRS5.
            Computed in mss_eff_cnfg. Each memory channel will have a value.
            creator: mss_eff_cnfg
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>DISABLE = 0, PL4 = 4, PL5 = 5, PL6 = 6, PL8 = 8</enum>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_ca_parity_latency</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_CRC_ERROR_CLEAR</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            CRC Error Clear. This is for DDR4 MRS5.
            Computed in mss_eff_cnfg. Each memory channel will have a value.
            creator: mss_eff_cnfg
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>CLEAR = 0, ERROR = 1</enum>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_crc_error_clear</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_CA_PARITY_ERROR_STATUS</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            C/A Parity Error Status. This is for DDR4 MRS5.
            Computed in mss_eff_cnfg. Each memory channel will have a value.
            creator: mss_eff_cnfg
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>CLEAR = 0, ERROR = 1</enum>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_ca_parity_error_status</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_ODT_INPUT_BUFF</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            ODT Input Buffer during power down. This is for DDR4 MRS5.
            Computed in mss_eff_cnfg. Each memory channel will have a value.
            creator: mss_eff_cnfg
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>ACTIVATED = 0, DEACTIVATED = 1</enum>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_odt_input_buff</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_CA_PARITY</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            CA Parity Persistance Error. This is for DDR4 MRS5.
            Computed in mss_eff_cnfg. Each memory channel will have a value.
            creator: mss_eff_cnfg
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>DISABLE = 0, ENABLE = 1</enum>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_ca_parity</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DATA_MASK</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            Data Mask. This is for DDR4 MRS5.
            Computed in mss_eff_cnfg. Each memory channel will have a value.
            creator: mss_eff_cnfg
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>DISABLE = 0, ENABLE = 1</enum>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_data_mask</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_WRITE_DBI</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            Write DBI. This is for DDR4 MRS5.
            Computed in mss_eff_cnfg. Each memory channel will have a value.
            creator: mss_eff_cnfg
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>DISABLE = 0, ENABLE = 1</enum>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_write_dbi</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_READ_DBI</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            Read DBI. This is for DDR4 MRS5.
            Computed in mss_eff_cnfg. Each memory channel will have a value.
            creator: mss_eff_cnfg
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>DISABLE = 0, ENABLE = 1</enum>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_read_dbi</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_VREF_DQ_TRAIN_VALUE</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            vrefdq_train value. This is for DDR4 MRS6.
            Computed in mss_eff_cnfg. Each memory channel will have a value.
            Creator: mss_eff_cnfg
            Consumer:various
            Firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 2 4</array>
        <mssAccessorName>eff_vref_dq_train_value</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_VREF_DQ_TRAIN_RANGE</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            vrefdq_train range. This is for DDR4 MRS6.
            Computed in mss_eff_cnfg. Each memory channel will have a value.
            Creator: mss_eff_cnfg
            Consumer:various
            Firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>RANGE1 = 0, RANGE2 = 1</enum>
        <writeable/>
        <array> 2 2 4</array>
        <mssAccessorName>eff_vref_dq_train_range</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_VREF_DQ_TRAIN_ENABLE</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            vrefdq_train enable. This is for DDR4 MRS6.
            Computed in mss_eff_cnfg. Each memory channel will have a value.
            Creator: mss_eff_cnfg
            Consumer:various
            Firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>DISABLE = 0, ENABLE = 1</enum>
        <writeable/>
        <array> 2 2 4</array>
        <mssAccessorName>eff_vref_dq_train_enable</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_WRITE_CRC</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            Write CRC control for DDR4 in MRS2.
            Set in mss_eff_cnfg.
            Each memory channel will have a value.
            Creator: mss_eff_cnfg
            Consumer:various
            Firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>DISABLE = 0, ENABLE = 1</enum>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_write_crc</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_MSS_CAL_STEP_ENABLE</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            A bit map of vector denoting valid cal steps to run (0 is left most bit)
            [0] EXT_ZQCAL
            [1] WR_LEVEL
            [2] DQS_ALIGN
            [3] RDCLK_ALIGN
            [4] READ_CTR
            [5] READ_CTR_2D_VREF
            [6] WRITE_CTR
            [7] WRITE_CTR_2D_VREF
            [8] COARSE_WR
            [9] COARSE_RD
            [10]:[15] Reserved for future use
            COARSE_WR and COARSE_RD  will be consumed together to form COARSE_LVL.
        </description>
        <initToZero></initToZero>
        <valueType>uint16</valueType>
        <writeable/>
        <array>2</array>
        <mssAccessorName>cal_step_enable</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_MSS_VREF_CAL_ENABLE</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            A bit vector denoting bits in every DP16 on the port to be calibrated.
            That is, all of the set bits will be calibrated for all DP16. A value
            of zero indicates the calibration should not be run.
        </description>
        <initToZero></initToZero>
        <valueType>uint16</valueType>
        <writeable/>
        <array>2</array>
        <mssAccessorName>vref_cal_enable</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_MSS_CAL_ABORT_ON_ERROR</id>
        <targetType>TARGET_TYPE_SYSTEM</targetType>
        <description>
          Whether or not to abort on the first DDR PHY calibration error.
          Firmware should always have this set to NO. YES can be used in the
          lab for troubleshooting, screening, etc.
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <enum>NO = 0, YES = 1</enum>
        <mssAccessorName>cal_abort_on_error</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_MSS_SLEW_RATE_DATA</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            The 4 bit result of running the slew calibration algorithm at various rates and impedances.
            The first dimension is port, the second is the impedance of 24,30,34, and 40 Ohms.
            The 3rd dimension is the rate: 3,4,5 or 6 V/ns.
            Computed and sent to the correct data blocks in phy_reset.
            Also used in advanced training
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 4 4</array>
        <mssAccessorName>slew_rate_data</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_MSS_SLEW_RATE_ADR</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            The 4 bit result of running the slew calibration algorithm at various rates and impedances.
            The first dimension is the port.  The second is the impedance of 15, 20, 30 and 40 Ohms.
            The 3rd dimension is the rate:3, 4,5 or 6 V/ns.
            Computed and sent to the correct data blocks in phy_reset.
            Also used in advanced training
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 4 4</array>
        <mssAccessorName>slew_rate_adr</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_SCHMOO_MULTIPLE_SETUP_CALL</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>MCBIST for multiple setup</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array>2</array>

        <mssAccessorName>schmoo_multiple_setup_call</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_BUFFER_LATENCY</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            Additional buffer latency in the case of RDIMMs and LRDIMMs.
            It is expected that this value will come from the VPD
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_buffer_latency</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_LRDIMM_WORD_X</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>Additional buffer control word for LRDIMM building of the BCW</description>
        <initToZero></initToZero>
        <valueType>uint64</valueType>
        <writeable/>
        <array> 2 2</array>
        <mssAccessorName> eff_lrdimm_word_x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_LRDIMM_MR12_REG</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            LRDIMM MR1,2 register.
            DRAM Rtt_WR for all ranks, DRAM Rtt_Nom for ranks 0 and 1, DRAM driver impedance for all ranks.
            Eff config should set this up.
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 2</array>
        <mssAccessorName>lrdimm_mr12_reg</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_LRDIMM_ADDITIONAL_CNTL_WORDS</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            LRDIMM additional RCD control words as set by DIMM SPD:
            F[3,4]RC0A, F[3,4]RC0B, F[5,6]RC0A, F[5,6]RC0B, F[7,8]RC0A, F[7,8]RC0B, F[9,10]RC0A, F[9,10]RC0B,
            F[1]RC8, F[3]RC9, F[3]RC8, F[1]RC0B, F[1]RC0C, F[1]RC0D, F[1]RC0E, F[1]RC0F.
            Eff config should set this up
        </description>
        <initToZero></initToZero>
        <valueType>uint64</valueType>
        <writeable/>
        <array> 2 2</array>
        <mssAccessorName>lrdimm_additional_cntl_words</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_LRDIMM_RANK_MULT_MODE</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
          LRDIMM rank multiplication mode.
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>NORMAL = 0, 2X_MULT = 2, 4X_MULT = 4</enum>
        <writeable/>
        <array>2</array>
        <mssAccessorName>lrdimm_rank_mult_mode</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_MSS_EFF_VPD_VERSION</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
        The lowest VPD Version of the DIMMs attached to the MBA. Comes directly (in ASCII) of the VINI VZ keyword
    </description>
    <initToZero></initToZero>
        <valueType>uint32</valueType>
        <writeable/>
        <array>2</array>
        <mssAccessorName>eff_vpd_version</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_MSS_VOLT_OVERRIDE</id>
        <targetType>TARGET_TYPE_MCBIST</targetType>
        <description>
          Possible DRAM voltage override.
          Firmware notes: Default should be NONE (0x00).
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>NONE = 0x00, VOLT_120 = 0x02</enum>
        <writeable/>
        <mssAccessorName>volt_override</mssAccessorName>
    </attribute>

   <attribute>
        <id>ATTR_MSS_VDDR_OVERIDE_SPD</id>
        <targetType>TARGET_TYPE_SYSTEM</targetType>
        <description>Possible VDDR voltage override.</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>NONE = 0x00, VOLT_1350 = 0x01, VOLT_1200 = 0x02</enum>
        <writeable/>
        <mssAccessorName>vddr_overide_spd</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_MSS_VMEM_REGULATOR_MAX_DIMM_COUNT</id>
        <targetType>TARGET_TYPE_SYSTEM</targetType>
        <description>Maximum number of installed DIMMs per VMEM regulator for all VMEM regulators in the system.</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <mssAccessorName>vmem_regulator_max_dimm_count</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_MSS_VREF_DAC_NIBBLE</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>Value for VREF DAC nibble</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 </array>
        <mssAccessorName>vref_dac_nibble</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_MSS_VCCD_OVERRIDE</id>
        <targetType>TARGET_TYPE_SYSTEM</targetType>
        <description>Whether or not to override VCCD. Defaults to no.</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>NO = 0, YES = 1</enum>
        <writeable/>
        <mssAccessorName>vccd_override</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_MAC</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
          Maximum Activate Count. Used in various locations and is computed in mss_eff_cnfg.
          creator: mss_eff_cnfg
          consumer: various
          firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint16</valueType>
        <enum>UNTESTED = 0, 700K = 700, 600K = 600, 500K = 500, 400K = 400, 300K = 300, 200K = 200,  UNLIMITED = 8</enum>
        <writeable/>
        <array>2 2</array>
        <mssAccessorName>eff_dram_mac</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_MODULE_BUS_WIDTH</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            Module Memory Bus Width.
            Used in various locations and is evaluated in mss_eff_cnfg.
            creator: mss_eff_cnfg
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <mssUnit>bits</mssUnit>
        <valueType>uint8</valueType>
        <writeable/>
        <array>2 2</array>
        <mssAccessorName>eff_dram_module_bus_width</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_RTT_NOM</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            RTT_NOM value read to be programmed into MRS02
            For RDIMMS, this is based off of the VPD
            For LRDIMMS, this comes from the SPD
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 4</array>
        <mssAccessorName>eff_dram_rtt_nom</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_RTT_WR</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            RTT_WR value read to be programmed into MRS02
            For RDIMMS, this is based off of the VPD
            For LRDIMMS, this comes from the SPD
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 4</array>
        <mssAccessorName>eff_dram_rtt_wr</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_RTT_PARK</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            RTT_PARK value read to be programmed into MRS05
            For RDIMMS, this is based off of the VPD
            For LRDIMMS, this comes from the SPD
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 4</array>
        <mssAccessorName>eff_dram_rtt_park</mssAccessorName>
    </attribute>


    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_BC00</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F0BCW00 Host Interface DQ RTT_NOM Control</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_bc00</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_BC01</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F0BCW01 Host Interface DQ RTT_WR Control</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_bc01</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_BC02</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F0BCW02 Host Interface DQ RTT_PARK Control</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_bc02</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_BC03</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F0BCW03 Host Interface DQ Driver Control Word</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_bc03</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_BC04</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F0BCW04 DRAM Interface MDQ RTT Control Word</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_bc04</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_BC05</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F0BCW05 DRAM Interface MDQ Driver Control Word</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_bc05</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_BC06</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F0BCW06 Command Space Control Word</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_bc06</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_BC07</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F0BCW07 Rank Presence Control Word</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_bc07</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_BC08</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F0BCW08 RankSelection Control Word</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_bc08</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_BC09</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F0BCW09 Power Saving Settings Control Word</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_bc09</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_BC0A</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F0BCW0A LRDIMM Operating Speed </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_bc0a</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_BC0B</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F0BCW0B Operating Voltage Control Word</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_bc0b</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_BC0C</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F0BCW0C Buffer Training Mode Control Word</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_bc0c</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_BC0D</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F0BCW0D Reserved for future use</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_bc0d</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_BC0E</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F0BCW0E Parity Control Word</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_bc0e</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_BC0F</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F0BCW0F Error Status Word</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_bc0f</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F0BC1x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F0BCW1x Buffer Configuration Control Word</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f0bc1x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F30BC2x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F30BCW2x Lower Nibble DRAM Interface Receive Enable Training Control Word for ranks 0 to 3</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f30bc2x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F30BC3x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F30BCW3x Lower Nibble DRAM Interface Receive Enable Training Control Word for ranks 0 to 3</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f30bc3x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F30BC4x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F30BCW4x Lower Nibble MDQS Read Delay Control Word for ranks 0 to 3</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f30bc4x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F30BC5x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F30BCW5x Upper Nibble MDQS Read Delay Control Word for ranks 0 to 3</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f30bc5x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F0BC6x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F0BCW6x Fine Granularity Frequency Operating Speed Control Word</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f0bc6x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F70BC7x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F70BCW7x Function Space Selector Control Word</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f70bc7x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F30BC8x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F30BCW8x Lower Nibble MDQ-MDQS Write Delay Control Word for ranks 0 to 3</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f30bc8x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F30BC9x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F30BCW9x Upper Nibble MDQ-MDQS Write Delay Control Word for ranks 0 to 3</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f30bc9x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F30BCAx</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F30BCWAx Lower Nibble DRAM Interface Write Leveling Control Word for ranks 0 to 3</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f30bcax</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F30BCBx</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F30BCWBx Upper Nibble DRAM Interface Write Leveling Control Word for ranks 0 to 3</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f30bcbx</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F0BCCx</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F0BCWCx Lower/Upper Nibble Additional Cycles of DRAM Interface Receive Enable Control Word for rank 0</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f0bccx</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F0BCDx</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F0BCWDx Lower/Upper Nibble Additional Cycles of DRAM Interface Write Leveling Control Word for rank 0</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f0bcdx</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F0BCEx</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F0BCWEx Lower/Upper Nibble Additional Cycles of DRAM Interface Write Leveling Control Word for rank 0</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f0bcex</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F0BCFx</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F0BCWFx Lower/Upper Nibble Additional Cycles of DRAM Interface Write Leveling Control Word for rank 2</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f0bcfx</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F1BCCx</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F1BCWCx Lower/Upper Nibble Additional Cycles of DRAM Interface Receive Enable Control Word for rank 1</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f1bccx</mssAccessorName>
        </attribute>
        <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F1BCDx</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F1BCWDx Lower/Upper Nibble Additional Cycles of DRAM Interface Write Leveling Control Word for rank 1</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f1bcdx</mssAccessorName>
        </attribute>
        <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F1BCEx</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F1BCWEx Lower/Upper Nibble Additional Cycles of DRAM Interface Receive Enable Control Word for rank 3</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f1bcex</mssAccessorName>
        </attribute>
        <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F1BCFx</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F1BCWFx Lower/Upper Nibble Additional Cycles of DRAM Interface Write Leveling Control Word for rank 3</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f1bcfx</mssAccessorName>
        </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F4BC0x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F4BCW0x MRS0 snooped settings</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f4bc0x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F4BC1x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F4BCW1x MRS1 snooped settings</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f4bc1x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F4BC2x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F4BCW2x MRS2 snooped settings</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f4bc2x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F4BC3x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F4BCW3x MRS3 snooped settings</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f4bc3x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F4BC4x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F4BCW4x MRS4 snooped settings</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f4bc4x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F4BC5x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F4BCW5x MRS5 snooped settings</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f4bc5x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F4BC6x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F4BCW6x MRS6 snooped settings</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f4bc6x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F5BC0x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F5BCW0x Upper and Lower MPR bits[7:0] for U0</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f5bc0x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F5BC1x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F5BCW1x Upper and Lower MPR bits[15:8] for U1</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f5bc1x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F5BC2x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F5BCW2x Upper and Lower MPR bits[23:16] for U2</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f5bc2x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F5BC3x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F5BCW3x Upper and Lower MPR bits[31:24] for U3</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f5bc3x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F5BC5x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F5BCW5x Host Interface Vref Control Word</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f5bc5x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F5BC6x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F5BCW6x DRAM Interface Vref Control Word</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f5bc6x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F6BC0x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F6BCW0x Upper and Lower MPR bits[39:32] for U4</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f6bc0x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F6BC1x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F6BCW1x Upper and Lower MPR bits[47:40] for U5</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f6bc1x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F6BC2x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F6BCW2x Upper and Lower MPR bits[55:48] for U6</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f6bc2x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F6BC3x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F6BCW3x Upper and Lower MPR bits[63:56] for U7</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f6bc3x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F6BC4x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F6BCW4x Buffer Training Configuration Control Word</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f6bc4x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F6BC5x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F6BCW5x Buffer Training Status Word</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f6bc5x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F74BC8x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F74BCW8x MDQ0/4 -Read Delay Control Word for ranks 0 to 3</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f74bc8x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F74BC9x</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F74BCW9x MDQ1/5 -Read Delay Control Word for ranks 0 to 3</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f74bc9x</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F74BCAx</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F74BCWAx MDQ2/6 -Read Delay Control Word for ranks 0 to 3</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f74bcax</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F74BCBx</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F74BCWBx MDQ3/7 -Read Delay Control Word for ranks 0 to 3</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f74bcbx</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F74BCCx</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F74BCWCx MDQ0/4-MDQS Write Delay Control Word for ranks 0 to 3</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f74bccx</mssAccessorName>
    </attribute>

   <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F74BCDx</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F74BCWDx MDQ1/5-MDQS Write Delay Control Word for ranks 0 to 3</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f74bcdx</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F74BCEx</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F74BCWEx MDQ2/6-MDQS Write Delay Control Word for ranks 0 to 3</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f74bcex</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_DDR4_F74BCFx</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>F74BCWFx MDQ3/7-MDQS Write Delay Control Word for ranks 0 to 3</description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable />
        <array> 2 2 </array>
        <mssAccessorName>eff_dimm_ddr4_f74bcfx</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_RON</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            DRAM Ron.
            Used in various locations and comes from the MT keyword of the VPD
            OHM48 is for DDR4.
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>INVALID = 0, OHM34 = 34, OHM40 = 40, OHM48 = 48</enum>
        <array>2 2</array>
        <writeable/>
        <mssAccessorName>eff_dram_ron</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_TDQS</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            TDQS.
            Used in various locations and is computed in mss_eff_cnfg.
            Each memory channel will have a value.
            creator: mss_eff_cnfg
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>DISABLE = 0, ENABLE = 1</enum>
        <writeable/>
        <array> 2 </array>
        <mssAccessorName>eff_dram_tdqs</mssAccessorName>
    </attribute>

    <attribute>
      <id>ATTR_EFF_DRAM_TREFI</id>
      <targetType>TARGET_TYPE_MCS</targetType>
      <description>
        Average Refresh Interval (tREFI)
        in nck (number of clock cycles).
        This depends on MRW attribute that selects fine refresh mode (x1, x2, x4).
        From DDR4 spec (79-4A).

        For 3DS, the tREFI time to the same logical rank is defined as
        tRFC_slr1, tRFC_slr2, or tRFC_slr4.

        creator: mss_eff_config
        consumer: various
        firmware notes: none
      </description>
      <initToZero></initToZero>
      <valueType>uint16</valueType>
      <writeable/>
      <array> 2 </array>
      <mssUnits> nck </mssUnits>
      <mssAccessorName>eff_dram_trefi</mssAccessorName>
    </attribute>


    <attribute>
        <id>ATTR_EFF_DRAM_TRTP</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
          Internal Read to Precharge Delay.
          From the DDR4 spec (79-4A).
          Each memory channel will have a value.
          creator: mss_eff_cnfg_timing
          consumer: various
          firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 </array>
        <mssAccessorName>eff_dram_trtp</mssAccessorName>
    </attribute>

    <attribute>
      <id>ATTR_EFF_DRAM_TRFC_DLR</id>
      <targetType>TARGET_TYPE_MCS</targetType>
      <description>
        Minimum Refresh Recovery Delay Time (different logical ranks)
        in nck (number of clock cyles).
        Selected tRFC value (tRFC_dlr1, tRFC_dlr2, or tRFC_dlr4)
        depends on MRW attribute that selects fine refresh mode (x1, x2, x4).
        For 3DS, The tRFC time to different logical ranks are defined as tRFC_dlr
        creator: eff_config
        consumer: various
        firmware notes: none</description>
    <initToZero></initToZero>
      <valueType>uint8</valueType>
      <writeable/>
      <array> 2 </array>
      <mssUnits> nck </mssUnits>
      <mssAccessorName>eff_dram_trfc_dlr</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_TFAW_DLR</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
          Minimum Four Activate Window Delay Time
          in nck (number of clock cycles).
          For 3DS, the tFAW time to different logical ranks are defined as tFAW_dlr
          Each memory channel will have a value.
          creator: eff_cnfg
          consumer: various
          firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 </array>
        <mssUnits> nck </mssUnits>
        <mssAccessorName>eff_dram_tfaw_dlr</mssAccessorName>
    </attribute>

    <attribute>
      <id>ATTR_EFF_DRAM_TRRD_DLR</id>
      <targetType>TARGET_TYPE_MCS</targetType>
      <description>
        Minimum Activate to Activate Delay Time (different logical ranks)
        in nck (number of clock cycles).
        For 3DS, The tRRD_S time to a different logical rank is defined as tRRD_dlr.
        Each memory channel will have a value.
        creator: eff_confg
        consumer: various
        firmware notes: none
      </description>
      <initToZero></initToZero>
      <valueType>uint8</valueType>
      <writeable/>
      <array> 2 </array>
      <mssUnits> nck </mssUnits>
      <mssAccessorName>eff_dram_trrd_dlr</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_TXS</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
          Exit Self-Refresh to commands not requiring a locked DLL.
          In nck (number of clock cycles).
          Each memory channel will have a value.
          creator: eff_config
          consumer: various
          firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 </array>
        <mssUnits> nck </mssUnits>
        <mssAccessorName>eff_dram_txs</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_MSS_IGNORE_PLUG_RULES</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
          Set to IGNORE if you want to ignore the plug rules. Sometimes
          this is needed in a partial-good configuration
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <enum>NO = 0, YES = 1</enum>
        <mssUnits> bool </mssUnits>
        <mssAccessorName>ignore_plug_rules</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_MSS_MVPD_FWMS</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
          Mark store records from MPVD Lx keyword
        </description>
        <initToZero></initToZero>
        <valueType>uint32</valueType>
        <writeable/>
        <array> 2 8 </array>
        <mssAccessorName>mvpd_fwms</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_MSS_REORDER_QUEUE_SETTING</id>
        <targetType>TARGET_TYPE_MCBIST</targetType>
        <description>
            Contains the settings for write/read reorder queue
        </description>
        <default>REORDER</default>
        <initToZero></initToZero>
        <writeable/>
        <enum>REORDER = 0, FIFO = 1</enum>
        <valueType>uint8</valueType>
        <writeable/>
        <mssAccessorName>reorder_queue_setting</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_RANK_GROUP_OVERRIDE</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
          Override PHY RANK_PAIR settings. First uint16 value is for RANK_PAIR0
          register value, and second is for RANK_PAIR1. Note that DIMM1 ranks in
          a dual-drop config will be converted from Centaur canonical number
          (4,5) to correct PHY settings (2,3). Set this attribute to zero
          to use default settings.
        </description>
        <initToZero></initToZero>
        <valueType>uint16</valueType>
        <writeable/>
        <array> 2 2 </array>
        <mssAccessorName>eff_rank_group_override</mssAccessorName>
    </attribute>

</attributes>