/
dp16.H
1779 lines (1543 loc) · 73.5 KB
/
dp16.H
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/* IBM_PROLOG_BEGIN_TAG */
/* This is an automatically generated prolog. */
/* */
/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H $ */
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
/* Licensed under the Apache License, Version 2.0 (the "License"); */
/* you may not use this file except in compliance with the License. */
/* You may obtain a copy of the License at */
/* */
/* http://www.apache.org/licenses/LICENSE-2.0 */
/* */
/* Unless required by applicable law or agreed to in writing, software */
/* distributed under the License is distributed on an "AS IS" BASIS, */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
/* implied. See the License for the specific language governing */
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
///
/// @file dp16.H
/// @brief Subroutines to control the DP16 logic blocks
///
// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 2
// *HWP Consumed by: FSP:HB
#ifndef _MSS_DP16_H_
#define _MSS_DP16_H_
#include <vector>
#include <fapi2.H>
#include <p9_mc_scom_addresses.H>
#include <p9_mc_scom_addresses_fld.H>
#include <lib/utils/scom.H>
#include <lib/utils/find.H>
#include <lib/mss_attribute_accessors.H>
namespace mss
{
///
/// @brief Given a mt/s, create a PHY 'standard' bit field for that freq.
/// @param[in] i_freq the value from mss::freq for your target
/// @return uint64_t a right-aligned bitfield which can be inserted in to a buffer
///
inline uint64_t freq_bitfield_helper( const uint64_t i_freq )
{
fapi2::buffer<uint64_t> l_data(0b1000);
FAPI_DBG("freq_bitfield_helper seeing MT/s: %d", i_freq);
// Shift l_data over based on freq.
switch(i_freq)
{
// We don't support 1866 on Nimbus.
case fapi2::ENUM_ATTR_MSS_FREQ_MT1866:
l_data >>= 3;
break;
case fapi2::ENUM_ATTR_MSS_FREQ_MT2133:
l_data >>= 2;
break;
case fapi2::ENUM_ATTR_MSS_FREQ_MT2400:
l_data >>= 1;
break;
case fapi2::ENUM_ATTR_MSS_FREQ_MT2666:
l_data >>= 0;
break;
default:
FAPI_ERR("Unkown MT/s: %d", i_freq);
fapi2::Assert(false);
break;
};
return l_data;
}
// I have a dream that the PHY code can be shared among controllers. So, I drive the
// engine from a set of traits. This might be folly. Allow me to dream. BRS
///
/// @class dp16Traits
/// @brief a collection of traits associated with the PHY DP16 block
/// @tparam T fapi2::TargetType representing the PHY
///
template< fapi2::TargetType T >
class dp16Traits;
///
/// @class dp16Traits
/// @brief a collection of traits associated with the Centaur PHY
///
template<>
class dp16Traits<fapi2::TARGET_TYPE_MBA>
{
};
///
/// @class dp16Traits
/// @brief a collection of traits associated with the Nimbus PHY DP16 block
///
template<>
class dp16Traits<fapi2::TARGET_TYPE_MCA>
{
public:
// Number of DP instances
static constexpr uint64_t DP_COUNT = 5;
// Maximum number of DRAM's per DP
static constexpr uint64_t MAX_DRAM_PER_DP = 4;
// Number of instances of the DLL per DP16. Used for checking parameters, the rest of the
// code assumes 2 DLL per DP16. There are no DLL in Centaur so we don't need to worry about
// any of this for some time.
static constexpr uint64_t DLL_PER_DP16 = 2;
// Maximum and minimum RD_VREF percentage of VDD. We only test against max and min because
// there are so many allowable values.
static constexpr uint64_t MAX_RD_VREF = fapi2::ENUM_ATTR_MSS_VPD_MT_VREF_MC_RD_VDD91875;
static constexpr uint64_t MIN_RD_VREF = fapi2::ENUM_ATTR_MSS_VPD_MT_VREF_MC_RD_VDD31208;
// Constants used for converting RD_VREF percentage to DAC settings, normalized to integers
static constexpr uint64_t RD_VREF_DVDD = 12;
static constexpr uint64_t RD_VREF_DAC_STEP = 6500;
// Vectors of DP16 registers. The pair represents the two DLL in per DP16
static const std::vector< uint64_t > DLL_CNFG_REG;
static const std::vector< uint64_t > RD_VREF_CAL_ENABLE_REG;
static const std::vector< uint64_t > RD_VREF_CAL_ERROR_REG;
static const std::vector< uint64_t > DATA_BIT_DIR1;
static const std::vector< uint64_t > PR_STATIC_OFFSET_REG;
static const std::vector< uint64_t > IO_TX_FET_SLICE_REG;
static const std::vector< uint64_t > IO_TX_PFET_TERM_REG;
static const std::vector< uint64_t > READ_DELAY_OFFSET_REG;
static const std::vector< std::pair<uint64_t, uint64_t> > DLL_CNTRL_REG;
static const std::vector< std::pair<uint64_t, uint64_t> > DLL_DAC_LOWER_REG;
static const std::vector< std::pair<uint64_t, uint64_t> > DLL_DAC_UPPER_REG;
static const std::vector< std::pair<uint64_t, uint64_t> > DLL_SLAVE_LOWER_REG;
static const std::vector< std::pair<uint64_t, uint64_t> > DLL_SLAVE_UPPER_REG;
static const std::vector< std::pair<uint64_t, uint64_t> > DLL_EXTRA_REG;
static const std::vector< std::pair<uint64_t, uint64_t> > DLL_SW_CNTRL_REG;
static const std::vector< std::pair<uint64_t, uint64_t> > DLL_VREG_COARSE_REG;
static const std::vector< std::pair<uint64_t, uint64_t> > DLL_VREG_CNTRL_REG;
static const std::vector< std::pair<uint64_t, uint64_t> > AC_BOOST_CNTRL_REG;
static const std::vector< std::pair<uint64_t, uint64_t> > CTLE_CNTRL_REG;
static const std::vector< std::pair<uint64_t, uint64_t> > RD_VREF_CNTRL_REG;
static const std::vector<std::vector<std::pair<uint64_t, uint64_t>>> BIT_DISABLE_REG;
//WR VREF registers
static const std::vector< uint64_t > WR_VREF_CONFIG0_REG;
static const std::vector< uint64_t > WR_VREF_CONFIG1_REG;
static const std::vector< uint64_t > WR_VREF_STATUS0_REG;
static const std::vector< uint64_t > WR_VREF_STATUS1_REG;
static const std::vector< std::pair<uint64_t, uint64_t> > WR_VREF_ERROR_MASK_REG;
static const std::vector< std::pair<uint64_t, uint64_t> > WR_VREF_ERROR_REG;
static const std::vector< std::pair<uint64_t, uint64_t> > WR_VREF_VALUE_RP0_REG;
static const std::vector< std::pair<uint64_t, uint64_t> > WR_VREF_VALUE_RP1_REG;
static const std::vector< std::pair<uint64_t, uint64_t> > WR_VREF_VALUE_RP2_REG;
static const std::vector< std::pair<uint64_t, uint64_t> > WR_VREF_VALUE_RP3_REG;
enum
{
DLL_CNTL_INIT_RXDLL_CAL_RESET = MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_INIT_RXDLL_CAL_RESET,
FLUSH = MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0_01_FLUSH,
INIT_IO = MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0_01_INIT_IO,
ADV_PP = MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0_01_ADVANCE_PING_PONG,
DELAY_PP_HALF = MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0_01_DELAY_PING_PONG_HALF,
DISABLE_PING_PONG = MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0_01_DISABLE_PING_PONG,
TSYS_DATA = MCA_DDRPHY_DP16_WRCLK_PR_P0_0_01_TSYS,
TSYS_DATA_LEN = MCA_DDRPHY_DP16_WRCLK_PR_P0_0_01_TSYS_LEN,
// Seriously PHY guys?
AC_BOOST_WR_DOWN = MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICENDRV_DC,
AC_BOOST_WR_DOWN_LEN = MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICENDRV_DC_LEN,
AC_BOOST_WR_UP = MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICEPDRV_DC,
AC_BOOST_WR_UP_LEN = MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICEPDRV_DC_LEN,
AC_BOOST_RD_UP = MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICEPTERM_DC,
AC_BOOST_RD_UP_LEN = MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICEPTERM_DC_LEN,
CTLE_EVEN_CAP = MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_DQSEL_CAP,
CTLE_EVEN_CAP_LEN = MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_DQSEL_CAP_LEN,
CTLE_EVEN_RES = MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_DQSEL_RES,
CTLE_EVEN_RES_LEN = MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_DQSEL_RES_LEN,
CTLE_ODD_CAP = MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_DQSEL_CAP,
CTLE_ODD_CAP_LEN = MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_DQSEL_CAP_LEN,
CTLE_ODD_RES = MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_DQSEL_RES,
CTLE_ODD_RES_LEN = MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_DQSEL_RES_LEN,
RD_VREF_BYTE0_NIB0 = MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_0_01_NIB0,
RD_VREF_BYTE0_NIB0_LEN = MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_0_01_NIB0_LEN,
RD_VREF_BYTE0_NIB1 = MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_0_01_NIB1,
RD_VREF_BYTE0_NIB1_LEN = MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_0_01_NIB1_LEN,
RD_VREF_BYTE1_NIB2 = MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_0_01_NIB2,
RD_VREF_BYTE1_NIB2_LEN = MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_0_01_NIB2_LEN,
RD_VREF_BYTE1_NIB3 = MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_0_01_NIB3,
RD_VREF_BYTE1_NIB3_LEN = MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_0_01_NIB3_LEN,
IO_TX_FET_SLICE = MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_0,
IO_TX_FET_SLICE_EN_N_WR = MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_0_01_EN_N_WR,
IO_TX_FET_SLICE_EN_N_WR_LEN = MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_0_01_EN_N_WR_LEN,
IO_TX_FET_SLICE_EN_P_WR = MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_0_01_EN_P_WR,
IO_TX_FET_SLICE_EN_P_WR_LEN = MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_0_01_EN_P_WR_LEN,
IO_TX_PFET_TERM = MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_0,
IO_TX_PFET_TERM_EN_P_WR = MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_0_01_EN_P_WR,
IO_TX_PFET_TERM_EN_P_WR_LEN = MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_0_01_EN_P_WR_LEN,
////////////////////////////////////////
// WR VREF register field information //
////////////////////////////////////////
// CONFIG0
WR_VREF_CONFIG0_1D_ONLY_SWITCH = MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_1D_CHICKEN_SWITCH,
WR_VREF_CONFIG0_FULL_1D = MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_RUN_FULL_1D,
WR_VREF_CONFIG0_2D_SMALL_STEP_VAL = MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_2D_SMALL_STEP_VAL ,
WR_VREF_CONFIG0_2D_SMALL_STEP_VAL_LEN = MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_2D_SMALL_STEP_VAL_LEN,
WR_VREF_CONFIG0_2D_BIG_STEP_VAL = MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_2D_BIG_STEP_VAL,
WR_VREF_CONFIG0_2D_BIG_STEP_VAL_LEN = MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_2D_BIG_STEP_VAL_LEN,
WR_VREF_CONFIG0_NUM_BITS_TO_SKIP = MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_NUM_BITS_TO_SKIP,
WR_VREF_CONFIG0_NUM_BITS_TO_SKIP_LEN = MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_NUM_BITS_TO_SKIP_LEN,
WR_VREF_CONFIG0_NUM_NO_INC_COMP = MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_NUM_NO_INC_COMP,
WR_VREF_CONFIG0_NUM_NO_INC_COMP_LEN = MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_NUM_NO_INC_COMP_LEN,
// CONFIG1
WR_VREF_CONFIG1_CTR_RANGE_SELECT = MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_0_01_CTR_RANGE_SELECT,
WR_VREF_CONFIG1_CTR_RANGE_CROSSOVER = MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_0_01_CTR_RANGE_CROSSOVER,
WR_VREF_CONFIG1_CTR_RANGE_CROSSOVER_LEN = MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_0_01_CTR_RANGE_CROSSOVER_LEN,
WR_VREF_CONFIG1_CTR_SINGLE_RANGE_MAX = MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_0_01_CTR_SINGLE_RANGE_MAX,
WR_VREF_CONFIG1_CTR_SINGLE_RANGE_MAX_LEN = MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_0_01_CTR_SINGLE_RANGE_MAX_LEN,
// ERROR_MASK0/1 - note: all of these are one bit masks for error flags
WR_VREF_ERROR_MASK_MAX_RANGE_DRAM_EVEN = MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_MAX_RANGE ,
WR_VREF_ERROR_MASK_MIN_RANGE_DRAM_EVEN = MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_MIN_RANGE ,
WR_VREF_ERROR_MASK_TWO_RANGE_BEST_CASE_DRAM_EVEN = MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_TWO_RANGE_BEST_CASE ,
WR_VREF_ERROR_MASK_BIT_STEP_DELTA_DRAM_EVEN = MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_BIT_STEP_DELTA ,
WR_VREF_ERROR_MASK_STEP_RANGE_EDGE_DRAM_EVEN = MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_STEP_RANGE_EDGE ,
WR_VREF_ERROR_MASK_NO_INCREASE_DRAM_EVEN = MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_NO_INCREASE ,
WR_VREF_ERROR_MASK_1D_EYE_NOISE_DRAM_EVEN = MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_1D_EYE_NOISE ,
WR_VREF_ERROR_MASK_BAD_BIT_DRAM_EVEN = MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_BAD_BIT ,
WR_VREF_ERROR_MASK_MAX_RANGE_MASK_DRAM_ODD = MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_MAX_RANGE_MASK1 ,
WR_VREF_ERROR_MASK_MIN_RANGE_DRAM_ODD = MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_MIN_RANGE_MASK1 ,
WR_VREF_ERROR_MASK_TWO_RANGE_BEST_CASE_DRAM_ODD = MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_TWO_RANGE_BEST_CASE_MASK1,
WR_VREF_ERROR_MASK_BIT_STEP_DELTA_DRAM_ODD = MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_BIT_STEP_DELTA_MASK1 ,
WR_VREF_ERROR_MASK_STEP_RANGE_EDGE_DRAM_ODD = MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_STEP_RANGE_EDGE_MASK1 ,
WR_VREF_ERROR_MASK_NO_INCREASE_DRAM_ODD = MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_NO_INCREASE_MASK1 ,
WR_VREF_ERROR_MASK_1D_EYE_NOISE_DRAM_ODD = MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_1D_EYE_NOISE_MASK1 ,
WR_VREF_ERROR_MASK_BAD_BIT_DRAM_ODD = MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_BAD_BIT_MASK1 ,
// ERROR0/1 - note: all of these are one bit error flags
WR_VREF_ERROR_MAX_RANGE_DRAM_EVEN = MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_MAX_RANGE_ERR0 ,
WR_VREF_ERROR_MIN_RANGE_DRAM_EVEN = MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_MIN_RANGE_ERR0 ,
WR_VREF_ERROR_TWO_RANGE_BEST_CASE_DRAM_EVEN = MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_TWO_RANGE_BEST_CASE_ERR0 ,
WR_VREF_ERROR_BIT_STEP_DELTA_DRAM_EVEN = MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_BIT_STEP_DELTA_ERR0 ,
WR_VREF_ERROR_STEP_RANGE_EDGE_DRAM_EVEN = MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_STEP_RANGE_EDGE_ERR0 ,
WR_VREF_ERROR_NO_INCREASE_DRAM_EVEN = MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_NO_INCREASE_ERR0 ,
WR_VREF_ERROR_1D_EYE_NOISE_DRAM_EVEN = MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_1D_EYE_NOISE_ERR0 ,
WR_VREF_ERROR_BAD_BIT_DRAM_EVEN = MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_BAD_BIT_ERR0 ,
WR_VREF_ERROR_MAX_RANGE_MASK_DRAM_ODD = MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_MAX_RANGE_ERR1 ,
WR_VREF_ERROR_MIN_RANGE_DRAM_ODD = MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_MIN_RANGE_ERR1 ,
WR_VREF_ERROR_TWO_RANGE_BEST_CASE_DRAM_ODD = MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_TWO_RANGE_BEST_CASE_ERR1 ,
WR_VREF_ERROR_BIT_STEP_DELTA_DRAM_ODD = MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_BIT_STEP_DELTA_ERR1 ,
WR_VREF_ERROR_STEP_RANGE_EDGE_DRAM_ODD = MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_STEP_RANGE_EDGE_ERR1 ,
WR_VREF_ERROR_NO_INCREASE_DRAM_ODD = MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_NO_INCREASE_ERR1 ,
WR_VREF_ERROR_1D_EYE_NOISE_DRAM_ODD = MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_1D_EYE_NOISE_ERR1 ,
WR_VREF_ERROR_BAD_BIT_DRAM_ODD = MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_BAD_BIT_ERR1 ,
// STATUS0
WR_VREF_STATUS0_WRRD_CNT = MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_0_01_CTR_NUM_WRRDREQ_CNT ,
WR_VREF_STATUS0_WRRD_CNT_LEN = MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_0_01_CTR_NUM_WRRDREQ_CNT_LEN ,
// STATUS1
WR_VREF_STATUS1_VREFREQ_CNT = MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_0_01_CTR_NUM_VREFREQ_CNT ,
WR_VREF_STATUS1_VREFREQ_CNT_LEN = MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_0_01_CTR_NUM_VREFREQ_CNT_LEN ,
WR_VREF_STATUS1_CUR_VREF = MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_0_01_CTR_CUR ,
WR_VREF_STATUS1_CUR_VREF_LEN = MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_0_01_CTR_CUR_LEN,
// VALUE0/1 for all rankpairs
WR_VREF_VALUE_RANGE_DRAM_EVEN = MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0_01_RANGE_DRAM0 ,
WR_VREF_VALUE_VALUE_DRAM_EVEN = MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0_01_VALUE_DRAM0 ,
WR_VREF_VALUE_VALUE_DRAM_EVEN_LEN = MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0_01_VALUE_DRAM0_LEN ,
WR_VREF_VALUE_RANGE_DRAM_ODD = MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0_01_RANGE_DRAM1 ,
WR_VREF_VALUE_VALUE_DRAM_ODD = MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0_01_VALUE_DRAM1 ,
WR_VREF_VALUE_VALUE_DRAM_ODD_LEN = MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0_01_VALUE_DRAM1_LEN ,
// Read Delay fields.
READ_OFFSET_LOWER = MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0_01,
READ_OFFSET_LOWER_LEN = MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0_01_LEN,
READ_OFFSET_UPPER = MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0_01_OFFSET1,
READ_OFFSET_UPPER_LEN = MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0_01_OFFSET1_LEN,
// Read Diagnostic Config 5 (same bit for all MCAs)
FORCE_FIFO_CAPTURE = MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_FORCE_FIFO_CAPTURE,
};
};
///
/// @brief Given a RD_VREF value, create a PHY 'standard' bit field for that percentage.
/// @tparam T fapi2 Target Type - derived
/// @tparam TT traits type defaults to dp16Traits<T>
/// @param[in] i_target the fapi2 target of the port
/// @param[in] i_vref the value from the mss_vpd_mt_vref_mc_rd attribute for your target
/// @param[out] o_bitfield value of DAC bitfield for given VREF setting
/// @return FAPI2_RC_SUCCESS iff ok
///
template< fapi2::TargetType T, typename TT = dp16Traits<T> >
fapi2::ReturnCode rd_vref_bitfield_helper( const fapi2::Target<T>& i_target,
const uint32_t i_vref,
uint64_t& o_bitfield );
namespace dp16
{
///
/// @brief Read TSYS_DATA
/// @tparam I DP16 instance
/// @tparam T fapi2 Target Type - derived
/// @tparam TT traits type defaults to dp16Traits<T>
/// @param[in] i_target the fapi2 target of the port
/// @param[out] o_data the value of the register
/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
///
template< uint64_t I, fapi2::TargetType T, typename TT = dp16Traits<T> >
inline fapi2::ReturnCode read_tsys_data( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
{
static_assert( I < TT::DP_COUNT, "dp16 instance out of range");
FAPI_TRY( mss::getScom(i_target, TT::PR_STATIC_OFFSET_REG[I], o_data) );
FAPI_INF("tsys_data dp16%d: 0x%016lx", I, o_data);
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Write TSYS_DATA
/// @tparam I DP16 instance
/// @tparam T fapi2 Target Type - derived
/// @tparam TT traits type defaults to dp16Traits<T>
/// @param[in] i_target the fapi2 target of the port
/// @param[in] i_data the value of the register
/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
///
template< uint64_t I, fapi2::TargetType T, typename TT = dp16Traits<T> >
inline fapi2::ReturnCode write_tsys_data( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data )
{
static_assert( I < TT::DP_COUNT, "dp16 instance out of range");
FAPI_INF("tsys_data dp16%d: 0x%016lx", I, i_data);
FAPI_TRY( mss::putScom(i_target, TT::PR_STATIC_OFFSET_REG[I], i_data) );
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Reset tsys_data
/// @tparam T fapi2 Target Type - derived
/// @tparam TT traits type defaults to dp16Traits<T>
/// @param[in] i_target the fapi2 target of the port
/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
///
template< fapi2::TargetType T, typename TT = dp16Traits<T> >
inline fapi2::ReturnCode reset_tsys_data( const fapi2::Target<T>& i_target )
{
fapi2::buffer<uint64_t> l_data;
uint8_t l_tsys_data = 0;
FAPI_TRY( mss::vpd_mr_tsys_data(mss::find_target<fapi2::TARGET_TYPE_MCS>(i_target), l_tsys_data) );
l_data.insertFromRight<TT::TSYS_DATA, TT::TSYS_DATA_LEN>(l_tsys_data);
for (const auto r : TT::PR_STATIC_OFFSET_REG)
{
// TODO RTC:160358 Suspect duplicated scoms in ddr initfile
FAPI_INF("reset tsys_data 0x%016lx: 0x%016lx", r, l_data);
FAPI_TRY( mss::putScom(i_target, r, l_data) );
}
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Read DLL_CNTL
/// @tparam I DP16 instance
/// @tparam D DLL instance in the specified DP16
/// @tparam T fapi2 Target Type - derived
/// @tparam TT traits type defaults to dp16Traits<T>
/// @param[in] i_target the fapi2 target of the port
/// @param[out] o_data the value of the register
/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
///
template< uint64_t I, uint64_t D, fapi2::TargetType T, typename TT = dp16Traits<T> >
inline fapi2::ReturnCode read_dll_cntl( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
{
static_assert( I < TT::DP_COUNT, "dp16 instance out of range");
static_assert( D < TT::DLL_PER_DP16, "dll instance out of range");
// The pair represents the upper and lower bytes of the DP16 - each has its own DLL registers
const uint64_t& l_addr = (D == 0) ? TT::DLL_CNTRL_REG[I].first : TT::DLL_CNTRL_REG[I].second;
FAPI_TRY( mss::getScom(i_target, l_addr, o_data) );
FAPI_INF("dll_cntl dp16<%d, %d>: 0x%016lx", I, D, o_data);
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Write DLL_CNTL
/// @tparam I DP16 instance
/// @tparam D DLL instance in the specified DP16
/// @tparam T fapi2 Target Type - derived
/// @tparam TT traits type defaults to dp16Traits<T>
/// @param[in] i_target the fapi2 target of the port
/// @param[in] i_data the value of the register
/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
///
template< uint64_t I, uint64_t D, fapi2::TargetType T, typename TT = dp16Traits<T> >
inline fapi2::ReturnCode write_dll_cntl( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data )
{
static_assert( I < TT::DP_COUNT, "dp16 instance out of range");
static_assert( D < TT::DLL_PER_DP16, "dll instance out of range");
// The pair represents the upper and lower bytes of the DP16 - each has its own DLL registers
const uint64_t& l_addr = (D == 0) ? TT::DLL_CNTRL_REG[I].first : TT::DLL_CNTRL_REG[I].second;
FAPI_INF("dll_cntl dp16<%d,%d>: 0x%016lx", I, D, i_data);
FAPI_TRY( mss::putScom(i_target, l_addr, i_data) );
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Reset all of the DLL registers - Nimbus only
/// @param[in] i_target an MCA
/// @return FAPI2_RC_SUCCESs iff ok
///
fapi2::ReturnCode reset_dll( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target );
///
/// @brief Read AC_BOOST_CNTL
/// @tparam I DP16 instance
/// @tparam T fapi2 Target Type - derived
/// @tparam P the type of the std::pair elements
/// @tparam TT traits type defaults to dp16Traits<T>
/// @param[in] i_target the fapi2 target of the port
/// @param[out] o_data the value of both of the registers (upper and lower bytes)
/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
///
template< uint64_t I, fapi2::TargetType T, typename P, typename TT = dp16Traits<T> >
inline fapi2::ReturnCode read_ac_boost_cntl( const fapi2::Target<T>& i_target,
std::pair<P, P>& o_data )
{
static_assert( I < TT::DP_COUNT, "dp16 instance out of range");
// The pair represents the upper and lower bytes of the DP16 - each has its own boost registers
FAPI_TRY( mss::getScom(i_target, TT::AC_BOOST_CNTRL_REG[I].first, o_data.first) );
FAPI_TRY( mss::getScom(i_target, TT::AC_BOOST_CNTRL_REG[I].second, o_data.second) );
FAPI_INF("ac_boost_cntl dp16<%d>: 0x%016lx, 0x%016lx", I, o_data.first, o_data.second);
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Read AC_BOOST_CNTL
/// @tparam T fapi2 Target Type - derived
/// @tparam P the type of the std::pair elements
/// @tparam TT traits type defaults to dp16Traits<T>
/// @param[in] i_target the fapi2 target of the port
/// @param[in] i_dp the dp16 instance's index
/// @param[out] o_data the value of both of the the registers (upper and lower bytes)
/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
///
template< fapi2::TargetType T, typename P, typename TT = dp16Traits<T> >
inline fapi2::ReturnCode read_ac_boost_cntl( const fapi2::Target<T>& i_target,
const uint64_t i_dp,
std::pair<P, P>& o_data )
{
switch (i_dp)
{
case(0):
return ( read_ac_boost_cntl<0>( i_target, o_data ) );
case(1):
return ( read_ac_boost_cntl<1>( i_target, o_data ) );
case(2):
return ( read_ac_boost_cntl<2>( i_target, o_data ) );
case(3):
return ( read_ac_boost_cntl<3>( i_target, o_data ) );
case(4):
return ( read_ac_boost_cntl<4>( i_target, o_data ) );
default:
return fapi2::FAPI2_RC_INVALID_PARAMETER;
}
}
///
/// @brief Write AC_BOOST_CNTL
/// @tparam I DP16 instance
/// @tparam T fapi2 Target Type - derived
/// @tparam P the type of the std::pair elements
/// @tparam TT traits type defaults to dp16Traits<T>
/// @param[in] i_target the fapi2 target of the port
/// @param[in] i_data the value of both of the registers (upper and lower bytes)
/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
///
template< uint64_t I, fapi2::TargetType T, typename P, typename TT = dp16Traits<T> >
inline fapi2::ReturnCode write_ac_boost_cntl( const fapi2::Target<T>& i_target,
const std::pair<P, P>& i_data )
{
static_assert( I < TT::DP_COUNT, "dp16 instance out of range");
// The pair represents the upper and lower bytes of the DP16 - each has its own boost registers
FAPI_INF("ac_boost_cntl dp16<%d>: 0x%016lx, 0x%016lx", I, i_data.first, i_data.second);
FAPI_TRY( mss::putScom(i_target, TT::AC_BOOST_CNTRL_REG[I].first, i_data.first) );
FAPI_TRY( mss::putScom(i_target, TT::AC_BOOST_CNTRL_REG[I].second, i_data.second) );
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Write AC_BOOST_CNTL
/// @tparam T fapi2 Target Type - derived
/// @tparam P the type of the std::pair elements
/// @tparam TT traits type defaults to dp16Traits<T>
/// @param[in] i_target the fapi2 target of the port
/// @param[in] i_dp the dp16 instance's index
/// @param[in] i_data the value of both of the the registers (upper and lower bytes)
/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
///
template< fapi2::TargetType T, typename P, typename TT = dp16Traits<T> >
inline fapi2::ReturnCode write_ac_boost_cntl( const fapi2::Target<T>& i_target,
const uint64_t i_dp,
const std::pair<P, P>& i_data )
{
switch (i_dp)
{
case(0):
return ( write_ac_boost_cntl<0>( i_target, i_data ) );
case(1):
return ( write_ac_boost_cntl<1>( i_target, i_data ) );
case(2):
return ( write_ac_boost_cntl<2>( i_target, i_data ) );
case(3):
return ( write_ac_boost_cntl<3>( i_target, i_data ) );
case(4):
return ( write_ac_boost_cntl<4>( i_target, i_data ) );
default:
return fapi2::FAPI2_RC_INVALID_PARAMETER;
}
}
///
/// @brief Reset AC_BOOST_CNTL - for all DP16 in the target
/// @tparam T fapi2 Target Type - derived
/// @tparam TT traits type defaults to dp16Traits<T>
/// @param[in] i_target the fapi2 target of the port
/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
///
template< fapi2::TargetType T, typename TT = dp16Traits<T> >
fapi2::ReturnCode reset_ac_boost_cntl( const fapi2::Target<T>& i_target );
///
/// @brief Read CTLE
/// @tparam I DP16 instance
/// @tparam T fapi2 Target Type - derived
/// @tparam P the type of the std::pair elements
/// @tparam TT traits type defaults to dp16Traits<T>
/// @param[in] i_target the fapi2 target of the port
/// @param[out] o_data the value of both of the registers (upper and lower bytes)
/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
///
template< uint64_t I, fapi2::TargetType T, typename P, typename TT = dp16Traits<T> >
inline fapi2::ReturnCode read_ctle_cntl( const fapi2::Target<T>& i_target,
std::pair<P, P>& o_data )
{
static_assert( I < TT::DP_COUNT, "dp16 instance out of range");
// The pair represents the upper and lower bytes of the DP16 - each has its own boost registers
FAPI_TRY( mss::getScom(i_target, TT::CTLE_CNTRL_REG[I].first, o_data.first) );
FAPI_TRY( mss::getScom(i_target, TT::CTLE_CNTRL_REG[I].second, o_data.second) );
FAPI_INF("ctle_cntl dp16<%d>: 0x%016lx, 0x%016lx", I, o_data.first, o_data.second);
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Write CTLE
/// @tparam I DP16 instance
/// @tparam T fapi2 Target Type - derived
/// @tparam P the type of the std::pair elements
/// @tparam TT traits type defaults to dp16Traits<T>
/// @param[in] i_target the fapi2 target of the port
/// @param[in] i_data the value of both of the registers (upper and lower bytes)
/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
///
template< uint64_t I, fapi2::TargetType T, typename P, typename TT = dp16Traits<T> >
inline fapi2::ReturnCode write_ctle_cntl( const fapi2::Target<T>& i_target,
const std::pair<P, P>& i_data )
{
static_assert( I < TT::DP_COUNT, "dp16 instance out of range");
// The pair represents the upper and lower bytes of the DP16 - each has its own boost registers
FAPI_INF("ctle_cntl dp16<%d>: 0x%016lx, 0x%016lx", I, i_data.first, i_data.second);
FAPI_TRY( mss::putScom(i_target, TT::CTLE_CNTRL_REG[I].first, i_data.first) );
FAPI_TRY( mss::putScom(i_target, TT::CTLE_CNTRL_REG[I].second, i_data.second) );
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Reset CTLE - for all DP16 in the target
/// @tparam T fapi2 Target Type - derived
/// @tparam TT traits type defaults to dp16Traits<T>
/// @param[in] i_target the fapi2 target of the port
/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
///
template< fapi2::TargetType T, typename TT = dp16Traits<T> >
fapi2::ReturnCode reset_ctle_cntl( const fapi2::Target<T>& i_target );
///
/// @brief Set the DLL cal reset (begins DLL cal operations)
/// @tparam T fapi2 Target Type - defaults to TARGET_TYPE_MCA
/// @tparam TT traits type defaults to dp16Traits<T>
/// @param[out] o_data the value of the register
/// @param[in] i_state mss::LOW or mss::HIGH representing the state of the bit
/// @note Default state is 'low' as writing a 0 forces the cal to begin.
///
template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = dp16Traits<T> >
inline void set_dll_cal_reset( fapi2::buffer<uint64_t>& o_data, const states i_state = mss::LOW )
{
FAPI_INF("set_dll_cal_reset %s", (i_state == mss::LOW ? "low" : "high"));
o_data.writeBit<TT::DLL_CNTL_INIT_RXDLL_CAL_RESET>(i_state);
}
///
/// @brief Read DATA_BIT_DIR1
/// @tparam I DP16 instance
/// @tparam T fapi2 Target Type - derived
/// @tparam TT traits type defaults to dp16Traits<T>
/// @param[in] i_target the fapi2 target of the port
/// @param[out] o_data the value of the register
/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
///
template< uint64_t I, fapi2::TargetType T, typename TT = dp16Traits<T> >
inline fapi2::ReturnCode read_data_bit_dir1( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
{
static_assert( I < TT::DP_COUNT, "dp16 instance out of range");
FAPI_TRY( mss::getScom(i_target, TT::DATA_BIT_DIR1[I], o_data) );
FAPI_INF("data_bit_dir1 dp16%d: 0x%016lx", I, o_data);
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Write DATA_BIT_DIR1
/// @tparam I DP16 instance
/// @tparam T fapi2 Target Type - derived
/// @tparam TT traits type defaults to dp16Traits<T>
/// @param[in] i_target the fapi2 target of the port
/// @param[in] i_data the value of the register
/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
///
template< uint64_t I, fapi2::TargetType T, typename TT = dp16Traits<T> >
inline fapi2::ReturnCode write_data_bit_dir1( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data )
{
static_assert( I < TT::DP_COUNT, "dp16 instance out of range");
FAPI_INF("data_bit_dir1 dp16%d: 0x%016lx", I, i_data);
FAPI_TRY( mss::putScom(i_target, TT::DATA_BIT_DIR1[I], i_data) );
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Set the output flush
/// @tparam T fapi2 Target Type - defaults to TARGET_TYPE_MCA
/// @tparam TT traits type defaults to dp16Traits<T>
/// @param[out] o_data the value of the register
/// @param[in] i_state mss::LOW or mss::HIGH representing the state of the bit
///
template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = dp16Traits<T> >
inline void set_output_flush( fapi2::buffer<uint64_t>& o_data, const states i_state )
{
FAPI_INF("set_output_flush %s", (i_state == mss::LOW ? "low" : "high"));
o_data.writeBit<TT::FLUSH>(i_state);
}
///
/// @brief Set the init IO state
/// @tparam T fapi2 Target Type - defaults to TARGET_TYPE_MCA
/// @tparam TT traits type defaults to dp16Traits<T>
/// @param[out] o_data the value of the register
/// @param[in] i_state mss::LOW or mss::HIGH representing the state of the bit
///
template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = dp16Traits<T> >
inline void set_init_io( fapi2::buffer<uint64_t>& o_data, const states i_state )
{
FAPI_INF("set_init_io %s", (i_state == mss::LOW ? "low" : "high"));
o_data.writeBit<TT::INIT_IO>(i_state);
}
///
/// @brief Set advance_ping_pong
/// @tparam T fapi2 Target Type - defaults to TARGET_TYPE_MCA
/// @tparam TT traits type defaults to dp16Traits<T>
/// @param[out] o_data the value of the register
/// @param[in] i_state mss::LOW or mss::HIGH representing the state of the bit
///
template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = dp16Traits<T> >
inline void set_adv_pp( fapi2::buffer<uint64_t>& o_data, const states i_state )
{
FAPI_INF("set_adv_pp %s", (i_state == mss::LOW ? "low" : "high"));
o_data.writeBit<TT::ADV_PP>(i_state);
}
///
/// @brief Set delay ping pong half
/// @tparam T fapi2 Target Type - defaults to TARGET_TYPE_MCA
/// @tparam TT traits type defaults to dp16Traits<T>
/// @param[out] o_data the value of the register
/// @param[in] i_state mss::LOW or mss::HIGH representing the state of the bit
///
template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = dp16Traits<T> >
inline void set_delay_pp_half( fapi2::buffer<uint64_t>& o_data, const states i_state )
{
FAPI_INF("set_delay_pp_half %s", (i_state == mss::LOW ? "low" : "high"));
o_data.writeBit<TT::DELAY_PP_HALF>(i_state);
}
///
/// @brief Set the ping pong disable IO state
/// @tparam T fapi2 Target Type - defaults to TARGET_TYPE_MCA
/// @tparam TT traits type defaults to dp16Traits<T>
/// @param[in,out] io_data the value of the register
/// @param[in] i_state mss::LOW or mss::HIGH representing the state of the bit
///
template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = dp16Traits<T> >
inline void set_disable_ping_pong( fapi2::buffer<uint64_t>& io_data, const states i_state )
{
FAPI_INF("set_init_io %s", (i_state == mss::LOW ? "low" : "high"));
io_data.writeBit<TT::DISABLE_PING_PONG>(i_state);
}
///
/// @brief Get the ping pong disable IO state
/// @tparam T fapi2 Target Type - defaults to TARGET_TYPE_MCA
/// @tparam TT traits type defaults to dp16Traits<T>
/// @param[in] i_data the value of the register
/// @return value of the ping pong disable bit
///
template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = dp16Traits<T> >
inline bool get_disable_ping_pong( const fapi2::buffer<uint64_t>& i_data )
{
return i_data.getBit<TT::DISABLE_PING_PONG>();
}
///
/// @brief Configure the DP16 sysclk
/// @tparam T the fapi2 target type
/// @tparam TT the target traits
/// @param[in] i_target a target
/// @return FAPI2_RC_SUCCESs iff ok
///
template< fapi2::TargetType T, typename TT = dp16Traits<T> >
fapi2::ReturnCode reset_sysclk( const fapi2::Target<T>& i_target );
///
/// @brief Reset the training delay configureation
/// @tparam T the type of the port
/// @tparam TT the target traits
/// @param[in] i_target the port target
/// @param[in] l_rank_pairs vector of rank pairs
/// @return FAPI2_RC_SUCCES iff ok
///
template< fapi2::TargetType T, typename TT = dp16Traits<T> >
fapi2::ReturnCode reset_delay_values( const fapi2::Target<T>& i_target,
const std::vector< uint64_t >& l_rank_pairs );
///
/// @brief Reset the read clock enable registers
/// @tparam T the type of the port
/// @tparam TT the target traits
/// @param[in] i_target a port target
/// @param[in] l_rank_pairs vector of rank pairs
/// @return FAPI2_RC_SUCCES iff ok
///
template< fapi2::TargetType T, typename TT = dp16Traits<T> >
fapi2::ReturnCode reset_read_clock_enable( const fapi2::Target<T>& i_target,
const std::vector< uint64_t >& l_rank_pairs );
///
/// @brief Resets the write clock enable registers
/// @tparam T the type of the port
/// @tparam TT the target traits
/// @param[in] i_target a port target
/// @param[in] l_rank_pairs vector of rank pairs
/// @return FAPI2_RC_SUCCES iff ok
///
template< fapi2::TargetType T, typename TT = dp16Traits<T> >
fapi2::ReturnCode reset_write_clock_enable( const fapi2::Target<T>& i_target,
const std::vector< uint64_t >& l_rank_pairs );
///
/// @brief Reset the data bit enable registers
/// @tparam T the type of the port
/// @tparam TT the target traits
/// @param[in] i_target a port target
/// @return FAPI2_RC_SUCCESs iff ok
///
template< fapi2::TargetType T, typename TT = dp16Traits<T> >
fapi2::ReturnCode reset_data_bit_enable( const fapi2::Target<T>& i_target );
///
/// @brief Reset the bad-bits masks for a port
/// @note Read the bad bits from the f/w attributes and stuff them in the
/// appropriate registers.
/// @param[in] i_target the fapi2 target of the port
/// @return FAPI2_RC_SUCCESS if and only if ok
///
fapi2::ReturnCode reset_bad_bits(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target);
///
/// @brief Reset the bad-bits masks for a port - helper for testing
/// @note The magic 10 is because there are 80 bits represented in this attribute, and each element is 8 bits.
/// So to get to 80, we need 10 bytes.
/// @param[in] i_target the fapi2 target of the port
/// @param[in] i_bad_dq array representing the data from the bad dq bitmap
/// @return FAPI2_RC_SUCCESS if and only if ok
///
fapi2::ReturnCode reset_bad_bits_helper(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
const uint8_t i_bad_dq[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM][10]);
///
/// @brief Configure the DP16 io_tx config0 registers
/// @tparam T the fapi2::TargetType
/// @tparam TT the target traits
/// @param[in] i_target a fapi2 target
/// @return FAPI2_RC_SUCCESs iff ok
///
template< fapi2::TargetType T, typename TT = dp16Traits<T> >
fapi2::ReturnCode reset_io_tx_config0( const fapi2::Target<T>& i_target );
///
/// @brief Configure ADR DLL/VREG Config 1
/// @tparam T the fapi2::TargetType
/// @tparam TT the target traits
/// @param[in] i_target a fapi2 target
/// @return FAPI2_RC_SUCCESs iff ok
///
template< fapi2::TargetType T, typename TT = dp16Traits<T> >
fapi2::ReturnCode reset_dll_vreg_config1( const fapi2::Target<T>& i_target );
///
/// @brief Configure Read VREF Registers
/// @tparam T the fapi2::TargetType
/// @tparam TT the target traits
/// @param[in] i_target a fapi2 target
/// @return FAPI2_RC_SUCCESs iff ok
///
template< fapi2::TargetType T, typename TT = dp16Traits<T> >
fapi2::ReturnCode reset_rd_vref( const fapi2::Target<T>& i_target );
///
/// Specializations
///
///
/// @brief Configure the DP16 sysclk
/// @param[in] i_target a MCBIST target
/// @return FAPI2_RC_SUCCESs iff ok
///
fapi2::ReturnCode reset_sysclk( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target );
///
/// @brief Reset the training delay configureation
/// @param[in] i_target the port target
/// @param[in] l_rank_pairs vector of rank pairs
/// @return FAPI2_RC_SUCCES iff ok
///
fapi2::ReturnCode reset_delay_values( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
const std::vector< uint64_t >& l_rank_pairs );
///
/// @brief Reset the read clock enable registers
/// @param[in] i_target a port target
/// @param[in] l_rank_pairs vector of rank pairs
/// @return FAPI2_RC_SUCCES iff ok
///
fapi2::ReturnCode reset_read_clock_enable( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
const std::vector< uint64_t >& l_rank_pairs );
///
/// @brief Reset the write clock enable registers
/// @param[in] i_target a port target
/// @param[in] l_rank_pairs vector of rank pairs
/// @return FAPI2_RC_SUCCES iff ok
///
fapi2::ReturnCode reset_write_clock_enable( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
const std::vector< uint64_t >& l_rank_pairs );
///
/// @brief Reset the data bit enable registers
/// @param[in] i_target a port target
/// @return FAPI2_RC_SUCCESs iff ok
///
fapi2::ReturnCode reset_data_bit_enable( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target );
///
/// @brief Configure the DP16 io_tx config0 registers
/// @param[in] i_target a MCBIST target
/// @return FAPI2_RC_SUCCESs iff ok
///
fapi2::ReturnCode reset_io_tx_config0( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target );
///
/// @brief Configure ADR DLL/VREG Config 1
/// @param[in] i_target a MCBIST target
/// @return FAPI2_RC_SUCCESs iff ok
///
fapi2::ReturnCode reset_dll_vreg_config1( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target );
///
/// @brief Configure Read VREF Registers
/// @param[in] i_target a MCA target
/// @return FAPI2_RC_SUCCESs iff ok
///
fapi2::ReturnCode reset_rd_vref( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target );
///
/// @brief sets up the DQ/DQS driver impedances
/// @tparam T the type of the target in question
/// @param[in] i_target the port in question
/// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS iff no error
///
template< fapi2::TargetType T >
fapi2::ReturnCode reset_dq_dqs_drv_imp( const fapi2::Target<T>& i_target );
///
/// @brief sets the register value for DQ/DQS driver impedance from the VPD value
/// @tparam T the type of the target in question
/// @param[in] i_target the port in question
/// @param[out] o_reg_value values to push into the registers
/// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS iff no error
///
template< fapi2::TargetType T >
fapi2::ReturnCode get_dq_dqs_drv_imp_field_value( const fapi2::Target<T>& i_target,
fapi2::buffer<uint8_t>* o_reg_value );
///
/// @brief Read dq_dqs_drv_imp
/// @tparam I DP16 instance
/// @tparam T fapi2 Target Type - derived
/// @tparam TT traits type defaults to dp16Traits<T>
/// @param[in] i_target the fapi2 target of the port
/// @param[out] o_data the value of both of the registers (upper and lower bytes)
/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
///
template< uint64_t I, fapi2::TargetType T, typename TT = dp16Traits<T> >
inline fapi2::ReturnCode read_dq_dqs_drv_imp( const fapi2::Target<T>& i_target,
fapi2::buffer<uint64_t>& o_data )