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L3 update -- p9_smp_link_layer
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whitespace, line length updates

Change-Id: Iaa312ba533e99c4a018ca768c0c71edcfe7648ea
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41698
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41701
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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@jjmcgill @dcrowell77
jjmcgill authored and dcrowell77 committed Jun 19, 2017
1 parent 12a64eb commit 0483af6
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Showing 2 changed files with 39 additions and 34 deletions.
53 changes: 30 additions & 23 deletions src/import/chips/p9/procedures/hwp/nest/p9_smp_link_layer.C
View file
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2016 */
/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -33,7 +33,7 @@
// *HWP HWP Owner: Joe McGill <jmcgill@us.ibm.com>
// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
// *HWP Team: Nest
// *HWP Level: 2
// *HWP Level: 3
// *HWP Consumed by: HB,FSP
//

Expand All @@ -43,47 +43,48 @@
#include <p9_smp_link_layer.H>
#include <p9_fbc_smp_utils.H>


//------------------------------------------------------------------------------
// Function definitions
//------------------------------------------------------------------------------


///
/// @brief Engage DLL/TL training for a single fabric link (X/A)
///
/// @param[in] i_target Reference to processor chip target
/// @param[in] i_ctl Reference to link control structure
/// @param[in] i_target Reference to processor chip target
/// @param[in] i_ctl Reference to link control structure
///
/// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
///
fapi2::ReturnCode
p9_smp_link_layer_train_link(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
const p9_fbc_link_ctl_t& i_ctl)

p9_smp_link_layer_train_link(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
const p9_fbc_link_ctl_t& i_ctl)
{
FAPI_DBG("Start");
fapi2::buffer<uint64_t> l_dll_control;

// optical (IOOOL)/electrical (IOEL) control registers share common bit
// layout, R-M-W control register to set link startup bits
fapi2::buffer<uint64_t> l_dll_control;
FAPI_TRY(fapi2::getScom(i_target, i_ctl.dl_control_addr, l_dll_control),
"Error reading DLL control register!");
// optical (IOOOL)/electrical (IOEL) control registers share common bit layout
"Error reading DLL control register (0x%08X)!",
i_ctl.dl_control_addr);
l_dll_control.setBit<XBUS_LL0_IOEL_CONTROL_LINK0_STARTUP>();
l_dll_control.setBit<XBUS_LL0_IOEL_CONTROL_LINK1_STARTUP>();
FAPI_TRY(fapi2::putScom(i_target, i_ctl.dl_control_addr, l_dll_control),
"Error writing DLL control register!");
"Error writing DLL control register (0x%08X)!",
i_ctl.dl_control_addr);

fapi_try_exit:
FAPI_DBG("End");
return fapi2::current_err;
}


// NOTE: see doxygen comments in header
fapi2::ReturnCode
p9_smp_link_layer(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
const bool i_train_electrical,
const bool i_train_optical)
p9_smp_link_layer(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
const bool i_train_electrical,
const bool i_train_optical)
{
FAPI_INF("Start");

Expand All @@ -93,10 +94,14 @@ p9_smp_link_layer(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
uint8_t l_a_en[P9_FBC_UTILS_MAX_A_LINKS];

// process set of enabled links
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG, i_target, l_x_en),
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG,
i_target,
l_x_en),
"Error from FAPI_ATTR_GET (ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG");

FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG, i_target, l_a_en),
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG,
i_target,
l_a_en),
"Error from FAPI_ATTR_GET (ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG");

for (uint8_t l_link = 0; l_link < P9_FBC_UTILS_MAX_X_LINKS; l_link++)
Expand All @@ -109,8 +114,9 @@ p9_smp_link_layer(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
(P9_FBC_XBUS_LINK_CTL_ARR[l_link].endp_type == OPTICAL)))
{
FAPI_DBG("Training link X%d", l_link);
FAPI_TRY(p9_smp_link_layer_train_link(i_target,
P9_FBC_XBUS_LINK_CTL_ARR[l_link]),
FAPI_TRY(p9_smp_link_layer_train_link(
i_target,
P9_FBC_XBUS_LINK_CTL_ARR[l_link]),
"Error from p9_smp_link_layer_train_link (X)");
}
}
Expand All @@ -128,8 +134,9 @@ p9_smp_link_layer(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
(P9_FBC_ABUS_LINK_CTL_ARR[l_link].endp_type == OPTICAL))
{
FAPI_DBG("Training link A%d", l_link);
FAPI_TRY(p9_smp_link_layer_train_link(i_target,
P9_FBC_ABUS_LINK_CTL_ARR[l_link]),
FAPI_TRY(p9_smp_link_layer_train_link(
i_target,
P9_FBC_ABUS_LINK_CTL_ARR[l_link]),
"Error from p9_smp_link_layer_train_link (A)");
}
}
Expand Down
20 changes: 9 additions & 11 deletions src/import/chips/p9/procedures/hwp/nest/p9_smp_link_layer.H
View file
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2016 */
/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -42,20 +42,18 @@
// *HWP HWP Owner: Joe McGill <jmcgill@us.ibm.com>
// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
// *HWP Team: Nest
// *HWP Level: 2
// *HWP Level: 3
// *HWP Consumed by: HB,FSP
//

#ifndef _P9_SMP_LINK_LAYER_H_
#define _P9_SMP_LINK_LAYER_H_


//------------------------------------------------------------------------------
// Includes
//------------------------------------------------------------------------------
#include <fapi2.H>


//------------------------------------------------------------------------------
// Structure definitions
//------------------------------------------------------------------------------
Expand All @@ -66,7 +64,6 @@ typedef fapi2::ReturnCode (*p9_smp_link_layer_FP_t) (
const bool,
const bool);


//------------------------------------------------------------------------------
// Function prototypes
//------------------------------------------------------------------------------
Expand All @@ -77,15 +74,16 @@ extern "C"
///
/// @brief Train fabric DLL/TL layers
///
/// @param[in] i_target Reference to processor chip target
/// @param[in] i_train_electrical Train electrical links?
/// @param[in] i_train_optical Train optical links?
/// @param[in] i_target Reference to processor chip target
/// @param[in] i_train_electrical Train electrical links?
/// @param[in] i_train_optical Train optical links?
///
/// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
///
fapi2::ReturnCode p9_smp_link_layer(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
const bool i_train_electrical,
const bool i_train_optical);
fapi2::ReturnCode p9_smp_link_layer(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
const bool i_train_electrical,
const bool i_train_optical);

} // extern "C"

Expand Down

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