Move disabling PSI CEC interrupts to the common path for INT reset

In DD1 we used a SW reset to reset the INT unit, in DD2 we will use
the HW resets. In both paths we need to disable the PSI CEC intrs.
This commit moves the code that disables PSI CEC interrupts to before
the code paths diverge in the resetIntUnit func in intrrp.C

Change-Id: I2ebdbf374e7a2561151a138c6304ef31da1af4aa
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42850
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

src/usr/intr/intrrp.C

@@ -415,6 +415,15 @@ void IntrRp::acknowledgeInterrupt()
     TRACFCOMP(g_trac_intr, "IntrRp::acknowledgeInterrupt(), read result: %16x", l_ackRead);
 }
 
+void IntrRp::disablePsiInterrupts(intr_hdlr_t* i_proc)
+{
+    //Disable Incoming PSI Interrupts
+    PSIHB_SW_INTERFACES_t * l_psihb_ptr = i_proc->psiHbBaseAddr;
+
+    //Clear bit to disable PSI CEC interrupts
+    l_psihb_ptr->psihbcr = (l_psihb_ptr->psihbcr & ~PSI_BRIDGE_INTP_STATUS_CTL_DISABLE_PSI);
+}
+
 errlHndl_t IntrRp::resetIntUnit(intr_hdlr_t* i_proc)
 {
     errlHndl_t l_err = NULL;
@@ -436,6 +445,9 @@ errlHndl_t IntrRp::resetIntUnit(intr_hdlr_t* i_proc)
 
         if (l_doHwReset)
         {
+            //Disable the PSI CEC interrupts
+            disablePsiInterrupts(i_proc);
+
             //Use HW-based XIVE Reset
             //First quiesce the power bus
             TRACDCOMP(g_trac_intr, "IntrRp::resetIntUnit() - "
@@ -563,12 +575,8 @@ errlHndl_t IntrRp::disableInterrupts(intr_hdlr_t *i_proc)
 
     do
     {
-        //Disable Incoming PSI Interrupts
-        PSIHB_SW_INTERFACES_t * l_psihb_ptr = i_proc->psiHbBaseAddr;
-
-        //Clear bit to disable PSI CEC interrupts
-        l_psihb_ptr->psihbcr =
-             (l_psihb_ptr->psihbcr & ~PSI_BRIDGE_INTP_STATUS_CTL_DISABLE_PSI);
+        //Disable PSI CEC interrupts
+        disablePsiInterrupts(i_proc);
 
         //The XIVE HW is expecting these MMIO accesses to come from the
         // core/thread they were setup (master core, thread 0)

src/usr/intr/intrrp.H

@@ -398,6 +398,12 @@ namespace INTR
              */
             void enableLsiInterrupts();
 
+            /**
+             * Clear bit 3 of the PSIHB Control/Status register to disable
+               PSI interrupts from interrupting the CEC.
+             */
+            void disablePsiInterrupts(intr_hdlr_t* i_proc);
+
             /**
              * Message handler
              */