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crgeddesdcrowell77
crgeddes
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dcrowell77
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Fix up interrupt init process for MPIPL
Pulled enableVPCPullErr out of resetIntUnit function Added disableVPCPullErr to MPIPL flow Add in enableLSIInterupts func to call after enableInterrutps Moved enableInterrupts function before maskAllInterrupts call Change-Id: I6fadabfc74a5766862ad59db5c43596aa91e3199 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36570 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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‎src/usr/intr/intrrp.C

Lines changed: 100 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -137,6 +137,13 @@ errlHndl_t IntrRp::resetIntpForMpipl()
137137
PSIHB_SW_INTERFACES_t * this_psihb_ptr = (*targ_itr)->psiHbBaseAddr;
138138
this_psihb_ptr->icr = PSI_BRIDGE_INTP_STATUS_CTL_RESET;
139139
resetIntUnit(*targ_itr);
140+
//Turn off VPC error when in LSI mode
141+
err = disableVPCPullErr(*targ_itr);
142+
if (err)
143+
{
144+
TRACFCOMP(g_trac_intr, "Error masking VPC Pull Lsi Err");
145+
break;
146+
}
140147
}
141148
}
142149

@@ -148,6 +155,14 @@ errlHndl_t IntrRp::resetIntpForMpipl()
148155
//Reset XIVE Interrupt unit
149156
resetIntUnit(iv_masterHdlr);
150157

158+
//Turn off VPC error when in LSI mode
159+
err = disableVPCPullErr(iv_masterHdlr);
160+
if (err)
161+
{
162+
TRACFCOMP(g_trac_intr, "Error masking VPC Pull Lsi Err");
163+
break;
164+
}
165+
151166
//Clear out the mask list because pq state buffer gets cleared after
152167
//resetting the XIVE Interrupt unit
153168
iv_maskList.clear();
@@ -232,6 +247,8 @@ errlHndl_t IntrRp::_init()
232247
}
233248
}
234249

250+
251+
235252
//Disable Incoming PSI Interrupts
236253
TRACDCOMP(g_trac_intr, "IntrRp::_init() Disabling PSI Interrupts");
237254
uint64_t l_disablePsiIntr = PSI_BRIDGE_INTP_STATUS_CTL_DISABLE_PSI;
@@ -248,23 +265,55 @@ errlHndl_t IntrRp::_init()
248265
break;
249266
}
250267

251-
TRACFCOMP(g_trac_intr, "IntrRp::_init() Masking Interrupts");
252-
//Mask off all interrupt sources - these will be enabled as SW entities
253-
// register for specific interrupts via the appropriate message queue
254-
l_err = maskAllInterruptSources();
255-
if (l_err)
268+
// Check if we need to run the MPIPL path
269+
if(is_mpipl)
256270
{
257-
TRACFCOMP(g_trac_intr, "IntrRp::_init() Error masking all interrupt sources.");
258-
break;
259-
}
271+
// In MPIPL we enable Interrupt before masking sources -- while the
272+
// system is in this state interupts can get stuck, need to let any
273+
// interrupts have time to present themselves before we mask things
274+
TRACFCOMP(g_trac_intr, "IntrRp::_init() Enabling PSIHB Interrupts");
275+
//Enable PSIHB Interrupts
276+
l_err = enableInterrupts(l_procIntrHdlr);
260277

261-
TRACFCOMP(g_trac_intr, "IntrRp::_init() Enabling PSIHB Interrupts");
262-
//Enable PSIHB Interrupts
263-
l_err = enableInterrupts(l_procIntrHdlr);
264-
if (l_err)
278+
if (l_err)
279+
{
280+
TRACFCOMP(g_trac_intr, "IntrRp::_init() Error enabling Interrupts");
281+
break;
282+
}
283+
284+
285+
TRACFCOMP(g_trac_intr, "IntrRp::_init() Masking Interrupts");
286+
//Mask off all interrupt sources - these will be enabled as SW entities
287+
// register for specific interrupts via the appropriate message queue
288+
l_err = maskAllInterruptSources();
289+
if (l_err)
290+
{
291+
TRACFCOMP(g_trac_intr, "IntrRp::_init() Error masking all interrupt sources.");
292+
break;
293+
}
294+
295+
enableLsiInterrupts();
296+
}
297+
else
265298
{
266-
TRACFCOMP(g_trac_intr, "IntrRp::_init() Error enabling Interrupts");
267-
break;
299+
TRACFCOMP(g_trac_intr, "IntrRp::_init() Masking Interrupts");
300+
//Mask off all interrupt sources - these will be enabled as SW entities
301+
// register for specific interrupts via the appropriate message queue
302+
l_err = maskAllInterruptSources();
303+
if (l_err)
304+
{
305+
TRACFCOMP(g_trac_intr, "IntrRp::_init() Error masking all interrupt sources.");
306+
break;
307+
}
308+
309+
TRACFCOMP(g_trac_intr, "IntrRp::_init() Enabling PSIHB Interrupts");
310+
//Enable PSIHB Interrupts
311+
l_err = enableInterrupts(l_procIntrHdlr);
312+
if (l_err)
313+
{
314+
TRACFCOMP(g_trac_intr, "IntrRp::_init() Error enabling Interrupts");
315+
break;
316+
}
268317
}
269318

270319
// Create the kernel msg queue for external interrupts
@@ -293,6 +342,27 @@ errlHndl_t IntrRp::_init()
293342
return l_err;
294343
}
295344

345+
void IntrRp::enableLsiInterrupts()
346+
{
347+
TRACDCOMP(g_trac_intr, "IntrRp:: enableLsiInterrupts() enter");
348+
//The XIVE HW is expecting these MMIO accesses to come from the
349+
// core/thread they were setup (master core, thread 0)
350+
// These functions will ensure this code executes there
351+
task_affinity_pin();
352+
task_affinity_migrate_to_master();
353+
uint64_t * l_lsiEoi = iv_masterHdlr->xiveIcBarAddr;
354+
l_lsiEoi += XIVE_IC_LSI_EOI_OFFSET;
355+
l_lsiEoi += (0xC00 / sizeof(uint64_t));
356+
357+
volatile uint64_t l_eoiRead = *l_lsiEoi;
358+
TRACFCOMP(g_trac_intr, "IntrRp:: enableLsiInterrupts() read 0x%lx from pointer %p", l_eoiRead, l_lsiEoi);
359+
//MMIO Complete, rest of code can run on any thread
360+
task_affinity_unpin();
361+
TRACDCOMP(g_trac_intr, "IntrRp:: enableLsiInterrupts() exit");
362+
}
363+
364+
365+
296366
void IntrRp::acknowledgeInterrupt()
297367
{
298368

@@ -446,14 +516,6 @@ errlHndl_t IntrRp::resetIntUnit(intr_hdlr_t* i_proc)
446516
}
447517
}
448518

449-
//Enable VPC Pull Err regardles of XIVE HW Reset settings
450-
l_err = enableVPCPullErr(procTarget);
451-
if (l_err)
452-
{
453-
TRACFCOMP(g_trac_intr, "IntrRp::resetIntUnit() Error re-enabling VPC Pull Err");
454-
break;
455-
}
456-
457519
} while (0);
458520

459521
if (l_err)
@@ -1773,6 +1835,13 @@ void IntrRp::shutDown(uint64_t i_status)
17731835
PSIHB_SW_INTERFACES_t * this_psihb_ptr = (*targ_itr)->psiHbBaseAddr;
17741836
this_psihb_ptr->icr = PSI_BRIDGE_INTP_STATUS_CTL_RESET;
17751837
resetIntUnit(*targ_itr);
1838+
//Enable VPC Pull Err regardles of XIVE HW Reset settings
1839+
l_err = enableVPCPullErr((*targ_itr)->proc);
1840+
if (l_err)
1841+
{
1842+
delete l_err;
1843+
TRACFCOMP(g_trac_intr, "IntrRp::shutDown() Error re-enabling VPC Pull Err");
1844+
}
17761845
//Disable common interrupt BARs
17771846
l_err = setCommonInterruptBARs(*targ_itr, false);
17781847

@@ -1792,6 +1861,14 @@ void IntrRp::shutDown(uint64_t i_status)
17921861
//Reset XIVE Interrupt unit
17931862
resetIntUnit(iv_masterHdlr);
17941863

1864+
//Enable VPC Pull Err regardles of XIVE HW Reset settings
1865+
l_err = enableVPCPullErr(iv_masterHdlr->proc);
1866+
if (l_err)
1867+
{
1868+
delete l_err;
1869+
TRACFCOMP(g_trac_intr, "IntrRp::shutDown() Error re-enabling VPC Pull Err");
1870+
}
1871+
17951872
//Disable common interrupt BARs for master proc
17961873
l_err = setCommonInterruptBARs(iv_masterHdlr, false);
17971874
if (l_err)
@@ -3154,7 +3231,7 @@ errlHndl_t IntrRp::setPsiHbEsbBAR(intr_hdlr_t *i_proc,
31543231

31553232
uint64_t l_barValue = l_baseBarValue;
31563233
TRACFCOMP(g_trac_intr,"INTR: Target %p. "
3157-
"PSI BRIDGE ESB BAR value: 0x%016lx",
3234+
"PSI BRIDGE ESB BASE BAR value: 0x%016lx",
31583235
l_target,l_barValue);
31593236

31603237
uint64_t size = sizeof(l_barValue);

‎src/usr/intr/intrrp.H

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
/* */
66
/* OpenPOWER HostBoot Project */
77
/* */
8-
/* Contributors Listed Below - COPYRIGHT 2011,2016 */
8+
/* Contributors Listed Below - COPYRIGHT 2011,2017 */
99
/* [+] International Business Machines Corp. */
1010
/* */
1111
/* */
@@ -415,6 +415,12 @@ namespace INTR
415415

416416
errlHndl_t _init();
417417

418+
/**
419+
* Do a read from LSI ESB EOI page to enable presentation of LSI
420+
* interrupt to Hostboot
421+
*/
422+
void enableLsiInterrupts();
423+
418424
/**
419425
* Message handler
420426
*/

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