Updates code to run PHY DCD calibration

This update adds in workarounds to run the PHY's
duty cycle distortion calibration algorithm in DD1.*.

Change-Id: I5e9abcf7450491995f5114c362e3ac99d517417e
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36302
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36329
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

Author: sglancy6

src/build/citest/etc/workarounds.postsimsetup

@@ -32,4 +32,25 @@
 #echo "+++ Updating something wonderful in a simics file"
 #mkdir -p $sb/simu/data/cec-chip/
 #cp $BACKING_BUILD/src/simu/data/cec-chip/base_cec_chip_file $sb/simu/data/cec-chip
-#patch -p0 $sb/simu/data/cec-chip/base_cec_chip_file $PROJECT_ROOT/src/build/citest/etc/patches/my_patch_File
+#patch -p0 $sb/simu/data/cec-chip/base_cec_chip_file $PROJECT_ROOT/src/build/citest/etc/patches/my_patch_File
+#Need a newer HW image due to some co-reqs, pull in hw022817a.910
+sbex -t 1018118
+cd $sb/engd/href/
+mk -a -k
+
+### RTC 170736 - Patch begins
+echo "+++ Updating p9n.act file for p9_fab_iovalid_link_validate"
+echo "+++ SB: " $sb
+echo "+++ BACKING_BUILD: " $BACKING_BUILD
+echo "+++ PROJECT_ROOT: " $PROJECT_ROOT
+
+mkdir -p  $sb/simu/data/cec-chip/
+cp $BACKING_BUILD/src/simu/data/cec-chip/p9n.act $sb/simu/data/cec-chip/
+patch -p0 $sb/simu/data/cec-chip/p9n.act $PROJECT_ROOT/src/build/citest/etc/patches/p9n.act_fab_io_patch
+### RTC 170736 - Patch ends
+
+#pull in new actions in p9_memory.act RTC 171066
+echo "+++ Updating p9n_memory.act file for p9_mss_ddr_phy_reset"
+sbex -t 1019444
+
+

src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.C

@@ -35,6 +35,7 @@
 
 #include <fapi2.H>
 #include <lib/phy/adr32s.H>
+#include <lib/workarounds/adr32s_workarounds.H>
 #include <lib/utils/find.H>
 
 using fapi2::TARGET_TYPE_MCA;
@@ -63,16 +64,6 @@ const std::vector<uint64_t> adr32sTraits<fapi2::TARGET_TYPE_MCA>::DUTY_CYCLE_DIS
 {
     MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0,
     MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1,
-    MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0,
-    MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0,
-    MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1,
-    MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1,
-    MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2,
-    MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2,
-    MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3,
-    MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3,
-    MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4,
-    MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4,
 };
 
 // Definition of the ADR32S write clock static offset registers
@@ -85,122 +76,6 @@ const std::vector<uint64_t> adr32sTraits<fapi2::TARGET_TYPE_MCA>::PR_STATIC_OFFS
 namespace adr32s
 {
 
-///
-/// @brief Helper to iterate over ADR32S 'sides' when performing DCD cal
-/// @param[in] i_target the MCA to iterate for
-/// @param[in] i_reg the register (ADR0 or ADR1's register)
-/// @param[in] i_seed the seed value for the adjuster
-/// @param[in] i_side bool; true if this is side a, false for side b
-/// @param[out] o_value the value of the adjuster when the compare bit changes state
-/// @return FAPI2_RC_SUCCESS iff ok
-///
-fapi2::ReturnCode dcd_cal_helper( const fapi2::Target<TARGET_TYPE_MCA>& i_target,
-                                  const uint64_t i_reg,
-                                  const uint64_t i_seed,
-                                  const bool i_side,
-                                  uint64_t& o_value )
-{
-    typedef adr32sTraits<TARGET_TYPE_MCA> TT;
-
-    constexpr uint64_t l_dcd_adjust_overflow =  0b1111111;
-    constexpr uint64_t l_dcd_adjust_underflow = 0b0000000;
-
-    // If compare out is 0, we tick up ...
-    // Signed value which helps us increment or decrement the adjustment
-    int64_t l_tick = 1;
-    // ... and we expect a transition to 1
-    bool l_expected = 1;
-    // ... and we don't expect to overflow
-    uint64_t l_overrun = l_dcd_adjust_overflow;
-
-    fapi2::buffer<uint64_t> l_read;
-    uint64_t l_current_adjust = i_seed;
-    size_t l_iter = 0;
-
-    // More or less mirror's Bialas's logic for DD2 so we can kind of try out the algorithm on DD1.
-
-    FAPI_INF("enter dcd_cal_helper %s 0x%016lx seed: 0x%016lx side: %d",
-             mss::c_str(i_target), i_reg, i_seed, i_side );
-
-    // Prime the system with the starting values. We don't need to read/modify/write here as we're resetting
-    // the world and saving a scom here is likely benificial. Clear the compare out bit as writing it set
-    // will cause the PHY to throw a parity error
-    l_read.insertFromRight<TT::DCD_CONTROL_DLL_ADJUST, TT::DCD_CONTROL_DLL_ADJUST_LEN>(l_current_adjust);
-    l_read.writeBit<TT::DCD_CONTROL_DLL_ITER_A>(i_side);
-    l_read.clearBit<TT::DCD_CONTROL_DLL_COMPARE_OUT>();
-    FAPI_TRY( mss::putScom(i_target, i_reg, l_read) );
-
-    // Algorithm waits 128ck (~100ns) between steps. However, scom takes so long (and rippling up thru
-    // the platforms takes time too) that there's no need to actually delay - plenty of time has elapsed.
-
-    // Read. Note the register is volatile in that l_read which we just wrote isn't what we'll read
-    // as the distortion logic will take the seeded adjustment value and give us information on the next
-    // read (so don't get cute and remove this getScom.)
-    FAPI_TRY( mss::getScom(i_target, i_reg, l_read) );
-
-    // Based on the 'direction' we're going, we have some values to setup. We setup the bit == 0 case
-    // when we initialized these variables above.
-    if (l_read.getBit<TT::DCD_CONTROL_DLL_COMPARE_OUT>() != 0)
-    {
-        // If compare out is 1, we tick down ...
-        l_tick = -1;
-
-        // ... and we expect a transition to 0
-        l_expected = 0;
-
-        // ... and we don't expect to underflow
-        l_overrun = l_dcd_adjust_underflow;
-    }
-
-    do
-    {
-        l_iter += 1;
-        bool l_current_compare = l_read.getBit<TT::DCD_CONTROL_DLL_COMPARE_OUT>();
-
-        FAPI_INF("dcd_cal_helper: iter %d tick: %d expected: %d overrun: 0x%x out: %d adj: 0x%x",
-                 l_iter, l_tick, l_expected, l_overrun, l_current_compare, l_current_adjust);
-
-        if (l_current_compare == l_expected)
-        {
-            break;
-        }
-
-        // If we're here we're not done, so just adjust and try again. Clear the compare out bit, it must
-        // always be 0 or the PHY will parity error
-        l_read.insertFromRight<TT::DCD_CONTROL_DLL_ADJUST, TT::DCD_CONTROL_DLL_ADJUST_LEN>(l_current_adjust + l_tick);
-        l_read.clearBit<TT::DCD_CONTROL_DLL_COMPARE_OUT>();
-        FAPI_TRY( mss::putScom(i_target, i_reg, l_read) );
-
-        // Wait 128ck (~100ns) ...
-
-        FAPI_TRY( mss::getScom(i_target, i_reg, l_read) );
-
-        l_read.extractToRight<TT::DCD_CONTROL_DLL_ADJUST, TT::DCD_CONTROL_DLL_ADJUST_LEN>(l_current_adjust);
-
-    }
-    while (l_current_adjust != l_overrun);
-
-    FAPI_ASSERT( l_current_adjust != l_overrun,
-                 fapi2::MSS_DUTY_CLOCK_DISTORTION_CAL_FAILED()
-                 .set_TARGET(i_target)
-                 .set_CURRENT_ADJUST(l_current_adjust)
-                 .set_SIDE(i_side)
-                 .set_REGISTER(i_reg)
-                 .set_REGISTER_VALUE(l_read),
-                 "Failed ADR DCD for %s 0x%016lx", mss::c_str(i_target), i_reg );
-
-    // If we're here, we were done and there were no errors. So we can return back the current adjust value
-    // as the output/result of our operation
-    o_value = l_current_adjust;
-    FAPI_INF("side: %d final adjust value: 0x%x (0x%x)", i_side, o_value, l_current_adjust);
-
-    return FAPI2_RC_SUCCESS;
-
-fapi_try_exit:
-    return fapi2::current_err;
-}
-
-
 ///
 /// @brief Perform ADR DCD calibration - Nimbus Only
 /// @param[in] i_target the MCBIST (controler) to perform calibration on
@@ -240,34 +115,9 @@ fapi2::ReturnCode duty_cycle_distortion_calibration( const fapi2::Target<fapi2::
         fapi2::Assert(false);
     }
 
-    // We must calibrate each of our ports. Each has 2 ADR units and each unit needs it's A-side and B-side calibrated.
-    for (const auto& p : mss::find_targets<TARGET_TYPE_MCA>(i_target))
-    {
-        uint64_t l_seed = TT::DCD_ADJUST_DEFAULT;
-
-        for (const auto& r : TT::DUTY_CYCLE_DISTORTION_REG)
-        {
-            uint64_t l_a_side_value = 0;
-            uint64_t l_b_side_value = 0;
-
-            FAPI_TRY( dcd_cal_helper(p, r, l_seed, true, l_a_side_value) );
-
-            // We want to seed the other side (and each subsequent port) with the
-            // value found in the pervious iteration as that will likely reduce the number
-            // of iterations to find the transition. We back up one so that if we're on
-            // a transition, we don't 'bounce' from a 1 to a 0. This will give us a good
-            // transition if the a-side value is really to be the b-side value too.
-            FAPI_TRY( dcd_cal_helper(p, r, l_a_side_value - 1, false, l_b_side_value) );
-
-            // The final value is the average of the a-side and b-side values.
-            l_seed = (l_a_side_value + l_b_side_value) / 2;
-
-            FAPI_INF("average for both sides 0x%02x", l_seed);
-
-            // Note this writes all the other values to 0's which is OK for DD1
-            FAPI_TRY( mss::putScom(p, r, l_seed) );
-        }
-    }
+    // Runs the DD1 algorithm for now. The below TODO is to add in a switch to the DD2 algorithm
+    // TODO RTC:159687 For DD2 all we need to do is kick off the h/w cal and wait. We can check any ADR_DCD
+    FAPI_TRY(mss::workarounds::adr32s::duty_cycle_distortion_calibration(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;

src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.H

@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* Contributors Listed Below - COPYRIGHT 2016,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -324,21 +324,6 @@ inline void set_init_io( fapi2::buffer<uint64_t>& o_data, const states i_state )
     o_data.writeBit<TT::INIT_IO>(i_state);
 }
 
-///
-/// @brief Helper to iterate over ADR32S 'sides' when performing DCD cal
-/// @param[in] i_target the MCA to iterate for
-/// @param[in] i_reg the register (ADR0 or ADR1's register)
-/// @param[in] i_seed the seed value for the adjuster
-/// @param[in] i_side bool; true if this is side a, false for side b
-/// @param[out] o_value the value of the adjuster when the compare bit changes state
-/// @return FAPI2_RC_SUCCESS iff ok
-///
-fapi2::ReturnCode dcd_cal_helper( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
-                                  const uint64_t i_reg,
-                                  const uint64_t i_seed,
-                                  const bool i_side,
-                                  uint64_t& o_value );
-
 ///
 /// @brief Perform ADR DCD calibration - Nimbus Only
 /// @param[in] i_target the MCBIST (controler) to perform calibration on