Fixed CSID value for DD2

DD2 HW removed bits in the CSID register.
Values for CSID are now determined by nimbus chip revision.

Change-Id: I41da29248e34d0c48fb0293915a21add9b6918bd
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40508
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40511
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.C

@@ -400,8 +400,12 @@ fapi2::ReturnCode set_rank_pairs(const fapi2::Target<TARGET_TYPE_MCA>& i_target)
     // Set the CSID to all 'unused' and we'll reset them as we configure rank pairs.
     // Note: Centaur configured this as 0xff00 all the time - it's unclear if we need
     // to set only the bits for the rank pairs configured, or whether 0xff00 will suffice. BRS
-    fapi2::buffer<uint64_t> l_csid_data(0xFF00);
+    // Updating for DD2 0xF000, as bits 4-7 (in terms of the phy reg) are removed
+    constexpr uint64_t DD1_CSID = 0xff00;
+    constexpr uint64_t DD2_CSID = 0xf000;
+    const fapi2::buffer<uint64_t> l_csid_data = mss::chip_ec_nimbus_lt_2_0(i_target) ? DD1_CSID : DD2_CSID;
 
+    // Gets the rankpairs
     std::pair<uint64_t, uint64_t> l_rp_registers;
     FAPI_TRY( get_rank_pair_assignments(i_target, l_rp_registers) );