additional dd2 nimbus inits

Change-Id: I00487a727859a8c3311dcdad1da80d02c94a62a7 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40416 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40420 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
open-power · May 23, 2017 · 4908826 · 4908826
1 parent e60e1d2
commit 4908826
Show file tree

Hide file tree

Showing 2 changed files with 55 additions and 0 deletions.
diff --git a/src/import/chips/p9/initfiles/p9.mca.scom.initfile b/src/import/chips/p9/initfiles/p9.mca.scom.initfile
@@ -1084,6 +1084,31 @@ espy MC01.PORT0.ATCL.CL.CLSCOM.MCPERF2_ENABLE_REFRESH_BLOCK_DISP [when=S && ATTR
   OFF;
 }
 
+espy MC01.PORT0.ATCL.CL.CLSCOM.MCBUSYQ_ENABLE_BUSY_COUNTERS [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv;
+  ON;
+}
+
+espy MC01.PORT0.ATCL.CL.CLSCOM.MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv;
+  1024_CYCLES;
+}
+
+ispy MC01.PORT0.ATCL.CL.CLSCOM.MCBUSYQ_BUSY_COUNTER_THRESHOLD0 [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv;
+  38;
+}
+
+ispy MC01.PORT0.ATCL.CL.CLSCOM.MCBUSYQ_BUSY_COUNTER_THRESHOLD1 [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv;
+  51;
+}
+
+ispy MC01.PORT0.ATCL.CL.CLSCOM.MCBUSYQ_BUSY_COUNTER_THRESHOLD2 [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv;
+  64;
+}
+
 #################
 # DD2 WORKAROUNDS
 #################
@@ -1103,3 +1128,8 @@ espy MC01.PORT0.ATCL.CL.CLSCOM.MCPERF3_ENABLE_CL0 [when=S && ATTR_CHIP_EC_FEATUR
   ON;
 }
 
+# When AMO cache is re-enabled for DD2, we need to run with write open page disabled (same CQ observation)
+espy MCP.PORT0.SRQ.MBA_WRQ0Q_CFG_DISABLE_WR_PG_MODE [when=S && !ATTR_CHIP_EC_FEATURE_HW401780] {
+  spyv;
+  ON;
+}
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_mca_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_mca_scom.C
@@ -51,6 +51,9 @@ constexpr uint64_t literal_0b0000000000000000000000000 = 0b000000000000000000000
 constexpr uint64_t literal_0b1100111111111111111111111 = 0b1100111111111111111111111;
 constexpr uint64_t literal_0x1 = 0x1;
 constexpr uint64_t literal_6 = 6;
+constexpr uint64_t literal_38 = 38;
+constexpr uint64_t literal_51 = 51;
+constexpr uint64_t literal_64 = 64;
 constexpr uint64_t literal_0x8 = 0x8;
 constexpr uint64_t literal_17 = 17;
 constexpr uint64_t literal_1867 = 1867;
@@ -360,6 +363,21 @@ fapi2::ReturnCode p9_mca_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& TGT0,
             l_scom_buffer.insert<40, 8, 56, uint64_t>(l_def_MC_EPSILON_CFG_T2 );
             FAPI_TRY(fapi2::putScom(TGT0, 0x5010826ull, l_scom_buffer));
         }
+        {
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
+            {
+                FAPI_TRY(fapi2::getScom( TGT0, 0x5010827ull, l_scom_buffer ));
+
+                constexpr auto l_MC01_PORT0_ATCL_CL_CLSCOM_MCBUSYQ_ENABLE_BUSY_COUNTERS_ON = 0x1;
+                l_scom_buffer.insert<0, 1, 63, uint64_t>(l_MC01_PORT0_ATCL_CL_CLSCOM_MCBUSYQ_ENABLE_BUSY_COUNTERS_ON );
+                constexpr auto l_MC01_PORT0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT_1024_CYCLES = 0x1;
+                l_scom_buffer.insert<1, 3, 61, uint64_t>(l_MC01_PORT0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT_1024_CYCLES );
+                l_scom_buffer.insert<4, 10, 54, uint64_t>(literal_38 );
+                l_scom_buffer.insert<14, 10, 54, uint64_t>(literal_51 );
+                l_scom_buffer.insert<24, 10, 54, uint64_t>(literal_64 );
+                FAPI_TRY(fapi2::putScom(TGT0, 0x5010827ull, l_scom_buffer));
+            }
+        }
         {
             if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
             {
@@ -508,6 +526,13 @@ fapi2::ReturnCode p9_mca_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& TGT0,
 
             l_scom_buffer.insert<5, 1, 63, uint64_t>(l_TGT1_ATTR_MSS_REORDER_QUEUE_SETTING );
             l_scom_buffer.insert<55, 4, 60, uint64_t>(literal_0b1000 );
+
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
+            {
+                constexpr auto l_MCP_PORT0_SRQ_MBA_WRQ0Q_CFG_DISABLE_WR_PG_MODE_ON = 0x1;
+                l_scom_buffer.insert<6, 1, 63, uint64_t>(l_MCP_PORT0_SRQ_MBA_WRQ0Q_CFG_DISABLE_WR_PG_MODE_ON );
+            }
+
             FAPI_TRY(fapi2::putScom(TGT0, 0x701090dull, l_scom_buffer));
         }
         {