Fixed register values for RD VREF

Change-Id: I28167e1a2a627c3b955ef2cf91cdec32f5d0c22e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35911 Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: RYAN P. KING <rpking@us.ibm.com> Reviewed-by: Brian R. Silver <bsilver@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35917 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
open-power · Feb 12, 2017 · 506ba55 · 506ba55
1 parent 3db9e21
commit 506ba55
Show file tree

Hide file tree

Showing 3 changed files with 24 additions and 13 deletions.
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* Contributors Listed Below - COPYRIGHT 2016,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -470,9 +470,9 @@ inline fapi2::ReturnCode reset_vref_config1( const fapi2::Target<T>& i_target )
     FAPI_TRY( mss::eff_dram_al(i_target, l_al) );
     FAPI_TRY( mss::eff_dram_cl(i_target, l_cl) );
 
-    // PHY databook p 506
-    // The recommended setting is (AL + CL + 12).
-    l_data.insertFromRight<TT::CMD_PRECEDE_TIME, TT::CMD_PRECEDE_TIME_LEN>(l_al + l_cl + 12);
+    // Per Ryan King's characterization:
+    // The recommended setting is (AL + CL + 15).
+    l_data.insertFromRight<TT::CMD_PRECEDE_TIME, TT::CMD_PRECEDE_TIME_LEN>(l_al + l_cl + 15);
     l_data.insertFromRight<TT::MPR_PAGE, TT::MPR_PAGE_LEN>(0b0100); // From R. King
 
     // Note: when initial cal is setup, this register will change to accomodate the

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H
@@ -289,8 +289,6 @@ fapi_try_exit:
     return fapi2::current_err;
 }
 
-// TK read, write RD_WR_DATA
-
 ///
 /// @brief Setup odt_wr/rd_config
 /// @tparam T fapi2 Target Type - derived
@@ -302,13 +300,26 @@ template< fapi2::TargetType T, typename TT = seqTraits<T> >
 fapi2::ReturnCode reset_rd_wr_data( const fapi2::Target<T>& i_target )
 {
     // MPR_PATTERN_BIT of 0F0F0F0F pattern
-    static const uint64_t MPR_PATTERN = 0x5555;
+    // MPRLOC vs pattern
+    // MPR0   = 0F0F0F0F - these repeating patterns are for RD CTR, which needs transitions each data beat
+    // MPR1   = 00000000 - these 0 patterns are for RD VREF, which needs a static low level
+    // MPR2   = 00000000 - these 0 patterns are for RD VREF, which needs a static low level
+    // MPR3   = 0F0F0F0F - these repeating patterns are for RD CTR, which needs transitions each data beat
+    // MPR loc is noted above  the data below
+    //                                   0011
+    constexpr uint64_t MPR01_PATTERN = 0x5500;
+    // Per Ryan King: Only MPR page 0 locations 0/1 are required
+    //                2/3 are mirrored for safety but could be changed as needed
+    //                                   2233
+    constexpr uint64_t MPR23_PATTERN = 0x0055;
     fapi2::buffer<uint64_t> l_data;
 
-    l_data.insertFromRight<TT::MPR_PATTERN, TT::MPR_PATTERN_LEN>(MPR_PATTERN);
-
-    FAPI_INF("seq_rd_wr 0x%llx", l_data);
+    l_data.insertFromRight<TT::MPR_PATTERN, TT::MPR_PATTERN_LEN>(MPR01_PATTERN);
+    FAPI_INF("seq_rd_wr0 0x%llx", l_data);
     FAPI_TRY( mss::putScom(i_target, TT::SEQ_RDWR_DATA0, l_data) );
+
+    l_data.insertFromRight<TT::MPR_PATTERN, TT::MPR_PATTERN_LEN>(MPR23_PATTERN);
+    FAPI_INF("seq_rd_wr1 0x%llx", l_data);
     FAPI_TRY( mss::putScom(i_target, TT::SEQ_RDWR_DATA1, l_data) );
 
 fapi_try_exit:

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/write_cntrl.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/write_cntrl.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* Contributors Listed Below - COPYRIGHT 2016,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -338,8 +338,8 @@ inline fapi2::ReturnCode reset_config0( const fapi2::Target<T>& i_target )
         l_data.insertFromRight<TT::FW_WR_RD, TT::FW_WR_RD_LEN>(FW_WR_RD);
     }
 
-    // 63, 0b0, any;       # CUSTOM_INIT_WRITE
-    l_data.clearBit<TT::CUSTOM_INIT_WRITE>();
+    // 63, 0b1, any;       # CUSTOM_INIT_WRITE - set to a 1 to get proper values for RD VREF
+    l_data.setBit<TT::CUSTOM_INIT_WRITE>();
 
     FAPI_DBG("wc_config0 reset 0x%llx (tWLO_tWLOE: %d)", l_data, mss::twlo_twloe(i_target));
     FAPI_TRY( write_config0(i_target, l_data) );