p9_start_cbs updates

Adding delay to wait for PibReset
to complete

Change-Id: I79c9f591102c0114810348647c38d4b7fb762076
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37161
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Dev-Ready: Kahn C. Evans <kahnevan@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37237
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

src/import/chips/p9/procedures/hwp/perv/p9_start_cbs.C

@@ -52,7 +52,9 @@ enum P9_START_CBS_Private_Constants
     CBS_IDLE_VALUE = 0x002, // Read the value of CBS_CS_INTERNAL_STATE_VECTOR
     P9_CBS_IDLE_HW_NS_DELAY = 640000, // unit is nano seconds [min : 64k x (1/100MHz) = 64k x 10(-8) = 640 us
     //                       max : 64k x (1/50MHz) = 128k x 10(-8) = 1280 us]
-    P9_CBS_IDLE_SIM_CYCLE_DELAY = 7500000 // unit is sim cycles,to match the poll count change( 250000 * 30 )
+    P9_CBS_IDLE_SIM_CYCLE_DELAY = 7500000, // unit is sim cycles,to match the poll count change( 250000 * 30 )
+    P9_PIBRESET_HW_NS_DELAY = 4000,  // 256 pibclocks
+    P9_PIBRESET_SIM_CYCLE_DELAY = 256000
 };
 
 fapi2::ReturnCode p9_start_cbs(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>
@@ -65,8 +67,12 @@ fapi2::ReturnCode p9_start_cbs(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>
     fapi2::buffer<uint32_t> l_data32;
     fapi2::buffer<uint32_t> l_data32_cbs_cs;
     int l_timeout = 0;
+    fapi2::buffer<uint8_t> l_read_attr;
     FAPI_INF("p9_start_cbs: Entering ...");
 
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW402019_PIBRESET_DELAY,
+                           i_target_chip, l_read_attr));
+
     FAPI_DBG("Clearing  Selfboot message register before every boot ");
     // buffer is init value is 0
     FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_SB_MSG_FSI, l_data32));
@@ -146,11 +152,15 @@ fapi2::ReturnCode p9_start_cbs(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>
                 .set_HW_DELAY(P9_CBS_IDLE_HW_NS_DELAY),
                 "ERROR: CBS HAS NOT REACHED IDLE STATE VALUE 0x002 ");
 
-
-    FAPI_DBG("Setting up Pibreset");
-    l_data32.flush<1>();
-    FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_FSI2PIB_SET_PIB_RESET_FSI,
-                                    l_data32));
+    if ( l_read_attr )
+    {
+        FAPI_DBG("Setting up Pibreset");
+        l_data32.flush<1>();
+        FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_FSI2PIB_SET_PIB_RESET_FSI,
+                                        l_data32));
+        FAPI_DBG("waiting for pibreset to complete");
+        fapi2::delay(P9_PIBRESET_HW_NS_DELAY, P9_PIBRESET_SIM_CYCLE_DELAY);
+    }
 
     if ( i_sbe_start )
     {

src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml

@@ -2193,6 +2193,24 @@
       </chip>
     </chipEcFeature>
   </attribute>
+  <!-- ******************************************************************** -->
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_HW402019_PIBRESET_DELAY</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Nimbus DD1 only: Adding delay to wait for
+      pibreset to complete
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
 
   <!-- ******************************************************************** -->
   <!-- Memory Section                                                       -->