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L3 support for ddr_phy_reset, termination_control
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Change-Id: I70ad1f23dabc4b9f169821b30a903a200f52fbc4
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42437
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42452
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
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@JacobHarvey @sannerd
JacobHarvey authored and sannerd committed Jul 19, 2017
1 parent b47fc40 commit 543d555
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Showing 39 changed files with 469 additions and 402 deletions.
2 changes: 1 addition & 1 deletion src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/control_word_ddr4.H
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Expand Up @@ -28,7 +28,7 @@
/// @brief Run and manage the DDR4 control words for the RCD and data buffers
///
// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com>
// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com>
// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 1
// *HWP Consumed by: FSP:HB
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2 changes: 1 addition & 1 deletion src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H
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Expand Up @@ -28,7 +28,7 @@
/// @brief Code to support data_buffer_ddr4
///
// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com>
// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com>
// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 1
// *HWP Consumed by: HB:FSP
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2 changes: 1 addition & 1 deletion src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.C
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Expand Up @@ -28,7 +28,7 @@
/// @brief Latches WR VREF according to JEDEC spec
///
// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com>
// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 2
// *HWP Consumed by: FSP:HB Memory
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2 changes: 1 addition & 1 deletion src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.H
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Expand Up @@ -28,7 +28,7 @@
/// @brief Latches WR VREF according to JEDEC spec
///
// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com>
// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 2
// *HWP Consumed by: FSP:HB Memory
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6 changes: 3 additions & 3 deletions src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C
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Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2016 */
/* Contributors Listed Below - COPYRIGHT 2016,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand All @@ -27,10 +27,10 @@
/// @file mrs00.C
/// @brief Run and manage the DDR4 MRS00 loading
///
// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 1
// *HWP Level: 3
// *HWP Consumed by: FSP:HB

#include <fapi2.H>
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2 changes: 1 addition & 1 deletion src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C
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Expand Up @@ -27,7 +27,7 @@
/// @file mrs01.C
/// @brief Run and manage the DDR4 MRS01 loading
///
// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 1
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2 changes: 1 addition & 1 deletion src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C
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Expand Up @@ -27,7 +27,7 @@
/// @file mrs02.C
/// @brief Run and manage the DDR4 MRS02 loading
///
// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 1
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2 changes: 1 addition & 1 deletion src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C
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Expand Up @@ -27,7 +27,7 @@
/// @file mrs03.C
/// @brief Run and manage the DDR4 DDR4 loading
///
// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 1
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2 changes: 1 addition & 1 deletion src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C
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Expand Up @@ -27,7 +27,7 @@
/// @file mrs05.C
/// @brief Run and manage the DDR4 MRS05 loading
///
// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 1
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2 changes: 1 addition & 1 deletion src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs06.C
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Expand Up @@ -27,7 +27,7 @@
/// @file mrs06.C
/// @brief Run and manage the DDR4 MRS06 loading
///
// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 1
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2 changes: 1 addition & 1 deletion src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H
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Expand Up @@ -27,7 +27,7 @@
/// @file mrs_load_ddr4.H
/// @brief Code to support mrs_load_ddr4
///
// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 1
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2 changes: 1 addition & 1 deletion src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/state_machine.H
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Expand Up @@ -28,7 +28,7 @@
/// @brief state_machine delcaration
///
// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com>
// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com>
// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 2
// *HWP Consumed by: HB:FSP
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26 changes: 7 additions & 19 deletions src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.H
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Expand Up @@ -69,20 +69,6 @@ enum

};

///
/// @brief set of enums used for ffdc return codes
///
enum rank_functions
{
RANK_PAIR_TO_PHY = 0,
RANK_PAIR_FROM_PHY = 1,
SET_RANKS_IN_PAIR = 2,
GET_RANKS_IN_PAIR = 3,
GET_RANK_FIELD = 4,
GET_PAIR_VALID = 5,
SET_RANK_FIELD = 6,
RD_CTR_WORKAROUND_READ_DATA = 7,
};
///
/// @class rankPairTraits
/// @brief a collection of traits associated with rank pairs
Expand Down Expand Up @@ -1193,6 +1179,8 @@ template< uint64_t RP, fapi2::TargetType T, typename TT = rankPairTraits<T, RP>
fapi2::ReturnCode get_ranks_in_pair( const fapi2::Target<T>& i_target,
std::vector<uint64_t>& o_ranks )
{
static_assert(RP < MAX_RANK_PER_DIMM, "Passed in Rank Pair is too high");

o_ranks.clear();

// Read the rank pair register(s)
Expand Down Expand Up @@ -1338,12 +1326,12 @@ inline fapi2::ReturnCode get_ranks_in_pair( const fapi2::Target<T>& i_target,
FAPI_ASSERT( false,
fapi2::MSS_INVALID_RANK_PAIR()
.set_RANK_PAIR(i_rp)
.set_MCA_TARGET(i_target)
.set_FUNCTION(GET_RANKS_IN_PAIR),
"%s Invalid rank pair (%d) in get_ranks_in_pair",
.set_FUNCTION(GET_RANKS_IN_PAIR)
.set_MCA_TARGET(i_target),
"%s Invalid number of rankpairs entered. num: %lu max: %lu",
mss::c_str(i_target),
i_rp);

i_rp,
MAX_PRIMARY_RANKS_PER_PORT);
break;
}

Expand Down
4 changes: 2 additions & 2 deletions src/import/chips/p9/procedures/hwp/memory/lib/fir/check.C
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Expand Up @@ -27,10 +27,10 @@
/// @file check.C
/// @brief Subroutines for checking MSS FIR
///
// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com>
// *HWP HWP Backup: Marc Gollub <gollub@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 2
// *HWP Level: 3
// *HWP Consumed by: FSP:HB

#include <fapi2.H>
Expand Down
81 changes: 34 additions & 47 deletions src/import/chips/p9/procedures/hwp/memory/lib/phy/adr.C
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Expand Up @@ -27,10 +27,10 @@
/// @file adr.C
/// @brief Subroutines for the PHY ADR registers
///
// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 2
// *HWP Level: 3
// *HWP Consumed by: FSP:HB

#include <fapi2.H>
Expand Down Expand Up @@ -168,17 +168,14 @@ fapi2::ReturnCode reset_imp_clk( const fapi2::Target<TARGET_TYPE_MCA>& i_target
FAPI_TRY(mss::vpd_mt_mc_drv_imp_clk(i_target, l_attr_value));

//checks the attr value
if(l_attr_value != fapi2::ENUM_ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK_OHM30 &&
l_attr_value != fapi2::ENUM_ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK_OHM40 )
{
FAPI_ASSERT(false,
fapi2::MSS_INVALID_VPD_MT_MC_DRV_IMP_CLK()
.set_VALUE(l_attr_value)
.set_MCA_TARGET(i_target),
"%s value is not valid: %u",
c_str(i_target),
l_attr_value);
}
FAPI_ASSERT( l_attr_value == fapi2::ENUM_ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK_OHM30 ||
l_attr_value == fapi2::ENUM_ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK_OHM40,
fapi2::MSS_INVALID_VPD_MT_MC_DRV_IMP_CLK()
.set_VALUE(l_attr_value)
.set_MCS_TARGET( mss::find_target<fapi2::TARGET_TYPE_MCS>(i_target) ),
"%s value is not valid: %u",
c_str(i_target),
l_attr_value);

//loops and sets the value in each register
//Note: does RMW as other functions set the other lanes
Expand Down Expand Up @@ -228,17 +225,14 @@ fapi2::ReturnCode reset_imp_cmd_addr( const fapi2::Target<TARGET_TYPE_MCA>& i_ta
FAPI_TRY(mss::vpd_mt_mc_drv_imp_cmd_addr(i_target, l_attr_value));

//checks the attr value
if(l_attr_value != fapi2::ENUM_ATTR_MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR_OHM30 &&
l_attr_value != fapi2::ENUM_ATTR_MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR_OHM40 )
{
FAPI_ASSERT(false,
fapi2::MSS_INVALID_VPD_MT_MC_DRV_IMP_CMD_ADDR()
.set_VALUE(l_attr_value)
.set_MCA_TARGET(i_target),
"%s value is not valid: %u",
c_str(i_target),
l_attr_value);
}
FAPI_ASSERT( l_attr_value == fapi2::ENUM_ATTR_MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR_OHM30 ||
l_attr_value == fapi2::ENUM_ATTR_MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR_OHM40,
fapi2::MSS_INVALID_VPD_MT_MC_DRV_IMP_CMD_ADDR()
.set_VALUE(l_attr_value)
.set_MCS_TARGET( mss::find_target<fapi2::TARGET_TYPE_MCS>(i_target) ),
"%s value is not valid: %u",
c_str(i_target),
l_attr_value);

//loops and sets the value in each register
//Note: does RMW as other functions set the other lanes
Expand Down Expand Up @@ -288,17 +282,14 @@ fapi2::ReturnCode reset_imp_cntl( const fapi2::Target<TARGET_TYPE_MCA>& i_target
FAPI_TRY(mss::vpd_mt_mc_drv_imp_cntl(i_target, l_attr_value));

//checks the attr value
if(l_attr_value != fapi2::ENUM_ATTR_MSS_VPD_MT_MC_DRV_IMP_CNTL_OHM30 &&
l_attr_value != fapi2::ENUM_ATTR_MSS_VPD_MT_MC_DRV_IMP_CNTL_OHM40 )
{
FAPI_ASSERT(false,
fapi2::MSS_INVALID_VPD_MT_MC_DRV_IMP_CNTL()
.set_VALUE(l_attr_value)
.set_MCA_TARGET(i_target),
"%s value is not valid: %u",
c_str(i_target),
l_attr_value);
}
FAPI_ASSERT( l_attr_value == fapi2::ENUM_ATTR_MSS_VPD_MT_MC_DRV_IMP_CNTL_OHM30 ||
l_attr_value == fapi2::ENUM_ATTR_MSS_VPD_MT_MC_DRV_IMP_CNTL_OHM40,
fapi2::MSS_INVALID_VPD_MT_MC_DRV_IMP_CNTL()
.set_VALUE(l_attr_value)
.set_MCS_TARGET( mss::find_target<fapi2::TARGET_TYPE_MCS>(i_target) ),
"%s value is not valid: %u",
c_str(i_target),
l_attr_value);

//loops and sets the value in each register
//Note: does RMW as other functions set the other lanes
Expand All @@ -325,7 +316,6 @@ fapi2::ReturnCode reset_imp_cntl( const fapi2::Target<TARGET_TYPE_MCA>& i_target
FAPI_TRY(mss::putScom(i_target,
l_reg_info.first,
l_value));

}

fapi_try_exit:
Expand All @@ -348,17 +338,14 @@ fapi2::ReturnCode reset_imp_cscid( const fapi2::Target<TARGET_TYPE_MCA>& i_targe
FAPI_TRY(mss::vpd_mt_mc_drv_imp_cscid(i_target, l_attr_value));

//checks the attr value
if(l_attr_value != fapi2::ENUM_ATTR_MSS_VPD_MT_MC_DRV_IMP_CSCID_OHM30 &&
l_attr_value != fapi2::ENUM_ATTR_MSS_VPD_MT_MC_DRV_IMP_CSCID_OHM40 )
{
FAPI_ASSERT(false,
fapi2::MSS_INVALID_VPD_MT_MC_DRV_IMP_CSCID()
.set_VALUE(l_attr_value)
.set_MCA_TARGET(i_target),
"%s value is not valid: %u",
c_str(i_target),
l_attr_value);
}
FAPI_ASSERT( l_attr_value == fapi2::ENUM_ATTR_MSS_VPD_MT_MC_DRV_IMP_CSCID_OHM30 ||
l_attr_value == fapi2::ENUM_ATTR_MSS_VPD_MT_MC_DRV_IMP_CSCID_OHM40,
fapi2::MSS_INVALID_VPD_MT_MC_DRV_IMP_CSCID()
.set_VALUE(l_attr_value)
.set_MCS_TARGET( mss::find_target<fapi2::TARGET_TYPE_MCS>(i_target) ),
"%s value is not valid: %u",
c_str(i_target),
l_attr_value);

//loops and sets the value in each register
//Note: does RMW as other functions set the other lanes
Expand Down
20 changes: 10 additions & 10 deletions src/import/chips/p9/procedures/hwp/memory/lib/phy/adr.H
View file
Expand Up @@ -27,10 +27,10 @@
/// @file adr.H
/// @brief Subroutines for the PHY ADR registers
///
// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 2
// *HWP Level: 3
// *HWP Consumed by: FSP:HB

#ifndef _MSS_ADR_H_
Expand Down Expand Up @@ -223,7 +223,7 @@ inline fapi2::ReturnCode read_imp_clk( const fapi2::Target<T>& i_target,

//one register per CLK
FAPI_TRY( mss::getScom(i_target, TT::IO_TX_FET_SLICE_CLK_REG[I].first, o_data) );
FAPI_INF("imp_clk lane<%d>: 0x%016lx", I, o_data);
FAPI_INF("%s imp_clk lane<%d>: 0x%016lx", mss::c_str(i_target), I, o_data);

fapi_try_exit:
return fapi2::current_err;
Expand All @@ -245,7 +245,7 @@ inline fapi2::ReturnCode write_imp_clk( const fapi2::Target<T>& i_target,
static_assert( I < TT::NUM_CLK_LANES, "lane instance out of range");

//one register per CLK
FAPI_INF("imp_clk lane<%d>: 0x%016lx", I, i_data);
FAPI_INF("%s imp_clk lane<%d>: 0x%016lx", mss::c_str(i_target), I, i_data);
FAPI_TRY( mss::putScom(i_target, TT::IO_TX_FET_SLICE_CLK_REG[I].first, i_data) );

fapi_try_exit:
Expand Down Expand Up @@ -278,7 +278,7 @@ inline fapi2::ReturnCode read_imp_cmd_addr( const fapi2::Target<T>& i_target,

//one register per CMD/ADDR lane
FAPI_TRY( mss::getScom(i_target, TT::IO_TX_FET_SLICE_CMD_ADDR_REG[I].first, o_data) );
FAPI_INF("imp_cmd_addr lane<%d>: 0x%016lx", I, o_data);
FAPI_INF("%s imp_cmd_addr lane<%d>: 0x%016lx", mss::c_str(i_target), I, o_data);

fapi_try_exit:
return fapi2::current_err;
Expand All @@ -300,7 +300,7 @@ inline fapi2::ReturnCode write_imp_cmd_addr( const fapi2::Target<T>& i_target,
static_assert( I < TT::NUM_CMD_ADDR_LANES, "lane instance out of range");

//one register per CMD/ADDR lane
FAPI_INF("imp_cmd_addr lane<%d>: 0x%016lx", I, i_data);
FAPI_INF("%s imp_cmd_addr lane<%d>: 0x%016lx", mss::c_str(i_target), I, i_data);
FAPI_TRY( mss::putScom(i_target, TT::IO_TX_FET_SLICE_CMD_ADDR_REG[I].first, i_data) );

fapi_try_exit:
Expand Down Expand Up @@ -333,7 +333,7 @@ inline fapi2::ReturnCode read_imp_cntl( const fapi2::Target<T>& i_target,

//one register per CNTL
FAPI_TRY( mss::getScom(i_target, TT::IO_TX_FET_SLICE_CNTL_REG[I].first, o_data) );
FAPI_INF("imp_cntl lane<%d>: 0x%016lx", I, o_data);
FAPI_INF("%s imp_cntl lane<%d>: 0x%016lx", mss::c_str(i_target), I, o_data);

fapi_try_exit:
return fapi2::current_err;
Expand All @@ -355,7 +355,7 @@ inline fapi2::ReturnCode write_imp_cntl( const fapi2::Target<T>& i_target,
static_assert( I < TT::NUM_CNTL_LANES, "lane instance out of range");

//one register per CNTL
FAPI_INF("imp_cntl lane<%d>: 0x%016lx", I, i_data);
FAPI_INF("%s imp_cntl lane<%d>: 0x%016lx", mss::c_str(i_target), I, i_data);
FAPI_TRY( mss::putScom(i_target, TT::IO_TX_FET_SLICE_CNTL_REG[I].first, i_data) );

fapi_try_exit:
Expand Down Expand Up @@ -388,7 +388,7 @@ inline fapi2::ReturnCode read_imp_cscid( const fapi2::Target<T>& i_target,

//one register per CS/CID
FAPI_TRY( mss::getScom(i_target, TT::IO_TX_FET_SLICE_CSCID_REG[I].first, o_data) );
FAPI_INF("imp_cscid lane<%d>: 0x%016lx", I, o_data);
FAPI_INF("%s imp_cscid lane<%d>: 0x%016lx", mss::c_str(i_target), I, o_data);

fapi_try_exit:
return fapi2::current_err;
Expand All @@ -410,7 +410,7 @@ inline fapi2::ReturnCode write_imp_cscid( const fapi2::Target<T>& i_target,
static_assert( I < TT::NUM_CSCID_LANES, "lane instance out of range");

//one register per CS/CID
FAPI_INF("imp_cscid lane<%d>: 0x%016lx", I, i_data);
FAPI_INF("%s imp_cscid lane<%d>: 0x%016lx", mss::c_str(i_target), I, i_data);
FAPI_TRY( mss::putScom(i_target, TT::IO_TX_FET_SLICE_CSCID_REG[I].first, i_data) );

fapi_try_exit:
Expand Down

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