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Set ATTR_MINI_EC for Firmware use
Setting a new attribute that specifies the mini-EC level for use by non-fapi firmware. Change-Id: I48a3f3466af96f9d8d61a2c5701aa44c423cb4c8 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35449 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35603 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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+46
-6
lines changed

2 files changed

+46
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lines changed

src/import/chips/p9/procedures/hwp/perv/p9_getecid.C

Lines changed: 44 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -42,6 +42,19 @@
4242
#include <p9_misc_scom_addresses_fld.H>
4343
#include <p9_const_common.H>
4444

45+
enum DD1_MiniEC_Consts
46+
{
47+
dd_101 = 0b100, // bit field in ecid buffer representing DD1.01
48+
dd_102 = 0b110, // bit field in ecid buffer representing DD1.02
49+
dd_103 = 0b111, // bit field in ecid buffer representing DD1.03
50+
51+
ddLevelMemoryPart1 = dd_102,
52+
ddLevelMemoryPart2 = dd_103,
53+
54+
ddLevelPciePart = dd_101,
55+
56+
};
57+
4558
// The bit locations in ecid_part02 where the DD Level is found. These correspond to ECID bits 173:175
4659
constexpr uint64_t DD_LEVEL(45);
4760
constexpr uint64_t DD_LEVEL_LEN(3);
@@ -107,6 +120,17 @@ static fapi2::ReturnCode setup_memory_work_around_attributes(
107120
const fapi2::buffer<uint64_t>& i_ecid_part)
108121
{
109122
uint8_t l_version = 0;
123+
fapi2::ATTR_MINI_EC_Type l_miniEc = 0;
124+
fapi2::ATTR_EC_Type l_chipEc = 0;
125+
126+
FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_EC, i_target, l_chipEc));
127+
128+
if( l_chipEc != 0x10 )
129+
{
130+
// Nothing to do if this isn't DD1.0
131+
return fapi2::FAPI2_RC_SUCCESS;
132+
}
133+
110134
i_ecid_part.extractToRight<DD_LEVEL, DD_LEVEL_LEN>(l_version);
111135

112136
// Workarounds for modules which are before 1.02 (memory part 1)
@@ -135,6 +159,25 @@ static fapi2::ReturnCode setup_memory_work_around_attributes(
135159
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_SKIP_RD_VREF_VREFSENSE_OVERRIDE, i_target, l_value) );
136160
}
137161

162+
// Set the Mini-EC level for firmware to consume
163+
switch( l_version )
164+
{
165+
case(dd_101):
166+
l_miniEc = 1;
167+
break;
168+
169+
case(dd_102):
170+
l_miniEc = 2;
171+
break;
172+
173+
case(dd_103):
174+
l_miniEc = 3;
175+
break;
176+
}
177+
178+
FAPI_INF("MiniEC=%d", l_miniEc);
179+
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MINI_EC, i_target, l_miniEc) );
180+
138181
return fapi2::FAPI2_RC_SUCCESS;
139182

140183
fapi_try_exit:
@@ -148,7 +191,7 @@ fapi2::ReturnCode p9_getecid(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
148191
fapi2::buffer<uint64_t> l_ecid_part0_data64 = 0;
149192
fapi2::buffer<uint64_t> l_ecid_part1_data64 = 0;
150193
fapi2::buffer<uint64_t> l_ecid_part2_data64 = 0;
151-
fapi2::variable_buffer l_fuseString(fuseString_len);
194+
fapi2::variable_buffer l_fuseString(p9_getecid_fuseString_len);
152195
FAPI_INF("Entering ...");
153196

154197

src/import/chips/p9/procedures/hwp/perv/p9_getecid.H

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -42,12 +42,9 @@
4242

4343
#include <fapi2.H>
4444

45-
enum P9_GETECID_Private_Constants
45+
enum P9_GETECID_Public_Constants
4646
{
47-
fuseString_len = 192, // fuse string length
48-
ddLevelPciePart = 0b100, // bit field in ecid buffer representing DD1.01
49-
ddLevelMemoryPart1 = 0b110, // bit field in ecid buffer representing DD1.02
50-
ddLevelMemoryPart2 = 0b111, // bit field in ecid buffer representing DD1.03
47+
p9_getecid_fuseString_len = 192, // fuse string length
5148
};
5249

5350
typedef fapi2::ReturnCode (*p9_getecid_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&,

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