Updates MCBIST for dual-drop systems

Includes:
1) address configuration updates
2) FIFO/reorder queue updates needed to avoid hangs

Change-Id: Ib5ebbe6166535ebfb4477d2e917cf5a8b057d742
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35984
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35985
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H

@@ -86,6 +86,8 @@ class portTraits<fapi2::TARGET_TYPE_MCA>
         static constexpr uint64_t PHY_PERIODIC_CAL_RELOAD_REG = MCA_DDRPHY_PC_RELOAD_VALUE0_P0;
         static constexpr uint64_t PHY_CAL_TIMER_RELOAD_REG = MCA_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE_P0;
         static constexpr uint64_t PHY_ZCAL_TIMER_RELOAD_REG = MCA_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE_P0;
+        static constexpr uint64_t RRQ_REG = MCA_MBA_RRQ0Q;
+        static constexpr uint64_t WRQ_REG = MCA_MBA_WRQ0Q;
 
         static constexpr uint64_t MAGIC_NUMBER_SIM = 765;
         static constexpr uint64_t MAGIC_NUMBER_NOT_SIM = 196605;
@@ -254,6 +256,9 @@ class portTraits<fapi2::TARGET_TYPE_MCA>
             PER_START = MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_START,
             PER_ABORT_ON_ERR_EN = MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_ABORT_ON_ERR_EN,
             PER_DD2_FIX_DIS = MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_DD2_FIX_DIS,
+
+            RRQ_FIFO_MODE = MCA_MBA_RRQ0Q_CFG_RRQ_FIFO_MODE,
+            WRQ_FIFO_MODE = MCA_MBA_WRQ0Q_CFG_WRQ_FIFO_MODE,
         };
 };
 
@@ -634,6 +639,127 @@ fapi_try_exit:
     return fapi2::current_err;
 }
 
+///
+/// @brief Configures the write reorder queue for MCBIST operations
+/// @param[in] i_target the target to effect
+/// @param[in] i_state to set the bit too
+/// @return FAPI2_RC_SUCCSS iff ok
+///
+inline fapi2::ReturnCode configure_wrq(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, const mss::states i_state)
+{
+    typedef portTraits<fapi2::TARGET_TYPE_MCA> TT;
+
+    fapi2::buffer<uint64_t> l_data;
+
+    // Gets the reg
+    FAPI_TRY(mss::getScom(i_target, TT::WRQ_REG, l_data), "%s failed to getScom from MCA_MBA_WRQ0Q", mss::c_str(i_target));
+
+    // Sets the bit
+    l_data.writeBit<TT::WRQ_FIFO_MODE>(i_state == mss::states::ON);
+
+    // Sets the regs
+    FAPI_TRY(mss::putScom(i_target, TT::WRQ_REG, l_data), "%s failed to putScom to MCA_MBA_WRQ0Q", mss::c_str(i_target));
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+
+///
+/// @brief Configures the write reorder queue bit
+/// @param[in] i_target the target to effect
+/// @param[in] i_state to set the bit too
+/// @return FAPI2_RC_SUCCSS iff ok
+///
+inline fapi2::ReturnCode configure_wrq(const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target,
+                                       const mss::states i_state)
+{
+    // Loops through all MCA targets, hitting all the registers
+    for( const auto& l_mca : mss::find_targets<fapi2::TARGET_TYPE_MCA>(i_target) )
+    {
+        FAPI_TRY(configure_wrq(l_mca, i_state));
+    }
+
+    // In case we don't have any MCA's
+    return fapi2::FAPI2_RC_SUCCESS;
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Configures the read reorder queue for MCBIST operations
+/// @param[in] i_target the target to effect
+/// @param[in] i_state to set the bit too
+/// @return FAPI2_RC_SUCCSS iff ok
+///
+inline fapi2::ReturnCode configure_rrq(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, const mss::states i_state)
+{
+    typedef portTraits<fapi2::TARGET_TYPE_MCA> TT;
+
+    fapi2::buffer<uint64_t> l_data;
+
+    // Gets the reg
+    FAPI_TRY(mss::getScom(i_target, TT::RRQ_REG, l_data), "%s failed to getScom from MCA_MBA_RRQ0Q", mss::c_str(i_target));
+
+    // Sets the bit
+    l_data.writeBit<TT::RRQ_FIFO_MODE>(i_state == mss::states::ON);
+
+    // Sets the regs
+    FAPI_TRY(mss::putScom(i_target, TT::RRQ_REG, l_data), "%s failed to putScom to MCA_MBA_RRQ0Q", mss::c_str(i_target));
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Configures the read reorder queue bit
+/// @param[in] i_target the target to effect
+/// @param[in] i_state to set the bit too
+/// @return FAPI2_RC_SUCCSS iff ok
+///
+inline fapi2::ReturnCode configure_rrq(const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target,
+                                       const mss::states i_state)
+{
+    // Loops through all MCA targets, hitting all the registers
+    for( const auto& l_mca : mss::find_targets<fapi2::TARGET_TYPE_MCA>(i_target) )
+    {
+        FAPI_TRY(configure_rrq(l_mca, i_state));
+    }
+
+    // In case we don't have any MCA's
+    return fapi2::FAPI2_RC_SUCCESS;
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Resets the write/read reorder queue values - needs to be called after MCBIST execution
+/// @tparam T, the fapi2 target type of the target
+/// @param[in] i_target the target to effect
+/// @return FAPI2_RC_SUCCSS iff ok
+///
+template< fapi2::TargetType T>
+fapi2::ReturnCode reset_reorder_queue_settings(const fapi2::Target<T>& i_target)
+{
+    uint8_t l_reorder_queue = 0;
+    FAPI_TRY(reorder_queue_setting(i_target, l_reorder_queue));
+
+    // Changes the reorder queue settings
+    {
+        // Two settings are FIFO and REORDER.  FIFO is a 1 in the registers, while reorder is a 0 state
+        const mss::states l_state = ((l_reorder_queue == fapi2::ENUM_ATTR_MSS_REORDER_QUEUE_SETTING_FIFO) ?
+                                     mss::states::ON : mss::states::OFF);
+        FAPI_TRY(configure_rrq(i_target, l_state), "%s failed to reset read reorder queue settings", mss::c_str(i_target));
+        FAPI_TRY(configure_wrq(i_target, l_state), "%s failed to reset read reorder queue settings", mss::c_str(i_target));
+    }
+
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
 }// mss
 
 #endif

src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.C

@@ -437,6 +437,9 @@ fapi2::ReturnCode execute( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target,
 
     FAPI_TRY( clear_errors(i_target) );
 
+    // Configures the write/read FIFO bit
+    FAPI_TRY( load_fifo_mode( i_target, i_program) );
+
     // Slam the address generator config
     FAPI_TRY( load_addr_gen(i_target, i_program) );
 
@@ -631,7 +634,7 @@ fapi_try_exit:
     return fapi2::current_err;
 }
 
-} // namespace
+} // namespace MCBIST
 
 // Note: outside of the mcbist namespace
 

src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.H

@@ -48,6 +48,7 @@
 #include <lib/utils/num.H>
 #include <lib/mcbist/patterns.H>
 #include <lib/mcbist/settings.H>
+#include <lib/mc/port.H>
 
 namespace mss
 {
@@ -1020,6 +1021,7 @@ class program
             iv_config(0),
             iv_control(0),
             iv_async(false),
+            iv_fifo_mode(true),
             iv_pattern(PATTERN_0),
             iv_random24_data_seed(RANDOM24_SEEDS_0),
             iv_random24_seed_map(RANDOM24_SEED_MAP_0),
@@ -2022,6 +2024,18 @@ class program
             return;
         }
 
+        ///
+        /// @brief Enable or disable FIFO mode
+        /// @param[in] i_program the program in question
+        /// @param[in] i_mode mss::ON to enable, programs will run in FIFO vs mainline mode
+        /// @return void
+        ///
+        inline void change_fifo_mode( const bool i_mode )
+        {
+            iv_fifo_mode = i_mode;
+            return;
+        }
+
         ///
         /// @brief Select the port(s) to be used by the MCBIST
         /// @param[in] i_ports uint64_t representing the ports. Multiple bits set imply broadcast
@@ -2185,6 +2199,7 @@ class program
             l_equal &= iv_config == i_rhs.iv_config;
             l_equal &= iv_control == i_rhs.iv_control;
             l_equal &= iv_async == i_rhs.iv_async;
+            l_equal &= iv_fifo_mode == i_rhs.iv_fifo_mode;
             l_equal &= iv_pattern == i_rhs.iv_pattern;
             l_equal &= iv_thresholds == i_rhs.iv_thresholds;
             l_equal &= iv_data_rotate_cnfg == i_rhs.iv_data_rotate_cnfg;
@@ -2244,6 +2259,9 @@ class program
         // True iff we want to run in asynchronous mode
         bool                        iv_async;
 
+        // True if we want to run in FIFO mode - defaults to true as this is needed for most MCBIST tests
+        bool                        iv_fifo_mode;
+
         // The pattern for the pattern generator
         uint64_t                    iv_pattern;
 
@@ -2817,6 +2835,33 @@ inline fapi2::ReturnCode load_random24b_seeds( const fapi2::Target<T>& i_target,
     return load_random24b_seeds(i_target, i_program.iv_random24_data_seed, i_program.iv_random24_seed_map);
 }
 
+///
+/// @brief Loads the FIFO value if needed
+/// @tparam T, the fapi2::TargetType - derived
+/// @tparam TT, the mcbistTraits associated with T - derived
+/// @param[in] i_target the target to effect
+/// @param[in] i_program the mcbist::program
+/// @return FAPI2_RC_SUCCSS iff ok
+///
+template< fapi2::TargetType T, typename TT = mcbistTraits<T> >
+inline fapi2::ReturnCode load_fifo_mode( const fapi2::Target<T>& i_target, const mcbist::program<T>& i_program )
+{
+    // if the FIFO load is not needed, just exit out
+    if(!i_program.iv_fifo_mode)
+    {
+        return fapi2::FAPI2_RC_SUCCESS;
+    }
+
+    // Turns on FIFO mode
+    constexpr mss::states FIFO_ON = mss::states::ON;
+
+    FAPI_TRY(mss::configure_wrq(i_target, FIFO_ON));
+    FAPI_TRY(mss::configure_rrq(i_target, FIFO_ON));
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
 ///
 /// @brief Load MCBIST data patterns and configuration
 /// @tparam T, the fapi2::TargetType - derived

src/import/chips/p9/procedures/hwp/memory/lib/mcbist/memdiags.H

@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* Contributors Listed Below - COPYRIGHT 2016,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -108,6 +108,9 @@ class operation
             iv_const(i_const)
         {
             FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), iv_is_sim) );
+
+            // Disables FIFO mode, so memdiags will run in mainline mode
+            iv_program.change_fifo_mode(false);
             return;
 
         fapi_try_exit:

src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H

@@ -16871,6 +16871,28 @@ fapi_try_exit:
     return fapi2::current_err;
 }
 
+///
+/// @brief ATTR_MSS_REORDER_QUEUE_SETTING getter
+/// @param[in] const ref to the TARGET_TYPE_MCBIST
+/// @param[out] uint8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (NODIM A)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Contains the settings for write/read reorder
+/// queue
+///
+inline fapi2::ReturnCode reorder_queue_setting(const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target,
+        uint8_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_REORDER_QUEUE_SETTING, i_target, o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_MSS_REORDER_QUEUE_SETTING: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
 
 ///
 /// @brief ATTR_EFF_DRAM_GEN getter

src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml

@@ -3112,4 +3112,19 @@
         <mssAccessorName>mvpd_fwms</mssAccessorName>
     </attribute>
 
+    <attribute>
+        <id>ATTR_MSS_REORDER_QUEUE_SETTING</id>
+        <targetType>TARGET_TYPE_MCBIST</targetType>
+        <description>
+            Contains the settings for write/read reorder queue
+        </description>
+        <default>REORDER</default>
+        <initToZero></initToZero>
+        <writeable/>
+        <enum>REORDER = 0, FIFO = 1</enum>
+        <valueType>uint8</valueType>
+        <writeable/>
+        <mssAccessorName>reorder_queue_setting</mssAccessorName>
+    </attribute>
+
 </attributes>

src/usr/targeting/common/xmltohb/attribute_types.xml

@@ -32888,4 +32888,20 @@ Measured in GB</description>
     </hwpfToHbAttrMap>
 </attribute>
 
+<attribute>
+    <id>MSS_REORDER_QUEUE_SETTING</id>
+    <description>Contains the settings for write/read reorder queue</description>
+    <simpleType>
+        <uint8_t>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_REORDER_QUEUE_SETTING</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
 </attributes>

src/usr/targeting/common/xmltohb/target_types.xml

@@ -1924,6 +1924,7 @@
     <attribute><id>VDD_ID</id></attribute>
     <attribute><id>AVDD_ID</id></attribute>
 
+    <attribute><id>MSS_REORDER_QUEUE_SETTING</id></attribute>
 </targetType>
 
 <targetType>