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istepdispatcher: output current istep to LPC port 80h
Adds optional support to output istep progress to LPC I/O port 80h similar to POST codes on x86 BIOS boot process. Resolves #104 Signed-off-by: Robert Lippert <rlippert@google.com> Change-Id: I0e2a977863c37d5e6b72a890da9a1516a0a5bf58 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41404 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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src/usr/initservice/istepdispatcher/HBconfig

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@@ -13,4 +13,7 @@ config SIO_ISTEP_CONTROL
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help
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Allows istep control via SIO scratch registers.
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Typical usage is via mailbox (scom) scratch registers.
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config ISTEP_LPC_PORT80_DEBUG
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default n
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help
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Writes ISTEP progress to LPC port 80h.

src/usr/initservice/istepdispatcher/istepdispatcher.C

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@@ -65,6 +65,7 @@
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#include <console/consoleif.H>
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#include <isteps/hwpisteperror.H>
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#include <pnor/pnorif.H>
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#include <lpc/lpcif.H>
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#ifdef CONFIG_BMC_IPMI
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#include <ipmi/ipmiwatchdog.H> //IPMI watchdog timer
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#include <ipmi/ipmipowerstate.H> //IPMI System ACPI Power State
@@ -1953,6 +1954,17 @@ errlHndl_t IStepDispatcher::sendProgressCode(bool i_needsLock)
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Util::writeScratchReg( SPLESS::MBOX_SCRATCH_REG5,
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l_scratch5.data32 );
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#ifdef CONFIG_ISTEP_LPC_PORT80_DEBUG
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// Starting port 80h value for hostboot isteps. Each step started will
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// increase the value by one.
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static uint8_t port80_val = 0x30;
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static size_t port80_len = sizeof(port80_val);
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err = deviceWrite(TARGETING::MASTER_PROCESSOR_CHIP_TARGET_SENTINEL,
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&port80_val, port80_len,
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DEVICE_LPC_ADDRESS(LPC::TRANS_IO, 0x80));
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delete err; // this is debug only, ignore any errors
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port80_val++;
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#endif
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//--- Display step on serial console
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#ifdef CONFIG_CONSOLE_OUTPUT_PROGRESS

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