p9_fbc_eff_config -- update LE (2 chips per group) base epsilon table

Change-Id: I21e1418bc48746967d097cd0130266f8711e1a0d
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36724
Reviewed-by: SHELTON LEUNG <sleung@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36727
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

src/import/chips/p9/procedures/hwp/nest/p9_fbc_eff_config.C

@@ -53,11 +53,11 @@ const uint8_t NUM_EPSILON_READ_TIERS = 3;
 const uint8_t NUM_EPSILON_WRITE_TIERS = 2;
 
 // LE epsilon (2 chips per-group)
-const uint32_t EPSILON_R_T0_LE[] = {    4,    5,    5,    5,    6,    8 };
-const uint32_t EPSILON_R_T1_LE[] = {    4,    5,    5,    5,    6,    8 };
-const uint32_t EPSILON_R_T2_LE[] = {   47,   48,   49,   51,   54,   68 };
+const uint32_t EPSILON_R_T0_LE[] = {    7,    7,    7,    7,    8,    8 };
+const uint32_t EPSILON_R_T1_LE[] = {    7,    7,    7,    7,    8,    8 };
+const uint32_t EPSILON_R_T2_LE[] = {   61,   62,   63,   65,   68,   82 };
 const uint32_t EPSILON_W_T0_LE[] = {    0,    0,    0,    0,    0,    0 };
-const uint32_t EPSILON_W_T1_LE[] = {    0,    0,    0,    0,    0,    0 };
+const uint32_t EPSILON_W_T1_LE[] = {    9,    9,    7,    5,    1,    0 };
 
 // TODO: These values need to be updated whenever HE system info is available.
 // HE epsilon (4 chips per-group)