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PM: Change in self sestore region for lab.
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To support a lab scenario, first instruction of a thread
SPR restore region and SCOM Restore region should be a BLR
instruction instead of an ATTN instruction. This prevents a
thread from hitting attention if SPR restore entries don't
exist for it.

Change-Id: I86a268d2c8ec0ed4955dc37f338fca8f7410305e
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33877
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: ASHISH A. MORE <ashish.more@in.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33880
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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@premsjha @dcrowell77
premsjha authored and dcrowell77 committed Feb 2, 2017
1 parent 16ed14f commit a6a1c07
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Showing 4 changed files with 90 additions and 16 deletions.
3 changes: 3 additions & 0 deletions src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H
View file
Expand Up @@ -307,11 +307,14 @@ enum
MAX_CORES_PER_EX = 2,
CORE0_CHIPLET_ID = 0x20,
PAD_OPCODE = 0x00000200, //ATTN Opcode
BLR_INST = 0x4e800020, //blr instruction
THREAD_RESTORE_AREA_SIZE = 2048,
PPE_RESERVE_AREA = 0x200,
FUSED_MODE = 0xBB,
NONFUSED_MODE = 0xAA,
PK_DBG_PTR_AREA_SIZE = 64,
SCOM_ENTRY_SIZE = 16, // 4B pad, 4B address, 8B data
SCOM_RESTORE_PER_CHIPLET = 64, // size in words (16B * 16)/4

//---- QPMR ----
QPMR_OFFSET = HOMER_QPMR_REGION_NUM * ONE_MB,
Expand Down
88 changes: 79 additions & 9 deletions src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
View file
Expand Up @@ -374,7 +374,55 @@ extern "C"
return exChipletId;
}

//-------------------------------------------------------------------------
//-------------------------------------------------------------------------------------------------
void initScomRegion( Homerlayout_t* i_pChipHomer, PlatId i_platId )
{
FAPI_DBG(">initScomRegion");

do
{
uint32_t* pInitScom = NULL;
uint32_t initLength = MAX_CACHE_CHIPLET;
uint32_t fillPattern = SWIZZLE_4_BYTE(PAD_OPCODE);

if( ( PLAT_SELF != i_platId ) && ( PLAT_SGPE != i_platId ) )
{
FAPI_ERR("SCOM Region not defined for given platform 0x%08x", i_platId );
break;
}

if( PLAT_SELF == i_platId )
{
pInitScom = (uint32_t*)i_pChipHomer->cpmrRegion.selfRestoreRegion.coreScom;
initLength = MAX_CORES_PER_CHIP;

}

if( PLAT_SGPE == i_platId )
{
pInitScom = (uint32_t*)i_pChipHomer->qpmrRegion.cacheScomRegion;
}

uint32_t wordCnt = 0;
uint32_t scomSize = CACHE_SCOM_RESTORE_SIZE >> 2;

for( wordCnt = 0; wordCnt < scomSize; wordCnt++ )
{
memcpy( (pInitScom + wordCnt), &fillPattern, sizeof(uint32_t) );
}

fillPattern = SWIZZLE_4_BYTE(BLR_INST);

for( wordCnt = 0; wordCnt < initLength; wordCnt++ )
{
memcpy( (pInitScom + (wordCnt * SCOM_RESTORE_PER_CHIPLET)) , &fillPattern, sizeof(uint32_t) );
}
}
while(0);

FAPI_DBG("<initScomRegion");
}
//-------------------------------------------------------------------------------------------------

uint32_t validateSramImageSize( Homerlayout_t* i_pChipHomer, uint32_t& o_sramImgSize )
{
Expand Down Expand Up @@ -909,6 +957,8 @@ extern "C"
break;
}

initScomRegion( i_pChipHomer, PLAT_SGPE );

o_qpmrHdr.sgpeImgOffset = o_qpmrHdr.bootLoaderOffset + SGPE_LVL_2_BOOT_LOAD_SIZE;

FAPI_DBG("SGPE Hcode QPMR Offset = 0x%08X, Size = 0x%08X",
Expand Down Expand Up @@ -1025,17 +1075,37 @@ extern "C"
//Padding SPR restore area with ATTN Opcode
FAPI_INF("Padding CPMR Core Restore portion with Attn opcodes");
uint32_t wordCnt = 0;
uint32_t l_fillPattern = SWIZZLE_4_BYTE(PAD_OPCODE);
uint32_t l_fillBlr = SWIZZLE_4_BYTE(BLR_INST);
uint32_t l_fillAttn = SWIZZLE_4_BYTE(PAD_OPCODE);

while( wordCnt < CORE_RESTORE_SIZE )
{

uint32_t l_fillPattern = 0;

if( ( 0 == wordCnt ) || ( 0 == ( wordCnt % THREAD_RESTORE_AREA_SIZE ) ))
{
l_fillPattern = l_fillBlr;
}
else
{
l_fillPattern = l_fillAttn;
}

//Lab Need: First instruction in thread SPR restore region should be a blr instruction.
//This helps in a specific lab scenario. If Self Restore region is populated only for
//select number of threads, other threads will not hit attention during the self restore
//sequence. Instead, execution will hit a blr and control should return to thread launcher
//region.

memcpy( (uint32_t*)&i_pChipHomer->cpmrRegion.selfRestoreRegion.coreSelfRestore[wordCnt],
&l_fillPattern,
sizeof( uint32_t ));
wordCnt += 4;
}

updateCpmrHeaderSR( i_pChipHomer, i_fusedState );
initScomRegion( i_pChipHomer, PLAT_SELF );
}
while(0);

Expand Down Expand Up @@ -1205,7 +1275,7 @@ extern "C"
return retCode;
}

//------------------------------------------------------------------------------
//------------------------------------------------------------------------------

/**
* @brief get a blob of platform rings in a temp buffer.
Expand Down Expand Up @@ -1292,7 +1362,7 @@ extern "C"
return retCode;
}

//------------------------------------------------------------------------------
//------------------------------------------------------------------------------

uint32_t layoutSgpeScanOverride( Homerlayout_t* i_pHomer,
void* i_pOverride,
Expand Down Expand Up @@ -1403,7 +1473,7 @@ extern "C"
return rc;
}

//------------------------------------------------------------------------------
//------------------------------------------------------------------------------

/**
* @brief creates a lean scan ring layout for core specific rings in HOMER.
Expand Down Expand Up @@ -1497,7 +1567,7 @@ extern "C"
return rc;
}

//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/**
* @brief creates a lean scan ring layout for core specific rings in HOMER.
* @param i_pHOMER points to HOMER image.
Expand Down Expand Up @@ -1657,7 +1727,7 @@ extern "C"
return rc;
}

//------------------------------------------------------------------------------
//------------------------------------------------------------------------------

uint32_t layoutCmeScanOverride( Homerlayout_t* i_pHomer,
void* i_pOverride,
Expand Down Expand Up @@ -1752,7 +1822,7 @@ extern "C"
return rc;
}

//------------------------------------------------------------------------------
//------------------------------------------------------------------------------

/**
* @brief creates a lean scan ring layout for core rings in HOMER.
Expand Down Expand Up @@ -1894,7 +1964,7 @@ extern "C"
}


//------------------------------------------------------------------------------
//------------------------------------------------------------------------------

/**
* @brief creates a scan ring layout for quad common rings in HOMER.
Expand Down
10 changes: 6 additions & 4 deletions src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C
View file
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2016 */
/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -526,7 +526,8 @@ StopReturnCode_t p9_stop_save_cpureg( void* const i_pImage,
&(chipHomer->coreThreadRestore[coreId][threadId].coreArea[0]);
}

if( SWIZZLE_4_BYTE(ATTN_OPCODE) == *(uint32_t*)pThreadLocation )
if( ( SWIZZLE_4_BYTE(BLR_INST) == *(uint32_t*)pThreadLocation ) ||
( SWIZZLE_4_BYTE(ATTN_OPCODE) == *(uint32_t*) pThreadLocation ) )
{
// table for given core id doesn't exit. It needs to be
// defined.
Expand Down Expand Up @@ -864,6 +865,7 @@ StopReturnCode_t p9_stop_save_scom( void* const i_pImage,
uint32_t swizzleAttn = SWIZZLE_4_BYTE(ATTN_OPCODE);
uint32_t swizzleEntry = SWIZZLE_4_BYTE(SCOM_ENTRY_START);
uint32_t index = 0;
uint32_t swizzleBlr = SWIZZLE_4_BYTE(BLR_INST);

for( index = 0; index < entryLimit; ++index )
{
Expand All @@ -876,8 +878,8 @@ StopReturnCode_t p9_stop_save_scom( void* const i_pImage,
}

if( (( nopInst == entrySwzAddress ) ||
( swizzleAttn == entrySwzAddress )) &&
( !pNopLocation ) )
( swizzleAttn == entrySwzAddress ) ||
( swizzleBlr == entrySwzAddress )) && ( !pNopLocation ) )
{
pNopLocation = &pScomEntry[index];
}
Expand Down
5 changes: 2 additions & 3 deletions src/import/chips/p9/procedures/utils/stopreg/p9_stop_data_struct.H
View file
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2016 */
/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -64,8 +64,7 @@ typedef struct
*/
typedef struct
{
uint8_t threadArea[THREAD_SECTN_SIZE];
uint8_t reserve[THREAD_AREA_SIZE - THREAD_SECTN_SIZE];
uint8_t threadArea[THREAD_AREA_SIZE];
uint8_t coreArea[CORE_SPR_SECTN_SIZE];
} SprRestoreArea_t;

Expand Down

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