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aamarindcrowell77
aamarin
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dcrowell77
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Remove ZQCAL redundant CCS inst, move to draminit_training
Lab requested to move ZQCL to draminit_training to control (with granularity) all enabled cal steps from an attribute in training. Also removing redundant ZQCAL being sent out for both a-side/b-side and addr_mirroring since this only applies to MRS cmds. Added new attribute proposal for CAL_STEPS_ENABLE to account for LRDIMM training steps and more control bits such as INITIAL_PAT_WR and WR_VRE_LATCH Change-Id: Ibb758af74966a5dd659bf3dda86f283f73956bca Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38648 Reviewed-by: Louis Stermole <stermole@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38650 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
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‎src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -43,6 +43,7 @@
4343
#include <lib/dimm/bcw_load_ddr4.H>
4444
#include <lib/phy/dp16.H>
4545
#include <lib/dimm/ddr4/control_word_ddr4.H>
46+
#include <lib/eff_config/timing.H>
4647

4748
namespace mss
4849
{

‎src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C

Lines changed: 4 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -84,11 +84,7 @@ fapi2::ReturnCode mrs_load( const fapi2::Target<TARGET_TYPE_DIMM>& i_target,
8484
{
8585
FAPI_INF("ddr4::mrs_load %s", mss::c_str(i_target));
8686

87-
fapi2::buffer<uint16_t> l_cal_steps;
88-
uint64_t tDLLK = 0;
89-
uint8_t l_dimm_type = 0;
90-
91-
static std::vector< mrs_data<TARGET_TYPE_MCBIST> > l_mrs_data =
87+
static const std::vector< mrs_data<TARGET_TYPE_MCBIST> > MRS_DATA =
9288
{
9389
// JEDEC ordering of MRS per DDR4 power on sequence
9490
{ 3, mrs03, mrs03_decode, mss::tmrd() },
@@ -97,64 +93,22 @@ fapi2::ReturnCode mrs_load( const fapi2::Target<TARGET_TYPE_DIMM>& i_target,
9793
{ 4, mrs04, mrs04_decode, mss::tmrd() },
9894
{ 2, mrs02, mrs02_decode, mss::tmrd() },
9995
{ 1, mrs01, mrs01_decode, mss::tmrd() },
100-
101-
// We need to wait either tmod or tmrd before zqcl.
102-
{ 0, mrs00, mrs00_decode, std::max(mss::tmrd(), mss::tmod(i_target)) },
96+
// We need to wait tmod before zqcl, a non-mrs command
97+
{ 0, mrs00, mrs00_decode, mss::tmod(i_target) },
10398
};
10499

105100
std::vector< uint64_t > l_ranks;
106101
FAPI_TRY( mss::rank::ranks(i_target, l_ranks) );
107-
FAPI_TRY( mss::tdllk(i_target, tDLLK) );
108102

109103
// Load MRS
110-
for (const auto& d : l_mrs_data)
104+
for (const auto& d : MRS_DATA)
111105
{
112106
for (const auto& r : l_ranks)
113107
{
114108
FAPI_TRY( mrs_engine(i_target, d, r, io_inst) );
115109
}
116110
}
117111

118-
// Load ZQ Cal Long instruction only if the bit in the cal steps says to do so.
119-
FAPI_TRY( mss::cal_step_enable(i_target, l_cal_steps) );
120-
121-
if (l_cal_steps.getBit<EXT_ZQCAL>() != 0)
122-
{
123-
for (const auto& r : l_ranks)
124-
{
125-
// Note: this isn't general - assumes Nimbus via MCBIST instruction here BRS
126-
ccs::instruction_t<TARGET_TYPE_MCBIST> l_inst_a_side = ccs::zqcl_command<TARGET_TYPE_MCBIST>(i_target, r);
127-
ccs::instruction_t<TARGET_TYPE_MCBIST> l_inst_b_side;
128-
129-
FAPI_TRY( mss::address_mirror(i_target, r, l_inst_a_side) );
130-
l_inst_b_side = mss::address_invert(l_inst_a_side);
131-
132-
l_inst_a_side.arr1.insertFromRight<MCBIST_CCS_INST_ARR1_00_IDLES,
133-
MCBIST_CCS_INST_ARR1_00_IDLES_LEN>(tDLLK + mss::tzqinit());
134-
l_inst_b_side.arr1.insertFromRight<MCBIST_CCS_INST_ARR1_00_IDLES,
135-
MCBIST_CCS_INST_ARR1_00_IDLES_LEN>(tDLLK + mss::tzqinit());
136-
137-
// There's nothing to decode here.
138-
FAPI_INF("ZQCL 0x%016llx:0x%016llx %s:rank %d a-side",
139-
l_inst_a_side.arr0, l_inst_a_side.arr1, mss::c_str(i_target), r);
140-
FAPI_INF("ZQCL 0x%016llx:0x%016llx %s:rank %d b-side",
141-
l_inst_b_side.arr0, l_inst_b_side.arr1, mss::c_str(i_target), r);
142-
143-
// Add both to the CCS program
144-
io_inst.push_back(l_inst_a_side);
145-
io_inst.push_back(l_inst_b_side);
146-
}
147-
}
148-
149-
// For LRDIMMs, program BCW to send ZQCal Long command to all databuffers
150-
// in broadcast mode
151-
FAPI_TRY( eff_dimm_type(i_target, l_dimm_type) );
152-
153-
if( l_dimm_type == fapi2::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM )
154-
{
155-
FAPI_TRY( set_command_space(i_target, command::ZQCL, io_inst) );
156-
}
157-
158112
fapi_try_exit:
159113
return fapi2::current_err;
160114
}

‎src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.C

Lines changed: 131 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,3 +22,134 @@
2222
/* permissions and limitations under the License. */
2323
/* */
2424
/* IBM_PROLOG_END_TAG */
25+
26+
///
27+
/// @file zqcal.C
28+
/// @brief Subroutines to send ZQCL commands
29+
///
30+
// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com>
31+
// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com>
32+
// *HWP Team: Memory
33+
// *HWP Level: 2
34+
// *HWP Consumed by: FSP:HB
35+
36+
#include <vector>
37+
#include <fapi2.H>
38+
39+
#include <lib/dimm/ddr4/zqcal.H>
40+
#include <lib/dimm/ddr4/data_buffer_ddr4.H>
41+
#include <lib/ccs/ccs.H>
42+
#include <lib/eff_config/timing.H>
43+
44+
using fapi2::TARGET_TYPE_MCBIST;
45+
using fapi2::TARGET_TYPE_MCA;
46+
using fapi2::TARGET_TYPE_DIMM;
47+
48+
namespace mss
49+
{
50+
51+
///
52+
/// @brief Setup DRAM ZQCL
53+
/// Specializaton for TARGET_TYPE_DIMM
54+
/// @param[in] i_target the target associated with this cal
55+
/// @param[in] i_rank the current rank
56+
/// @param[in,out] io_inst a vector of CCS instructions we should add to
57+
/// @return FAPI2_RC_SUCCESS iff setup was successful
58+
///
59+
template<>
60+
fapi2::ReturnCode setup_dram_zqcal( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
61+
const uint64_t i_rank,
62+
std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst)
63+
{
64+
ccs::instruction_t<TARGET_TYPE_MCBIST> l_inst;
65+
66+
uint64_t tDLLK = 0;
67+
FAPI_TRY( mss::tdllk(i_target, tDLLK) );
68+
69+
// Note: this isn't general - assumes Nimbus via MCBIST instruction here BRS
70+
l_inst = ccs::zqcl_command<TARGET_TYPE_MCBIST>(i_target, i_rank);
71+
72+
l_inst.arr1.insertFromRight<MCBIST_CCS_INST_ARR1_00_IDLES,
73+
MCBIST_CCS_INST_ARR1_00_IDLES_LEN>(tDLLK + mss::tzqinit());
74+
75+
// There's nothing to decode here.
76+
FAPI_INF("ZQCL 0x%016llx:0x%016llx %s:rank %d",
77+
l_inst.arr0, l_inst.arr1, mss::c_str(i_target), i_rank);
78+
79+
// Add both to the CCS program
80+
io_inst.push_back(l_inst);
81+
82+
fapi_try_exit:
83+
return fapi2::current_err;
84+
}
85+
86+
///
87+
/// @brief Setup LRDIMM data buffer ZQCL
88+
/// Specializaton for TARGET_TYPE_DIMM
89+
/// @param[in] i_target the target associated with this cal
90+
/// @param[in,out] io_inst a vector of CCS instructions we should add to
91+
/// @return FAPI2_RC_SUCCESS iff setup was successful
92+
///
93+
template<>
94+
fapi2::ReturnCode setup_data_buffer_zqcal( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
95+
std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst)
96+
{
97+
// For LRDIMMs, program BCW to send ZQCal Long command to all data buffers
98+
// in broadcast mode
99+
uint8_t l_dimm_type = 0;
100+
FAPI_TRY( eff_dimm_type(i_target, l_dimm_type) );
101+
102+
if( l_dimm_type != fapi2::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM )
103+
{
104+
FAPI_INF("%s Skipping LRDIMM data buffer ZQCL, only done on LRDIMMs", mss::c_str(i_target));
105+
return fapi2::FAPI2_RC_SUCCESS;
106+
}
107+
108+
FAPI_TRY( ddr4::set_command_space(i_target, ddr4::command::ZQCL, io_inst) );
109+
110+
fapi_try_exit:
111+
return fapi2::current_err;
112+
}
113+
114+
///
115+
/// @brief Setup and execute DRAM ZQCL
116+
/// Specializaton for TARGET_TYPE_MCA
117+
/// @param[in] i_target the target associated with this cal
118+
/// @param[in] i_cal_steps_enabled fapi2::buffer<uint16_t> representing the cal steps to enable
119+
/// @return FAPI2_RC_SUCCESS iff setup was successful
120+
///
121+
template<>
122+
fapi2::ReturnCode setup_and_execute_zqcal( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
123+
const fapi2::buffer<uint32_t>& i_cal_steps_enabled)
124+
{
125+
mss::ccs::program<TARGET_TYPE_MCBIST> l_program;
126+
127+
for ( const auto& d : mss::find_targets<fapi2::TARGET_TYPE_DIMM>(i_target) )
128+
{
129+
// If this bit isn't set, nothing to do here...
130+
if ( i_cal_steps_enabled.getBit<DRAM_ZQCAL>() )
131+
{
132+
std::vector<uint64_t> l_ranks;
133+
FAPI_TRY( mss::rank::ranks(d, l_ranks) );
134+
135+
for( const auto& r : l_ranks)
136+
{
137+
FAPI_TRY( mss::setup_dram_zqcal(d, r, l_program.iv_instructions) );
138+
}// ranks
139+
}
140+
141+
// If this bit isn't set, nothing to do here...
142+
if ( i_cal_steps_enabled.getBit<DB_ZQCAL>() )
143+
{
144+
FAPI_TRY( mss::setup_data_buffer_zqcal(d, l_program.iv_instructions) );
145+
}
146+
}// dimm
147+
148+
// execute ZQCAL instructions
149+
FAPI_TRY( mss::ccs::execute(mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target), l_program, i_target) );
150+
151+
fapi_try_exit:
152+
return fapi2::current_err;
153+
}
154+
155+
} // ns mss

‎src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.H

Lines changed: 61 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,3 +22,64 @@
2222
/* permissions and limitations under the License. */
2323
/* */
2424
/* IBM_PROLOG_END_TAG */
25+
26+
///
27+
/// @file zqcal.H
28+
/// @brief Subroutines to send ZQCL commands
29+
///
30+
// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com>
31+
// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com>
32+
// *HWP Team: Memory
33+
// *HWP Level: 2
34+
// *HWP Consumed by: FSP:HB
35+
36+
#ifndef _MSS_ZQCAL_H_
37+
#define _MSS_ZQCAL_H_
38+
39+
#include <vector>
40+
#include <fapi2.H>
41+
#include <lib/ccs/ccs.H>
42+
43+
namespace mss
44+
{
45+
46+
///
47+
/// @brief Setup DRAM ZQCL
48+
/// @tparam T the target type associated with this cal
49+
/// @tparam TT the target type of the CCS instruction
50+
/// @param[in] i_target the target associated with this cal
51+
/// @param[in] i_rank the current rank
52+
/// @param[in,out] io_inst a vector of CCS instructions we should add to
53+
/// @return FAPI2_RC_SUCCESS iff setup was successful
54+
///
55+
template< fapi2::TargetType T, fapi2::TargetType TT >
56+
fapi2::ReturnCode setup_dram_zqcal( const fapi2::Target<T>& i_target,
57+
const uint64_t i_rank,
58+
std::vector< ccs::instruction_t<TT> >& io_inst);
59+
60+
///
61+
/// @brief Setup LRDIMM data buffer ZQCL
62+
/// @tparam T the target type associated with this cal
63+
/// @tparam TT the target type of the CCS instruction
64+
/// @param[in] i_target the target associated with this cal
65+
/// @param[in,out] io_inst a vector of CCS instructions we should add to
66+
/// @return FAPI2_RC_SUCCESS iff setup was successful
67+
///
68+
template< fapi2::TargetType T, fapi2::TargetType TT >
69+
fapi2::ReturnCode setup_data_buffer_zqcal( const fapi2::Target<T>& i_target,
70+
std::vector< ccs::instruction_t<TT> >& io_inst);
71+
72+
///
73+
/// @brief Setup and execute DRAM ZQCL
74+
/// @tparam T, the target type associated with this cal
75+
/// @param[in] i_target the target associated with this cal
76+
/// @param[in] i_cal_steps_enabled fapi2::buffer<uint16_t> representing the cal steps to enable
77+
/// @return FAPI2_RC_SUCCESS iff setup was successful
78+
///
79+
template< fapi2::TargetType T >
80+
fapi2::ReturnCode setup_and_execute_zqcal( const fapi2::Target<T>& i_target,
81+
const fapi2::buffer<uint32_t>& i_cal_steps_enabled);
82+
83+
}// mss
84+
85+
#endif

‎src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C

Lines changed: 16 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -4574,20 +4574,17 @@ fapi_try_exit:
45744574
///
45754575
fapi2::ReturnCode eff_dimm::cal_step_enable()
45764576
{
4577-
// These constexpr values are taken from the defiitions in ATTR_MSS_CAL_STEP_ENABLE
4578-
// RD/WR VREF correspond to 0x0400 and 0x0100 respectively.
4579-
constexpr uint64_t ONLY_1D = 0xFAC0;
4580-
constexpr uint64_t RD_VREF_WR_VREF_1D = 0xFFC0;
4581-
const uint16_t l_cal_step_value = (mss::chip_ec_feature_skip_hw_vref_cal(iv_mcs) ? ONLY_1D : RD_VREF_WR_VREF_1D);
4577+
const uint32_t l_cal_step_value = (mss::chip_ec_feature_skip_hw_vref_cal(iv_mcs) ?
4578+
RUN_CAL_SKIP_WR_RD_2D_VREF : RUN_ALL_CAL_STEPS);
45824579

45834580
FAPI_DBG("%s %s running HW VREF cal. cal_step value: 0x%0x VREF", mss::c_str(iv_mcs),
45844581
mss::chip_ec_feature_skip_hw_vref_cal(iv_mcs) ? "not" : "", l_cal_step_value);
45854582

45864583
// Sets up the vector
4587-
std::vector<uint16_t> l_cal_step(PORTS_PER_MCS, l_cal_step_value);
4584+
std::vector<uint32_t> l_cal_step(PORTS_PER_MCS, l_cal_step_value);
45884585

4589-
// Sets the values
4590-
return FAPI_ATTR_SET(fapi2::ATTR_MSS_CAL_STEP_ENABLE, iv_mcs, UINT16_VECTOR_TO_1D_ARRAY(l_cal_step, PORTS_PER_MCS));
4586+
// Sets the value
4587+
return FAPI_ATTR_SET(fapi2::ATTR_MSS_CAL_STEP_ENABLE, iv_mcs, UINT32_VECTOR_TO_1D_ARRAY(l_cal_step, PORTS_PER_MCS));
45914588
}
45924589

45934590
///
@@ -4597,8 +4594,9 @@ fapi2::ReturnCode eff_dimm::cal_step_enable()
45974594
fapi2::ReturnCode eff_dimm::rdvref_enable_bit()
45984595
{
45994596
// This enables which bits should be run for RD VREF, all 1's indicates that all bits should be run
4600-
constexpr uint64_t DISABLE = 0x0000;
4601-
constexpr uint64_t ENABLE = 0xFFFF;
4597+
constexpr uint16_t DISABLE = 0x0000;
4598+
constexpr uint16_t ENABLE = 0xFFFF;
4599+
46024600
const uint16_t l_vref_enable_value = (mss::chip_ec_feature_skip_hw_vref_cal(iv_mcs) ? DISABLE : ENABLE);
46034601

46044602
FAPI_DBG("%s %s running HW VREF cal. VREF enable value: 0x%0x", mss::c_str(iv_mcs),
@@ -4608,16 +4606,21 @@ fapi2::ReturnCode eff_dimm::rdvref_enable_bit()
46084606
std::vector<uint16_t> l_vref_enable(PORTS_PER_MCS, l_vref_enable_value);
46094607

46104608
// Sets the values
4611-
return FAPI_ATTR_SET(fapi2::ATTR_MSS_RDVREF_CAL_ENABLE, iv_mcs, UINT16_VECTOR_TO_1D_ARRAY(l_vref_enable,
4612-
PORTS_PER_MCS));
4609+
return FAPI_ATTR_SET(fapi2::ATTR_MSS_RDVREF_CAL_ENABLE,
4610+
iv_mcs,
4611+
UINT16_VECTOR_TO_1D_ARRAY(l_vref_enable, PORTS_PER_MCS));
46134612
}
46144613

46154614
///
4616-
/// @brief Determines and sets ATTR_MSS_PHY_SEQ_REFRESH_
4615+
/// @brief Determines and sets ATTR_MSS_PHY_SEQ_REFRESH
46174616
/// @return fapi2::FAPI2_RC_SUCCESS if okay
46184617
///
46194618
fapi2::ReturnCode eff_dimm::phy_seq_refresh()
46204619
{
4620+
// default setting is to turn on this workaround, this
4621+
// isn't an ec_chip_feature attribute because there is no
4622+
// known fix for this coming in DD2.0 modules. But the
4623+
// lab wants a control switch
46214624
constexpr size_t ENABLE = 1;
46224625

46234626
FAPI_DBG("Setting PHY_SEQ_REFRESH to %d on %s", ENABLE, mss::c_str(iv_mcs));

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