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future proof EC feature attributes, add missing P9N DD2 inits
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  redefine EC feature attributes, using inverse logic where required, to qualify
  inits specific to P9N DD1 where possible, to eliminate need for updates for
  future chips in plan

  attempt to remove usage of generic P9N_DD1_SPY_NAMES and P9N_DD2_SPY_NAMES
  attributes added to support initial P9NDD2 engineering data -- several spies
  were not being set as a result

  -----------------
  initfile updates:
  -----------------

  p9.cme.scan.initfile
    add HW391162, SCAN_SICR_TLBIE_QUIESCE feature attributes

  p9.core.common.scan.initfile
    remove fused core init, it was applying scan default for P9N DD1 and is
    not needed for P9N DD2+ given fuse controls

  p9.core.scan.initfile
    add CORE_P9NDD1 to qualify P9N DD1 specific register hierarchy and
    dial programming

    replace usage of P9N_DD1_SPY_NAMES, P9N_DD2_SPY_NAMES using CORE_P9NDD1
    and inverse, to pick up initial pass at P9C DD1 inits

  p9.cxa.scom.initfile
    add CXA_P9NDD1_SPY_NAMES to qualify P9N DD1 specific register hierarchy

  p9.ddrphy.scom.initfile
    add DDRPHY_P9NDD1_SPY_NAMES to qualify P9N DD1 specific register hierarchy

  p9.dpll.scan.initfile
    remove POSTDD1N_DPLL_SETTINGS feature attribute, use DD1_DPLL_SETTINGS
    attribute and inverse to drive inits

  p9.l2.scan.initfile
    invert definition of OPTIMAL_LARX_STCX_PERF, HW409069 feature attributes

  p9.l3.scan.initfile
  p9.l3.scom.initifle
    remove OPTIMAL_LCO_SCOM, HW396230_SCOM feature attributes
    use HW386657, HW396230 attributes to drive inits

  p9.mca.scom.initfile
    add MCA_P9NDD1_ASYNC to differentiate asynchronous boundary crossing
    programming and dial name differences between P9N DD1, P9N DD2

  p9.mmu.scan.initfile
  p9.mmu.scom.initfile
    invert definition of NMMU_DMT_DD2, NMMU_ISS734_DD2_1 feature attributes

  p9.ncu.scan.initfile
  p9.ncu.scom.initifle
    remove HW396230_SCOM, use HW396230 attribute to drive inits

  p9.npu.scom.initfile
    remove usage of P9N_DD1_SPY_NAMES, refactor CONFIG_ENABLE_PBUS specification
    to work for both P9NDD1, P9NDD2 ENGD

  p9.obus.scan.initfile
    remove EC qualification of OBUS FIR mask for simulation

  sample.ec.scan.initfile
    remove testcase requiring use of P9N_DD1_SPY_NAMES, properties of
    testcase are covered by other tests

  -----------------
  HWP updates:
  -----------------

  p9_xip_customize
    add customization of epsilon attributes for NMMU application

  p9_chiplet_scominit
    invert definition of P9_NDL_IOVALID feature attribute
    remove usage of P9N_DD1_SPY_NAMES

  p9_npu_scominit
    replace usage of P9N_DD1_SPY_NAMES with SETUP_BARS_NPU_DD1_ADDR

  p9_sbe_tracearray
    invert definition of CORE_TRACE_SCOMABLE feature attribute

  p9_sim_get_nia
    remove usage of P9N_DD1_SPY_NAMES, directly process CT/EC attributes
    (ok as this HWP is used for VBU sim only and not consumed by FW)

Change-Id: I63bfe8a4bfb8824b94e35a3688a6c69eecc1cf01
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40911
Reviewed-by: SHELTON LEUNG <sleung@us.ibm.com>
Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40916
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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@jjmcgill @dcrowell77
jjmcgill authored and dcrowell77 committed Jun 7, 2017
1 parent 72e68bb commit c1cafb2
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18 changes: 9 additions & 9 deletions src/import/chips/p9/initfiles/p9n.mca.scom.initfile
View file
Expand Up @@ -767,7 +767,7 @@ define def_perf_tune_case = (MCBIST.ATTR_MSS_FREQ==2400) && (SYS.ATTR_FREQ_PB_MH
# DD1

# "L" field
ispy MCP.PORT0.ECC64.SCOM.MBSECCQ_VAL_TO_DATA_DELAY [when=S && ATTR_CHIP_EC_FEATURE_P9N_DD1_SPY_NAMES] {
ispy MCP.PORT0.ECC64.SCOM.MBSECCQ_VAL_TO_DATA_DELAY [when=S && ATTR_CHIP_EC_FEATURE_MCA_P9NDD1_ASYNC] {
spyv, expr;
# OLD - keeping here because this Boston 2400/1600 fix is likely temporary (HW411339)
#3, (def_perf_tune_case==0); # untuned
Expand All @@ -778,7 +778,7 @@ ispy MCP.PORT0.ECC64.SCOM.MBSECCQ_VAL_TO_DATA_DELAY [when=S && ATTR_CHIP_EC_FEAT
}

# "D" field
ispy MCP.PORT0.ECC64.SCOM.MBSECCQ_NEST_VAL_TO_DATA_DELAY [when=S && ATTR_CHIP_EC_FEATURE_P9N_DD1_SPY_NAMES] {
ispy MCP.PORT0.ECC64.SCOM.MBSECCQ_NEST_VAL_TO_DATA_DELAY [when=S && ATTR_CHIP_EC_FEATURE_MCA_P9NDD1_ASYNC] {
spyv, expr;
# OLD - keeping here because this Boston 2400/1600 fix is likely temporary (HW411339)
#0, (def_perf_tune_case==0); # untuned
Expand All @@ -789,7 +789,7 @@ ispy MCP.PORT0.ECC64.SCOM.MBSECCQ_NEST_VAL_TO_DATA_DELAY [when=S && ATTR_CHIP_EC
}

# "dn" field
espy MCP.PORT0.ECC64.SCOM.MBSECCQ_DELAY_NONBYPASS [when=S && ATTR_CHIP_EC_FEATURE_P9N_DD1_SPY_NAMES] {
espy MCP.PORT0.ECC64.SCOM.MBSECCQ_DELAY_NONBYPASS [when=S && ATTR_CHIP_EC_FEATURE_MCA_P9NDD1_ASYNC] {
# OLD - keeping here because this Boston 2400/1600 fix is likely temporary (HW411339)
#spyv;
#OFF; # untuned and tuned same value
Expand All @@ -799,7 +799,7 @@ espy MCP.PORT0.ECC64.SCOM.MBSECCQ_DELAY_NONBYPASS [when=S && ATTR_CHIP_EC_FEATUR
}

# "h" field
espy MCP.PORT0.ECC64.SCOM.MBSECCQ_DELAY_VALID_1X [when=S && ATTR_CHIP_EC_FEATURE_P9N_DD1_SPY_NAMES] {
espy MCP.PORT0.ECC64.SCOM.MBSECCQ_DELAY_VALID_1X [when=S && ATTR_CHIP_EC_FEATURE_MCA_P9NDD1_ASYNC] {
spyv;
OFF; # untuned and tuned same value
}
Expand All @@ -809,15 +809,15 @@ espy MCP.PORT0.ECC64.SCOM.MBSECCQ_DELAY_VALID_1X [when=S && ATTR_CHIP_EC_FEATURE
# (note hierarchies for ECC scoms are slightly different in dd2)

# "L" field
ispy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_VAL_TO_DATA_DELAY [when=S && ATTR_CHIP_EC_FEATURE_P9N_DD2_SPY_NAMES] {
ispy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_VAL_TO_DATA_DELAY [when=S && !ATTR_CHIP_EC_FEATURE_MCA_P9NDD1_ASYNC] {
spyv, expr;
5, (PROC.ATTR_MC_SYNC_MODE==1); # sync
5, (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio < 1250); # async 2400m/2000n and below
6, (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 1250); # async 2666m/2000n
}

# "T" field (new for DD2)
espy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_BYPASS_TENURE_3 [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
espy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_BYPASS_TENURE_3 [when=S && !ATTR_CHIP_EC_FEATURE_MCA_P9NDD1_ASYNC] {
spyv, expr;
OFF, (PROC.ATTR_MC_SYNC_MODE==1); # sync
OFF, (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio < 963); # async 1866m/2000n
Expand All @@ -829,7 +829,7 @@ espy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_BYPASS_TENURE_3 [when=S && ATTR_CHIP_EC_FE
}

# "D" field
ispy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_NEST_VAL_TO_DATA_DELAY [when=S && ATTR_CHIP_EC_FEATURE_P9N_DD2_SPY_NAMES] {
ispy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_NEST_VAL_TO_DATA_DELAY [when=S && !ATTR_CHIP_EC_FEATURE_MCA_P9NDD1_ASYNC] {
spyv, expr;
0, (PROC.ATTR_MC_SYNC_MODE==1); # sync
2, (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio < 963); # async 1866m/2000n
Expand All @@ -841,13 +841,13 @@ ispy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_NEST_VAL_TO_DATA_DELAY [when=S && ATTR_CHI
}

# "dn" field
espy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_DELAY_NONBYPASS [when=S && ATTR_CHIP_EC_FEATURE_P9N_DD2_SPY_NAMES] {
espy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_DELAY_NONBYPASS [when=S && !ATTR_CHIP_EC_FEATURE_MCA_P9NDD1_ASYNC] {
spyv;
ON; # same across all frequency settings
}

# "h" field
espy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_DELAY_VALID_1X [when=S && ATTR_CHIP_EC_FEATURE_P9N_DD2_SPY_NAMES] {
espy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_DELAY_VALID_1X [when=S && !ATTR_CHIP_EC_FEATURE_MCA_P9NDD1_ASYNC] {
spyv, expr;
OFF, (PROC.ATTR_MC_SYNC_MODE==1); # sync
OFF, (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio < 963); # async 1866m/2000n
Expand Down
5 changes: 5 additions & 0 deletions src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.C
View file
Expand Up @@ -150,6 +150,11 @@ fapi2::ReturnCode writeMboxRegs (
MBOX_ATTR_WRITE (ATTR_DD1_SLOW_PCI_REF_CLOCK, FAPI_SYSTEM, i_image);
MBOX_ATTR_CLEAR (ATTR_PROC_EFF_FABRIC_GROUP_ID, i_procTarget, i_image);
MBOX_ATTR_CLEAR (ATTR_PROC_EFF_FABRIC_CHIP_ID, i_procTarget, i_image);
MBOX_ATTR_WRITE (ATTR_PROC_EPS_READ_CYCLES_T0, FAPI_SYSTEM, i_image);
MBOX_ATTR_WRITE (ATTR_PROC_EPS_READ_CYCLES_T1, FAPI_SYSTEM, i_image);
MBOX_ATTR_WRITE (ATTR_PROC_EPS_READ_CYCLES_T2, FAPI_SYSTEM, i_image);
MBOX_ATTR_WRITE (ATTR_PROC_EPS_WRITE_CYCLES_T1, FAPI_SYSTEM, i_image);
MBOX_ATTR_WRITE (ATTR_PROC_EPS_WRITE_CYCLES_T2, FAPI_SYSTEM, i_image);

fapi_try_exit:
FAPI_DBG("writeMboxRegs Exiting...");
Expand Down
19 changes: 17 additions & 2 deletions src/import/chips/p9/procedures/hwp/initfiles/p9_cxa_scom.C
View file
Expand Up @@ -108,14 +108,29 @@ fapi2::ReturnCode p9_cxa_scom(const fapi2::Target<fapi2::TARGET_TYPE_CAPP>& TGT0
FAPI_TRY(fapi2::putScom(TGT0, 0x2010819ull, l_scom_buffer));
}
{
FAPI_TRY(fapi2::getScom( TGT0, 0x201081bull, l_scom_buffer ));

if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) )
{
FAPI_TRY(fapi2::getScom( TGT0, 0x201081bull, l_scom_buffer ));
l_scom_buffer.insert<45, 3, 61, uint64_t>(literal_0b111 );
}

if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
{
l_scom_buffer.insert<45, 3, 61, uint64_t>(literal_0b111 );
}

if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) )
{
l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b0010 );
}

if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
{
l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b0010 );
FAPI_TRY(fapi2::putScom(TGT0, 0x201081bull, l_scom_buffer));
}

FAPI_TRY(fapi2::putScom(TGT0, 0x201081bull, l_scom_buffer));
}
{
FAPI_TRY(fapi2::getScom( TGT0, 0x201081cull, l_scom_buffer ));
Expand Down
28 changes: 14 additions & 14 deletions src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C
View file
Expand Up @@ -55,8 +55,8 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
fapi2::ATTR_NAME_Type l_chip_id;
FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_NAME, TGT0, l_chip_id));
FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_EC, TGT0, l_chip_ec));
fapi2::ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2_Type l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2;
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2, TGT0, l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2));
fapi2::ATTR_CHIP_EC_FEATURE_NMMU_NDD1_Type l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1;
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_NMMU_NDD1, TGT0, l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1));
fapi2::ATTR_PROC_FABRIC_PUMP_MODE_Type l_TGT1_ATTR_PROC_FABRIC_PUMP_MODE;
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_PUMP_MODE, TGT1, l_TGT1_ATTR_PROC_FABRIC_PUMP_MODE));
fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T1_Type l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T1;
Expand All @@ -67,11 +67,11 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
{
FAPI_TRY(fapi2::getScom( TGT0, 0x5012c03ull, l_scom_buffer ));

if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 == literal_0))
if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 != literal_0))
{
l_scom_buffer.insert<0, 22, 0, uint64_t>(literal_0x04047C0000000000 );
}
else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 != literal_0))
else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 == literal_0))
{
l_scom_buffer.insert<0, 22, 0, uint64_t>(literal_0x04247C0000000000 );
}
Expand All @@ -87,11 +87,11 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
{
FAPI_TRY(fapi2::getScom( TGT0, 0x5012c07ull, l_scom_buffer ));

if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 == literal_0))
if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 != literal_0))
{
l_scom_buffer.insert<0, 22, 0, uint64_t>(literal_0x409B000000000000 );
}
else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 != literal_0))
else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 == literal_0))
{
l_scom_buffer.insert<0, 22, 0, uint64_t>(literal_0x40FB000000000000 );
}
Expand Down Expand Up @@ -134,11 +134,11 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
{
FAPI_TRY(fapi2::getScom( TGT0, 0x5012c43ull, l_scom_buffer ));

if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 == literal_0))
if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 != literal_0))
{
l_scom_buffer.insert<0, 48, 16, uint64_t>(literal_0x0000FAF800FF );
}
else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 != literal_0))
else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 == literal_0))
{
l_scom_buffer.insert<0, 48, 16, uint64_t>(literal_0x0000FAFC00FB );
}
Expand All @@ -154,11 +154,11 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
{
FAPI_TRY(fapi2::getScom( TGT0, 0x5012c47ull, l_scom_buffer ));

if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 == literal_0))
if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 != literal_0))
{
l_scom_buffer.insert<0, 48, 16, uint64_t>(literal_0x910000040F00 );
}
else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 != literal_0))
else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 == literal_0))
{
l_scom_buffer.insert<0, 48, 16, uint64_t>(literal_0x9D1100000F04 );
}
Expand All @@ -171,11 +171,11 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
l_scom_buffer.insert<30, 1, 59, uint64_t>(literal_0b11111 );
l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b11111 );

if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 == literal_0))
if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 != literal_0))
{
l_scom_buffer.insert<0, 12, 52, uint64_t>(literal_0x00E );
}
else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 != literal_0))
else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 == literal_0))
{
l_scom_buffer.insert<0, 12, 52, uint64_t>(literal_0x000 );
}
Expand Down Expand Up @@ -227,12 +227,12 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
l_scom_buffer.insert<44, 8, 56, uint64_t>(l_NMMU_MM_MPSS_MODE_MPSS_ENA_PREF_PGSZ_ENA_G_64KB_H_64KB );
}

if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 == literal_0))
if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 != literal_0))
{
constexpr auto l_NMMU_MM_CFG_NMMU_CTL_TLB_HASH_PID_DIS_ON = 0x1;
l_scom_buffer.insert<21, 1, 63, uint64_t>(l_NMMU_MM_CFG_NMMU_CTL_TLB_HASH_PID_DIS_ON );
}
else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 != literal_0))
else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 == literal_0))
{
constexpr auto l_NMMU_MM_CFG_NMMU_CTL_TLB_HASH_PID_DIS_OFF = 0x0;
l_scom_buffer.insert<21, 1, 63, uint64_t>(l_NMMU_MM_CFG_NMMU_CTL_TLB_HASH_PID_DIS_OFF );
Expand Down
38 changes: 8 additions & 30 deletions src/import/chips/p9/procedures/hwp/initfiles/p9_npu_scom.C
View file
Expand Up @@ -91,20 +91,9 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&

l_scom_buffer.insert<4, 1, 63, uint64_t>(literal_0b0 );

if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) )
{
if ((l_def_NVLINK_ACTIVE == literal_1))
{
l_scom_buffer.insert<38, 1, 63, uint64_t>(literal_0x1 );
}
}

if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
if ((l_def_NVLINK_ACTIVE == literal_1))
{
if ((l_def_NVLINK_ACTIVE == literal_1))
{
l_scom_buffer.insert<38, 1, 63, uint64_t>(literal_0x1 );
}
l_scom_buffer.insert<38, 1, 63, uint64_t>(literal_0x1 );
}

if ((l_def_NVLINK_ACTIVE == literal_1))
Expand Down Expand Up @@ -424,20 +413,9 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&

l_scom_buffer.insert<4, 1, 63, uint64_t>(literal_0b0 );

if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) )
{
if ((l_def_NVLINK_ACTIVE == literal_1))
{
l_scom_buffer.insert<38, 1, 63, uint64_t>(literal_0x1 );
}
}

if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
if ((l_def_NVLINK_ACTIVE == literal_1))
{
if ((l_def_NVLINK_ACTIVE == literal_1))
{
l_scom_buffer.insert<38, 1, 63, uint64_t>(literal_0x1 );
}
l_scom_buffer.insert<38, 1, 63, uint64_t>(literal_0x1 );
}

if ((l_def_NVLINK_ACTIVE == literal_1))
Expand Down Expand Up @@ -1147,15 +1125,15 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&

l_scom_buffer.insert<4, 1, 63, uint64_t>(literal_0b0 );

if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) )
if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
{
if ((l_def_NVLINK_ACTIVE == literal_1))
{
l_scom_buffer.insert<38, 1, 63, uint64_t>(literal_0x1 );
}
}

if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) )
{
if ((l_def_NVLINK_ACTIVE == literal_1))
{
Expand Down Expand Up @@ -1564,15 +1542,15 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&

l_scom_buffer.insert<4, 1, 63, uint64_t>(literal_0b0 );

if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) )
if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
{
if ((l_def_NVLINK_ACTIVE == literal_1))
{
l_scom_buffer.insert<38, 1, 63, uint64_t>(literal_0x1 );
}
}

if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) )
{
if ((l_def_NVLINK_ACTIVE == literal_1))
{
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