PLL configuration updates -- permit e2e bypass execution

p9_sbe_attr_setup
p9_setup_sbe_config
  transmit PLL bypass controls through MBOX Scratch 4 bits 16:20
  transmit PLL mux controls through MBOX Scratch 5 bits 12:31

p9_common_poweronoff
  increase polling delays to account for refclock speed

p9_hcd_cache_dpll_setup
  permit DPLL execution in bypass, based on ATTR_DPLL_BYPASS

p9_sbe_npll_setup
  permit NEST PLL execution in bypass, based on ATTR_NEST_MEM_X_O_PCI_BYPASS

p9_mem_pll_setup
  permit MEM PLL execution in bypass, based on ATTR_NEST_MEM_X_O_PCI_BYPASS

p9_sbe_chiplet_pll_setup
  permit X/O/PCI PLL execution in bypass, based on ATTR_NEST_MEM_X_O_PCI_BYPASS

p9_sbe_tp_switch_gears
  skip adjustment of i2c bit divisor, based on ATTR_NEST_MEM_X_O_PCI_BYPASS

p9_sbe_attributes.xml
hb_temp_defaults.xml
  add defaults to enable platform CI

Change-Id: Ifd8e2472c020a8f5566272810495e80ffe75a812
Original-Change-Id: Icba6aee79d90b0280ba4818afd92c344c52f52ef
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28611
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36099
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.C

@@ -74,7 +74,7 @@ const uint64_t PPM_PFSNS[2] =   { C_PPM_PFSNS,
                                 };
 
 enum { FSM_IDLE_POLLING_HW_NS_DELAY = 10000,
-       FSM_IDLE_POLLING_SIM_CYCLE_DELAY = 80000,
+       FSM_IDLE_POLLING_SIM_CYCLE_DELAY = 320000,
        PFET_STATE_LENGTH = 2,
        VXX_PG_SEL_LEN = 4
      };