L3 support for ddr_phy_reset, termination_control

Change-Id: I06a2911a7df14c4bbdcef86df4bdf95686c7eabd
Original-Change-Id: I70ad1f23dabc4b9f169821b30a903a200f52fbc4
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42437
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43446
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>

Author: JacobHarvey

src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C

@@ -27,10 +27,10 @@
 /// @file mrs00.C
 /// @brief Run and manage the DDR4 MRS00 loading
 ///
-// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com>
+// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
 // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
 // *HWP Team: Memory
-// *HWP Level: 3
+// *HWP Level: 1
 // *HWP Consumed by: FSP:HB
 
 #include <fapi2.H>

src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C

@@ -27,7 +27,7 @@
 /// @file mrs01.C
 /// @brief Run and manage the DDR4 MRS01 loading
 ///
-// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com>
+// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
 // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
 // *HWP Team: Memory
 // *HWP Level: 1

src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C

@@ -27,7 +27,7 @@
 /// @file mrs02.C
 /// @brief Run and manage the DDR4 MRS02 loading
 ///
-// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com>
+// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
 // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
 // *HWP Team: Memory
 // *HWP Level: 1

src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C

@@ -27,7 +27,7 @@
 /// @file mrs03.C
 /// @brief Run and manage the DDR4 DDR4 loading
 ///
-// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com>
+// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
 // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
 // *HWP Team: Memory
 // *HWP Level: 1

src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C

@@ -27,7 +27,7 @@
 /// @file mrs05.C
 /// @brief Run and manage the DDR4 MRS05 loading
 ///
-// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com>
+// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
 // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
 // *HWP Team: Memory
 // *HWP Level: 1

src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs06.C

@@ -27,7 +27,7 @@
 /// @file mrs06.C
 /// @brief Run and manage the DDR4 MRS06 loading
 ///
-// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com>
+// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
 // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
 // *HWP Team: Memory
 // *HWP Level: 1