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rdtag_dly formulas based on PHY delays
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Change-Id: I28b51d549e03e566377807595d20e3e31a645a4c
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34671
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Reviewed-by: SARAVANAN SETHURAMAN <saravanans@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34680
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Shelton Leung authored and dcrowell77 committed Jan 24, 2017
1 parent bfe125e commit f7d4f6b
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Showing 2 changed files with 52 additions and 121 deletions.
39 changes: 17 additions & 22 deletions src/import/chips/p9/initfiles/p9.mca.scom.initfile
View file
Expand Up @@ -273,31 +273,26 @@ ispy MCP.PORT0.SRQ.MBA_TMR1Q_CFG_ACT_TO_DIFF_RANK_DLY [when=S] {
# DSM0 SCOM REGISTER #
# DRAM TIMING PARAMETERS #

# TODO RTC: 166455 NEED TO GET THE FORMULA FOR THIS - CURRENTLY GUESSES!
ispy MCP.PORT0.SRQ.MBA_DSM0Q_CFG_RDTAG_DLY [when=S] { # ATTR_EFF_DIMM_TYPE: CDIMM = 0 RDIMM = 1 UDIMM = 2 LRDIMM = 3
spyv, expr;

# rdtag_dly + 3 + rdptrdly > PHY DELAY + CL
# rdtag_dly > PHY DELAY + CL - 3 - rdptrdly
# PHY DELAY = 12 for 1866 and 2133, 13 for 2400 and 2666, +1 for LRDIMM
# rdptrdly = 1

17, def_IS_SIM;
22, ((def_MEM_TYPE_1866_13==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1)) && def_IS_HW;
22, ((def_MEM_TYPE_1866_14==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1)) && def_IS_HW;
26, ((def_MEM_TYPE_2133_15==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1)) && def_IS_HW;
26, ((def_MEM_TYPE_2133_16==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1)) && def_IS_HW;
26, ((def_MEM_TYPE_2400_16==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1)) && def_IS_HW;
26, ((def_MEM_TYPE_2400_17==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1)) && def_IS_HW;
26, ((def_MEM_TYPE_2400_18==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1)) && def_IS_HW;
26, ((def_MEM_TYPE_2666_18==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1)) && def_IS_HW;
28, ((def_MEM_TYPE_2666_19==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1)) && def_IS_HW;
28, ((def_MEM_TYPE_2666_20==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1)) && def_IS_HW;

24, ((def_MEM_TYPE_1866_13==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3)) && def_IS_HW;
24, ((def_MEM_TYPE_1866_14==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3)) && def_IS_HW;
28, ((def_MEM_TYPE_2133_15==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3)) && def_IS_HW;
28, ((def_MEM_TYPE_2133_16==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3)) && def_IS_HW;
28, ((def_MEM_TYPE_2400_16==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3)) && def_IS_HW;
28, ((def_MEM_TYPE_2400_17==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3)) && def_IS_HW;
28, ((def_MEM_TYPE_2400_18==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3)) && def_IS_HW;
26, ((def_MEM_TYPE_2666_18==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3)) && def_IS_HW;
30, ((def_MEM_TYPE_2666_19==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3)) && def_IS_HW;
30, ((def_MEM_TYPE_2666_20==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3)) && def_IS_HW;

8 + MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX], (def_MSS_FREQ_EQ_1866==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1) && def_IS_HW; # RDIMM
8 + MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX], (def_MSS_FREQ_EQ_2133==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1) && def_IS_HW; # RDIMM
9 + MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX], (def_MSS_FREQ_EQ_2400==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1) && def_IS_HW; # RDIMM
9 + MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX], (def_MSS_FREQ_EQ_2666==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1) && def_IS_HW; # RDIMM

9 + MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX], (def_MSS_FREQ_EQ_1866==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3) && def_IS_HW; # LRDIMM
9 + MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX], (def_MSS_FREQ_EQ_2133==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3) && def_IS_HW; # LRDIMM
10 + MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX], (def_MSS_FREQ_EQ_2400==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3) && def_IS_HW; # LRDIMM
10 + MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX], (def_MSS_FREQ_EQ_2666==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3) && def_IS_HW; # LRDIMM

}

ispy MCP.PORT0.SRQ.MBA_DSM0Q_CFG_WRDATA_DLY [when=S] {
Expand Down
134 changes: 35 additions & 99 deletions src/import/chips/p9/procedures/hwp/initfiles/p9_mca_scom.C
View file
Expand Up @@ -38,29 +38,25 @@ constexpr uint64_t literal_1 = 1;
constexpr uint64_t literal_17 = 17;
constexpr uint64_t literal_0 = 0;
constexpr uint64_t literal_2 = 2;
constexpr uint64_t literal_13 = 13;
constexpr uint64_t literal_1867 = 1867;
constexpr uint64_t literal_22 = 22;
constexpr uint64_t literal_14 = 14;
constexpr uint64_t literal_15 = 15;
constexpr uint64_t literal_8 = 8;
constexpr uint64_t literal_2134 = 2134;
constexpr uint64_t literal_26 = 26;
constexpr uint64_t literal_16 = 16;
constexpr uint64_t literal_2401 = 2401;
constexpr uint64_t literal_18 = 18;
constexpr uint64_t literal_9 = 9;
constexpr uint64_t literal_2666 = 2666;
constexpr uint64_t literal_19 = 19;
constexpr uint64_t literal_28 = 28;
constexpr uint64_t literal_20 = 20;
constexpr uint64_t literal_3 = 3;
constexpr uint64_t literal_10 = 10;
constexpr uint64_t literal_24 = 24;
constexpr uint64_t literal_30 = 30;
constexpr uint64_t literal_8 = 8;
constexpr uint64_t literal_9 = 9;
constexpr uint64_t literal_13 = 13;
constexpr uint64_t literal_14 = 14;
constexpr uint64_t literal_5 = 5;
constexpr uint64_t literal_15 = 15;
constexpr uint64_t literal_6 = 6;
constexpr uint64_t literal_16 = 16;
constexpr uint64_t literal_7 = 7;
constexpr uint64_t literal_10 = 10;
constexpr uint64_t literal_18 = 18;
constexpr uint64_t literal_19 = 19;
constexpr uint64_t literal_20 = 20;
constexpr uint64_t literal_11 = 11;
constexpr uint64_t literal_12 = 12;
constexpr uint64_t literal_267 = 267;
Expand Down Expand Up @@ -99,28 +95,28 @@ fapi2::ReturnCode p9_mca_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& TGT0,
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, TGT0, l_TGT0_ATTR_CHIP_UNIT_POS));
uint64_t l_def_POSITION = l_TGT0_ATTR_CHIP_UNIT_POS;
uint64_t l_def_PORT_INDEX = (l_def_POSITION % literal_2);
fapi2::ATTR_EFF_DRAM_CL_Type l_TGT2_ATTR_EFF_DRAM_CL;
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_EFF_DRAM_CL, TGT2, l_TGT2_ATTR_EFF_DRAM_CL));
fapi2::ATTR_MSS_FREQ_Type l_TGT1_ATTR_MSS_FREQ;
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_FREQ, TGT1, l_TGT1_ATTR_MSS_FREQ));
uint64_t l_def_MSS_FREQ_EQ_1866 = (l_TGT1_ATTR_MSS_FREQ < literal_1867);
fapi2::ATTR_EFF_DRAM_CL_Type l_TGT2_ATTR_EFF_DRAM_CL;
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_EFF_DRAM_CL, TGT2, l_TGT2_ATTR_EFF_DRAM_CL));
uint64_t l_def_MSS_FREQ_EQ_2133 = ((l_TGT1_ATTR_MSS_FREQ >= literal_1867) && (l_TGT1_ATTR_MSS_FREQ < literal_2134));
uint64_t l_def_MSS_FREQ_EQ_2400 = ((l_TGT1_ATTR_MSS_FREQ >= literal_2134) && (l_TGT1_ATTR_MSS_FREQ < literal_2401));
uint64_t l_def_MSS_FREQ_EQ_2666 = (l_TGT1_ATTR_MSS_FREQ >= literal_2666);
fapi2::ATTR_MSS_VPD_MR_DPHY_WLO_Type l_TGT2_ATTR_MSS_VPD_MR_DPHY_WLO;
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_DPHY_WLO, TGT2, l_TGT2_ATTR_MSS_VPD_MR_DPHY_WLO));
fapi2::ATTR_EFF_DRAM_CWL_Type l_TGT2_ATTR_EFF_DRAM_CWL;
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_EFF_DRAM_CWL, TGT2, l_TGT2_ATTR_EFF_DRAM_CWL));
uint64_t l_def_MEM_TYPE_1866_13 = (l_def_MSS_FREQ_EQ_1866 && (l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX] == literal_13));
uint64_t l_def_MEM_TYPE_1866_14 = (l_def_MSS_FREQ_EQ_1866 && (l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX] == literal_14));
uint64_t l_def_MSS_FREQ_EQ_2133 = ((l_TGT1_ATTR_MSS_FREQ >= literal_1867) && (l_TGT1_ATTR_MSS_FREQ < literal_2134));
uint64_t l_def_MEM_TYPE_2133_15 = (l_def_MSS_FREQ_EQ_2133 && (l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX] == literal_15));
uint64_t l_def_MEM_TYPE_2133_16 = (l_def_MSS_FREQ_EQ_2133 && (l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX] == literal_16));
uint64_t l_def_MSS_FREQ_EQ_2400 = ((l_TGT1_ATTR_MSS_FREQ >= literal_2134) && (l_TGT1_ATTR_MSS_FREQ < literal_2401));
uint64_t l_def_MEM_TYPE_2400_16 = (l_def_MSS_FREQ_EQ_2400 && (l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX] == literal_16));
uint64_t l_def_MEM_TYPE_2400_17 = (l_def_MSS_FREQ_EQ_2400 && (l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX] == literal_17));
uint64_t l_def_MEM_TYPE_2400_18 = (l_def_MSS_FREQ_EQ_2400 && (l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX] == literal_18));
uint64_t l_def_MSS_FREQ_EQ_2666 = (l_TGT1_ATTR_MSS_FREQ >= literal_2666);
uint64_t l_def_MEM_TYPE_2666_18 = (l_def_MSS_FREQ_EQ_2666 && (l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX] == literal_18));
uint64_t l_def_MEM_TYPE_2666_19 = (l_def_MSS_FREQ_EQ_2666 && (l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX] == literal_19));
uint64_t l_def_MEM_TYPE_2666_20 = (l_def_MSS_FREQ_EQ_2666 && (l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX] == literal_20));
fapi2::ATTR_MSS_VPD_MR_DPHY_WLO_Type l_TGT2_ATTR_MSS_VPD_MR_DPHY_WLO;
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_DPHY_WLO, TGT2, l_TGT2_ATTR_MSS_VPD_MR_DPHY_WLO));
fapi2::ATTR_EFF_DRAM_CWL_Type l_TGT2_ATTR_EFF_DRAM_CWL;
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_EFF_DRAM_CWL, TGT2, l_TGT2_ATTR_EFF_DRAM_CWL));
uint64_t l_def_RANK_SWITCH_TCK = (literal_4 + ((l_TGT1_ATTR_MSS_FREQ - literal_1866) / literal_267));
fapi2::ATTR_EFF_DRAM_TCCD_L_Type l_TGT2_ATTR_EFF_DRAM_TCCD_L;
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_EFF_DRAM_TCCD_L, TGT2, l_TGT2_ATTR_EFF_DRAM_TCCD_L));
Expand Down Expand Up @@ -197,105 +193,45 @@ fapi2::ReturnCode p9_mca_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& TGT0,
{
l_scom_buffer.insert<36, 6, 58, uint64_t>(literal_17 );
}
else if ((((l_def_MEM_TYPE_1866_13 == literal_1)
&& (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_1)) && l_def_IS_HW))
{
l_scom_buffer.insert<36, 6, 58, uint64_t>(literal_22 );
}
else if ((((l_def_MEM_TYPE_1866_14 == literal_1)
&& (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_1)) && l_def_IS_HW))
{
l_scom_buffer.insert<36, 6, 58, uint64_t>(literal_22 );
}
else if ((((l_def_MEM_TYPE_2133_15 == literal_1)
&& (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_1)) && l_def_IS_HW))
{
l_scom_buffer.insert<36, 6, 58, uint64_t>(literal_26 );
}
else if ((((l_def_MEM_TYPE_2133_16 == literal_1)
&& (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_1)) && l_def_IS_HW))
{
l_scom_buffer.insert<36, 6, 58, uint64_t>(literal_26 );
}
else if ((((l_def_MEM_TYPE_2400_16 == literal_1)
&& (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_1)) && l_def_IS_HW))
{
l_scom_buffer.insert<36, 6, 58, uint64_t>(literal_26 );
}
else if ((((l_def_MEM_TYPE_2400_17 == literal_1)
&& (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_1)) && l_def_IS_HW))
{
l_scom_buffer.insert<36, 6, 58, uint64_t>(literal_26 );
}
else if ((((l_def_MEM_TYPE_2400_18 == literal_1)
else if ((((l_def_MSS_FREQ_EQ_1866 == literal_1)
&& (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_1)) && l_def_IS_HW))
{
l_scom_buffer.insert<36, 6, 58, uint64_t>(literal_26 );
l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_8 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) );
}
else if ((((l_def_MEM_TYPE_2666_18 == literal_1)
else if ((((l_def_MSS_FREQ_EQ_2133 == literal_1)
&& (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_1)) && l_def_IS_HW))
{
l_scom_buffer.insert<36, 6, 58, uint64_t>(literal_26 );
l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_8 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) );
}
else if ((((l_def_MEM_TYPE_2666_19 == literal_1)
else if ((((l_def_MSS_FREQ_EQ_2400 == literal_1)
&& (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_1)) && l_def_IS_HW))
{
l_scom_buffer.insert<36, 6, 58, uint64_t>(literal_28 );
l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_9 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) );
}
else if ((((l_def_MEM_TYPE_2666_20 == literal_1)
else if ((((l_def_MSS_FREQ_EQ_2666 == literal_1)
&& (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_1)) && l_def_IS_HW))
{
l_scom_buffer.insert<36, 6, 58, uint64_t>(literal_28 );
}
else if ((((l_def_MEM_TYPE_1866_13 == literal_1)
&& (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_3)) && l_def_IS_HW))
{
l_scom_buffer.insert<36, 6, 58, uint64_t>(literal_24 );
}
else if ((((l_def_MEM_TYPE_1866_14 == literal_1)
&& (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_3)) && l_def_IS_HW))
{
l_scom_buffer.insert<36, 6, 58, uint64_t>(literal_24 );
}
else if ((((l_def_MEM_TYPE_2133_15 == literal_1)
&& (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_3)) && l_def_IS_HW))
{
l_scom_buffer.insert<36, 6, 58, uint64_t>(literal_28 );
}
else if ((((l_def_MEM_TYPE_2133_16 == literal_1)
&& (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_3)) && l_def_IS_HW))
{
l_scom_buffer.insert<36, 6, 58, uint64_t>(literal_28 );
}
else if ((((l_def_MEM_TYPE_2400_16 == literal_1)
&& (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_3)) && l_def_IS_HW))
{
l_scom_buffer.insert<36, 6, 58, uint64_t>(literal_28 );
}
else if ((((l_def_MEM_TYPE_2400_17 == literal_1)
&& (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_3)) && l_def_IS_HW))
{
l_scom_buffer.insert<36, 6, 58, uint64_t>(literal_28 );
l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_9 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) );
}
else if ((((l_def_MEM_TYPE_2400_18 == literal_1)
else if ((((l_def_MSS_FREQ_EQ_1866 == literal_1)
&& (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_3)) && l_def_IS_HW))
{
l_scom_buffer.insert<36, 6, 58, uint64_t>(literal_28 );
l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_9 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) );
}
else if ((((l_def_MEM_TYPE_2666_18 == literal_1)
else if ((((l_def_MSS_FREQ_EQ_2133 == literal_1)
&& (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_3)) && l_def_IS_HW))
{
l_scom_buffer.insert<36, 6, 58, uint64_t>(literal_26 );
l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_9 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) );
}
else if ((((l_def_MEM_TYPE_2666_19 == literal_1)
else if ((((l_def_MSS_FREQ_EQ_2400 == literal_1)
&& (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_3)) && l_def_IS_HW))
{
l_scom_buffer.insert<36, 6, 58, uint64_t>(literal_30 );
l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_10 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) );
}
else if ((((l_def_MEM_TYPE_2666_20 == literal_1)
else if ((((l_def_MSS_FREQ_EQ_2666 == literal_1)
&& (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_3)) && l_def_IS_HW))
{
l_scom_buffer.insert<36, 6, 58, uint64_t>(literal_30 );
l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_10 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) );
}

if ((l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_1))
Expand Down

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