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main.c
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main.c
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/* IBM_PROLOG_BEGIN_TAG */
/* This is an automatically generated prolog. */
/* */
/* $Source: src/occ_405/main.c $ */
/* */
/* OpenPOWER OnChipController Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2011,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
/* Licensed under the Apache License, Version 2.0 (the "License"); */
/* you may not use this file except in compliance with the License. */
/* You may obtain a copy of the License at */
/* */
/* http://www.apache.org/licenses/LICENSE-2.0 */
/* */
/* Unless required by applicable law or agreed to in writing, software */
/* distributed under the License is distributed on an "AS IS" BASIS, */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
/* implied. See the License for the specific language governing */
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
#include "ssx.h"
#include "ssx_io.h"
#include "ipc_api.h" //ipc base interfaces
#include "occhw_async.h" //async (GPE, OCB, etc) interfaces
#include "simics_stdio.h"
//#include "heartbeat.h"
#include <thread.h>
#include <sensor.h>
#include <threadSch.h>
#include <errl.h>
#include <apss.h>
#include <trac.h>
#include <occ_service_codes.h>
#include <occ_sys_config.h>
#include <timer.h>
#include <dcom.h>
#include <rtls.h>
#include <proc_data.h>
#include <centaur_data.h>
#include <dpss.h>
#include <state.h>
#include <amec_sys.h>
#include <cmdh_fsp.h>
#include <proc_pstate.h>
//#include <vrm.h>
#include <chom.h>
#include <homer.h>
#include <amec_health.h>
#include <amec_freq.h>
#include "scom.h"
//#include <fir_data_collect.h>
#include <pss_service_codes.h>
#include <dimm.h>
#include "occhw_shared_data.h"
#include <pgpe_shared.h>
#include <gpe_register_addresses.h>
#include <p9_pstates_occ.h>
#include <wof.h>
extern uint32_t __ssx_boot; // Function address is 32 bits
extern uint32_t G_occ_phantom_critical_count;
extern uint32_t G_occ_phantom_noncritical_count;
extern uint8_t G_occ_interrupt_type;
extern uint8_t G_occ_role;
extern GpeRequest G_meas_start_request;
extern GpeRequest G_meas_cont_request;
extern GpeRequest G_meas_complete_request;
extern apss_start_args_t G_gpe_start_pwr_meas_read_args;
extern apss_continue_args_t G_gpe_continue_pwr_meas_read_args;
extern apss_complete_args_t G_gpe_complete_pwr_meas_read_args;
extern uint32_t G_pgpe_beacon_address;
extern uint32_t G_proc_fmin_khz;
extern uint32_t G_proc_fmax_khz;
extern wof_header_data_t G_wof_header;
extern uint32_t G_khz_per_pstate;
extern uint8_t G_proc_pmin;
extern uint8_t G_proc_pmax;
IMAGE_HEADER (G_mainAppImageHdr,__ssx_boot,MAIN_APP_ID,ID_NUM_INVALID);
// PGPE Image Header Parameters
uint32_t G_pgpe_shared_sram_address;
uint32_t G_pgpe_shared_sram_sz;
uint32_t G_pgpe_pstate_table_address;
uint32_t G_pgpe_pstate_table_sz;
ppmr_header_t G_ppmr_header; // PPMR Header layout format
OCCPstateParmBlock G_oppb; // OCC Pstate Parameters Block Structure
extern uint16_t G_proc_fmax_mhz; // max(turbo,uturbo) frequencies
// Set main thread timer for one second
#define MAIN_THRD_TIMER_SLICE ((SsxInterval) SSX_SECONDS(1))
// Define location for data shared with GPEs
gpe_shared_data_t G_shared_gpe_data __attribute__ ((section (".gpe_shared")));
// SIMICS printf/printk
SimicsStdio G_simics_stdout;
SimicsStdio G_simics_stderr;
// Critical /non Critical Stacks
uint8_t G_noncritical_stack[NONCRITICAL_STACK_SIZE];
uint8_t G_critical_stack[CRITICAL_STACK_SIZE];
//NOTE: Three semaphores are used so that if in future it is decided
// to move health monitor and FFDC into it's own threads, then
// it can be done easily without more changes.
// Semaphores for the health monitor functions
SsxSemaphore G_hmonSem;
// Semaphores for the FFDC functions
SsxSemaphore G_ffdcSem;
// Timer for posting health monitor and FFDC semaphore
SsxTimer G_mainThrdTimer;
// Variable holding main thread loop count
uint32_t G_mainThreadLoopCounter = 0x0;
// Global flag indicating FIR collection is required
bool G_fir_collection_required = FALSE;
// Global flag indicating we are running on Simics
bool G_simics_environment = FALSE;
// Nest frequency in MHz
uint32_t G_nest_frequency_mhz;
extern uint8_t g_trac_inf_buffer[];
extern uint8_t g_trac_imp_buffer[];
extern uint8_t g_trac_err_buffer[];
void pmc_hw_error_isr(void *private, SsxIrqId irq, int priority);
void create_tlb_entry(uint32_t address, uint32_t size);
void read_oppb_params(const OCCPstateParmBlock* occ_ppb);
//Macro creates a 'bridge' handler that converts the initial fast-mode to full
//mode interrupt handler
SSX_IRQ_FAST2FULL(pmc_hw_error_fast, pmc_hw_error_isr);
/*
* Function Specification
*
* Name: check_runtime_environment
*
* Description: Determines whether we are running in Simics or on real HW.
*
* End Function Specification
*/
void check_runtime_environment(void)
{
uint64_t flags;
flags = in64(OCB_OCCFLG);
// NOTE: The lower 32 bits of this register have no latches on
// physical hardware and will return 0s, so we can use
// a backdoor hack in Simics to set bit 63, telling the
// firmware what environment it's running in.
G_simics_environment = ( 0 != (flags & 0x0000000000000001) ) ? TRUE : FALSE;
if (G_simics_environment)
{
// slow down RTL for Simics
G_mics_per_tick = SIMICS_MICS_PER_TICK;
G_dcom_tx_apss_wait_time = SIMICS_MICS_PER_TICK * 6 / 10;
// Same comment as above about lower 32-bits. Bit 62 can be toggled
// on or off (in Simics) to indicate for which APSS specification the
// model is configured.
G_shared_gpe_data.spipss_spec_p9 =
(0 != (flags & 0x0000000000000002) ) ? FALSE : TRUE;
}
else
{
G_shared_gpe_data.spipss_spec_p9 = 0;
}
}
/*
* Function Specification
*
* Name: pmc_hw_error_isr
*
* Description: Handles IRQ for PMCLFIR bit being set. Only bits that are
* unmasked (0x1010843) and have action0 (0x1010846) set to 1
* and action1 (0x1010847) set to 0 will cause this interupt
* (OISR0[9]) to fire. This runs in a non critical context
* (tracing allowed).
*
*
* End Function Specification
*/
void pmc_hw_error_isr(void *private, SsxIrqId irq, int priority)
{
// TODO: RTC 134619; enable Interrupt handlers for HW errors
// -- uncomment currently unused vars upon implementation
//errlHndl_t l_err;
//pmc_ffdc_data_t l_pmc_ffdc;
SsxMachineContext ctx;
// Mask this interrupt
ssx_irq_disable(irq);
// disable critical interrupts
ssx_critical_section_enter( SSX_NONCRITICAL, &ctx );
// clear this irq status in OISR0
ssx_irq_status_clear(irq);
// dump a bunch of FFDC registers
//fill_pmc_ffdc_buffer(&l_pmc_ffdc);
MAIN_TRAC_ERR("PMC Failure detected through OISR0[9]!!!");
/* @
* @moduleid PMC_HW_ERROR_ISR
* @reasonCode PMC_FAILURE
* @severity ERRL_SEV_PREDICTIVE
* @userdata1 0
* @userdata2 0
* @userdata4 OCC_NO_EXTENDED_RC
* @devdesc Failure detected in processor
* power management controller (PMC)
*/
/* TEMP NO MORE PMC - RTC 161456
l_err = createErrl( PMC_HW_ERROR_ISR, // i_modId,
PMC_FAILURE, // i_reasonCode,
OCC_NO_EXTENDED_RC,
ERRL_SEV_PREDICTIVE,
NULL, // tracDesc_t i_trace,
DEFAULT_TRACE_SIZE, // i_traceSz,
0, // i_userData1,
0); // i_userData2
//Add our register dump to the error log
addUsrDtlsToErrl(l_err,
(uint8_t*) &l_pmc_ffdc,
sizeof(l_pmc_ffdc),
ERRL_USR_DTL_STRUCT_VERSION_1,
ERRL_USR_DTL_BINARY_DATA);
//Add firmware callout
addCalloutToErrl(l_err,
ERRL_CALLOUT_TYPE_COMPONENT_ID,
ERRL_COMPONENT_ID_FIRMWARE,
ERRL_CALLOUT_PRIORITY_HIGH);
//Add processor callout
addCalloutToErrl(l_err,
ERRL_CALLOUT_TYPE_HUID,
G_sysConfigData.proc_huid,
ERRL_CALLOUT_PRIORITY_MED);
//Add planar callout
addCalloutToErrl(l_err,
ERRL_CALLOUT_TYPE_HUID,
G_sysConfigData.backplane_huid,
ERRL_CALLOUT_PRIORITY_LOW);
REQUEST_RESET(l_err);
*/
// Unmask this interrupt
ssx_irq_enable(irq);
// re-enable non-critical interrupts
ssx_critical_section_exit( &ctx );
}
/*
* Function Specification
*
* Name: occ_hw_error_isr
*
* Description: Handles IRQ for OCCLFIR bit being set. Only bits
* that are unmasked (0x1010803) and have action0 (0x1010806)
* set to 1 and action1 (0x1010807) set to 0 will cause this
* interupt (OISR0[2]) to fire. This runs in a critical
* context (no tracing!).
*
* End Function Specification
*/
//NOTE: use "putscom pu 6B111 0 3 101 -ib -p1" to inject the error.
#define OCC_LFIR_SPARE_BIT50 0x0000000000002000ull //gm031
void occ_hw_error_isr(void *private, SsxIrqId irq, int priority)
{
//set bit 50 of the OCC LFIR so that the PRDF component will log an error and callout the processor
//TMGT will also see a problem and log an error but it will be informational.
_putscom(OCB_OCCLFIR_OR, OCC_LFIR_SPARE_BIT50, SCOM_TIMEOUT);
//Halt occ so that hardware will enter safe mode
OCC_HALT(ERRL_RC_OCC_HW_ERROR);
}
// Enable and register any ISR's that need to be set up as early as possible.
void occ_irq_setup()
{
int l_rc;
errlHndl_t l_err;
do
{
// ------------- OCC Error IRQ Setup ------------------
// Disable the IRQ while we work on it
ssx_irq_disable(OCCHW_IRQ_OCC_ERROR);
// Set up the IRQ
l_rc = ssx_irq_setup(OCCHW_IRQ_OCC_ERROR,
SSX_IRQ_POLARITY_ACTIVE_HIGH,
SSX_IRQ_TRIGGER_EDGE_SENSITIVE);
if(l_rc)
{
MAIN_TRAC_ERR("occ_irq_setup: ssx_irq_setup(OCCHW_IRQ_OCC_ERROR) failed with rc=0x%08x", l_rc);
break;
}
// Register the IRQ handler with SSX
l_rc = ssx_irq_handler_set(OCCHW_IRQ_OCC_ERROR,
occ_hw_error_isr,
NULL,
SSX_CRITICAL);
if(l_rc)
{
MAIN_TRAC_ERR("occ_irq_setup: ssx_irq_handler_set(OCCHW_IRQ_OCC_ERROR) failed with rc=0x%08x", l_rc);
break;
}
//enable the IRQ
ssx_irq_status_clear(OCCHW_IRQ_OCC_ERROR);
ssx_irq_enable(OCCHW_IRQ_OCC_ERROR);
// ------------- PMC Error IRQ Setup ------------------
/* TODO - RTC: 134619 -- IS THIS NO LONGER A THING IN P9??
// Disable the IRQ while we work on it
ssx_irq_disable(OCCHW_IRQ_PMC_ERROR);
// Set up the IRQ
l_rc = ssx_irq_setup(OCCHW_IRQ_PMC_ERROR,
SSX_IRQ_POLARITY_ACTIVE_HIGH,
SSX_IRQ_TRIGGER_EDGE_SENSITIVE);
if(l_rc)
{
MAIN_TRAC_ERR("occ_irq_setup: ssx_irq_setup(OCCHW_IRQ_PMC_ERROR) failed with rc=0x%08x", l_rc);
break;
}
// Register the IRQ handler with SSX
l_rc = ssx_irq_handler_set(OCCHW_IRQ_PMC_ERROR,
pmc_hw_error_fast,
NULL,
SSX_NONCRITICAL);
if(l_rc)
{
MAIN_TRAC_ERR("occ_irq_setup: ssx_irq_handler_set(OCCHW_IRQ_PMC_ERROR) failed with rc=0x%08x", l_rc);
break;
}
//enable the IRQ
ssx_irq_status_clear(OCCHW_IRQ_PMC_ERROR);
ssx_irq_enable(OCCHW_IRQ_PMC_ERROR);
END TODO */
}while(0);
if(l_rc)
{
//single error for all error cases, just look at trace to see where it failed.
/* @
* @moduleid OCC_IRQ_SETUP
* @reasonCode SSX_GENERIC_FAILURE
* @severity ERRL_SEV_UNRECOVERABLE
* @userdata1 SSX return code
* @userdata4 OCC_NO_EXTENDED_RC
* @devdesc Firmware failure initializing IRQ
*/
l_err = createErrl( OCC_IRQ_SETUP, // i_modId,
SSX_GENERIC_FAILURE, // i_reasonCode,
OCC_NO_EXTENDED_RC,
ERRL_SEV_UNRECOVERABLE,
NULL, // tracDesc_t i_trace,
0, // i_traceSz,
l_rc, // i_userData1,
0); // i_userData2
//Callout firmware
addCalloutToErrl(l_err,
ERRL_CALLOUT_TYPE_COMPONENT_ID,
ERRL_COMPONENT_ID_FIRMWARE,
ERRL_CALLOUT_PRIORITY_HIGH);
commitErrl(&l_err);
}
}
/*
* Function Specification
*
* Name: create_tlb_entry
*
* Description: Creates a TLB entry in the 405 processor to access PGPE space.
* The TLB entry has read only access, and is cache-inhibited.
* This call takes care of pages alignment
* and adds additional pages in case the requested
* space crosses page boundaries.
*
* will result in panic if the TLB entry allocation
* fails.
*
* End Function Specification
*/
#define PAGE_SIZE PPC405_PAGE_SIZE_MIN
#define PAGE_ALIGNED_ADDRESS(addr) (addr & ~((uint32_t)(PAGE_SIZE-1)))
#define PAGE_ALIGNED_SIZE(sz) ((uint32_t)PAGE_SIZE*(((uint32_t)sz/PAGE_SIZE)+1))
void create_tlb_entry(uint32_t address, uint32_t size)
{
int l_rc = SSX_OK;
uint32_t tlb_entry_address, tlb_entry_size; // address and size that guarantee page alignment
tlb_entry_address = PAGE_ALIGNED_ADDRESS(address);
if(address + (size%PPC405_PAGE_SIZE_MIN) >=
tlb_entry_address + PPC405_PAGE_SIZE_MIN)
{
tlb_entry_size = PAGE_ALIGNED_SIZE(size+PPC405_PAGE_SIZE_MIN);
}
else
{
tlb_entry_size = PAGE_ALIGNED_SIZE(size);
}
#if PPC405_MMU_SUPPORT
// define DTLB for page aligned address and size
l_rc = ppc405_mmu_map(
tlb_entry_address,
tlb_entry_address,
tlb_entry_size,
0,
TLBLO_I, //Read-only, Cache-inhibited
NULL
);
#endif
if(l_rc != SSX_OK)
{
MAIN_TRAC_ERR("Failed to create TLB entry,"
"TLB Page Address[0x%08x], TLB Entry size[0x%08x], rc[0x%08x]",
tlb_entry_address, tlb_entry_size, l_rc);
/* @
* @errortype
* @moduleid CREATE_TLB_ENTRY
* @reasoncode SSX_GENERIC_FAILURE
* @userdata1 ppc405_mmu_map return code
* @userdata2 address for which a TLB entry is created
* @userdata4 ERC_TLB_ENTRY_CREATION_FAILURE
* @devdesc SSX semaphore related failure
*/
errlHndl_t l_err = createErrl(CREATE_TLB_ENTRY, //modId
SSX_GENERIC_FAILURE, //reasoncode
ERC_TLB_ENTRY_CREATION_FAILURE, //Extended reason code
ERRL_SEV_UNRECOVERABLE, //Severity
NULL, //Trace Buf
DEFAULT_TRACE_SIZE, //Trace Size
l_rc, //userdata1
address); //userdata2
REQUEST_RESET(l_err);
}
MAIN_TRAC_IMP("Created TLB entry for Address[0x%08x]"
"TLB Page Address[0x%08x], TLB Entry size[0x%08x]",
address, tlb_entry_address, tlb_entry_size);
}
/*
* Function Specification
*
* Name: read_wof_header
*
* Description: Read WOF Tables header and populate global variables
* needed for WOF
*
* End Function Specification
*/
void read_wof_header(void)
{
int l_ssxrc = SSX_OK;
uint32_t l_reasonCode = 0;
uint32_t l_extReasonCode = 0;
do
{
// use block copy engine to read WOF header
BceRequest l_wof_header_req;
// 128 byte aligned buffer to read the data
temp_bce_request_buffer_t l_temp_bce_buff = {{0}};
uint32_t pad = g_amec->wof.vfrt_tbls_main_mem_addr%128;
// Force WOF tables address is on 128 byte boundary
uint32_t wof_main_mem_addr_128 = g_amec->wof.vfrt_tbls_main_mem_addr - pad;
// Create request
l_ssxrc = bce_request_create(&l_wof_header_req, // block copy object
&G_pba_bcde_queue, // main to sram copy engine
wof_main_mem_addr_128, // mainstore address
(uint32_t) &l_temp_bce_buff, // SRAM start address
MIN_BCE_REQ_SIZE, // size of copy
SSX_WAIT_FOREVER, // no timeout
NULL, // no call back
NULL, // no call back args
ASYNC_REQUEST_BLOCKING);// blocking request
if(l_ssxrc != SSX_OK)
{
CMDH_TRAC_ERR("read_wof_header: BCDE request create failure rc=[%08X]", -l_ssxrc);
/*
* @errortype
* @moduleid READ_WOF_HEADER
* @reasoncode SSX_GENERIC_FAILURE
* @userdata1 RC for BCE block-copy engine
* @userdata2 Internal function checkpoint
* @userdata4 ERC_BCE_REQUEST_CREATE_FAILURE
* @devdesc Failed to create BCDE request
*/
l_reasonCode = SSX_GENERIC_FAILURE;
l_extReasonCode = ERC_BCE_REQUEST_CREATE_FAILURE;
break;
}
// Do the actual copy
l_ssxrc = bce_request_schedule(&l_wof_header_req);
if(l_ssxrc != SSX_OK)
{
CMDH_TRAC_ERR("read_wof_header: BCE request schedule failure rc=[%08X]", -l_ssxrc);
/*
* @errortype
* @moduleid READ_WOF_HEADER
* @reasoncode SSX_GENERIC_FAILURE
* @userdata1 RC for BCE block-copy engine
* @userdata4 ERC_BCE_REQUEST_SCHEDULE_FAILURE
* @devdesc Failed to read PPMR data by using BCDE
*/
l_reasonCode = SSX_GENERIC_FAILURE;
l_extReasonCode = ERC_BCE_REQUEST_SCHEDULE_FAILURE;
break;
}
// Copy the data into Global WOF header struct
memcpy(&G_wof_header, &(l_temp_bce_buff.data[pad]), sizeof(wof_header_data_t));
// Make sure the header is reporting a valid number of quads i.e. 1 or 6
if( (G_wof_header.active_quads_size != ACTIVE_QUAD_SZ_MIN) &&
(G_wof_header.active_quads_size != ACTIVE_QUAD_SZ_MAX) )
{
CMDH_TRAC_ERR("read_wof_header: Invalid number of active quads!"
" Expected: 1 or 6, Actual %d",
G_wof_header.active_quads_size );
/*
* @errortype
* @moduleid READ_WOF_HEADER
* @reasoncode INVALID_ACTIVE_QUAD_COUNT
* @userdata1 Reported active quad count
* @userdata4 Quad count failure
* @devdesc Read an invalid number of active quads
*/
l_reasonCode = INVALID_ACTIVE_QUAD_COUNT;
l_extReasonCode = ERC_WOF_QUAD_COUNT_FAILURE;
errlHndl_t l_errl = createErrl(READ_WOF_HEADER, //modId
INVALID_ACTIVE_QUAD_COUNT, //reasoncode
ERC_WOF_QUAD_COUNT_FAILURE, //Extended reason code
ERRL_SEV_UNRECOVERABLE, //Severity
NULL, //Trace Buf
0, //Trace Size
G_wof_header.active_quads_size, //userdata1
0); //userdata2
// Callout firmware
addCalloutToErrl(l_errl,
ERRL_CALLOUT_TYPE_COMPONENT_ID,
ERRL_COMPONENT_ID_FIRMWARE,
ERRL_CALLOUT_PRIORITY_HIGH);
// Commit error log
commitErrl(&l_errl);
// We were unable to get the active quad count. Do not run wof algo.
g_amec->wof.wof_disabled |= WOF_RC_INVALID_ACTIVE_QUADS_MASK;
}
}while( 0 );
// Check for errors and log, if any
if( l_ssxrc != SSX_OK )
{
errlHndl_t l_errl = createErrl(READ_WOF_HEADER, //modId
l_reasonCode, //reasoncode
l_extReasonCode, //Extended reason code
ERRL_SEV_UNRECOVERABLE, //Severity
NULL, //Trace Buf
0, //Trace Size
-l_ssxrc, //userdata1
0); //userdata2
// Callout firmware
addCalloutToErrl(l_errl,
ERRL_CALLOUT_TYPE_COMPONENT_ID,
ERRL_COMPONENT_ID_FIRMWARE,
ERRL_CALLOUT_PRIORITY_HIGH);
// Commit error log
commitErrl(&l_errl);
// We were unable to get the WOF header thus it should not be run.
g_amec->wof.wof_disabled |= WOF_RC_NO_WOF_HEADER_MASK;
return;
}
}
/*
* Function Specification
*
* Name: read_pgpe_header
*
* Description: Initialize PGPE image header entry in DTLB,
* Read PGPE image header, lookup shared SRAM address and size,
* Initialize OCC/PGPE shared SRAM entry in the DTLB,
* Populate global variables, including G_pgpe_peacon_address.
*
* End Function Specification
*/
void read_pgpe_header(void)
{
uint64_t magic_number;
errlHndl_t l_err;
// define DTLB for the PGPE image header
create_tlb_entry(PGPE_HEADER_ADDR, PGPE_HEADER_SZ);
// verify the validity of the magic number
magic_number = in64(PGPE_HEADER_ADDR);
if(PGPE_MAGIC_NUMBER != magic_number)
{
// The Magic number is invalid .. Invalid or corrupt PGPE image header
MAIN_TRAC_ERR("Invalid PGPGE Magic number. Address[0x%08X], Magic Number[0x%08X%08X]",
PGPE_HEADER_ADDR, (uint32_t)(magic_number>>32), (uint32_t)magic_number);
/* @
* @errortype
* @moduleid READ_PGPE_HEADER
* @reasoncode INVALID_MAGIC_NUMBER
* @userdata1 Low order 32 bits of retrieved PGPE magic number
* @userdata2 Hight order 32 bits of retrieved PGPE magic number
* @userdata4 OCC_NO_EXTENDED_RC
* @devdesc SSX semaphore related failure
*/
l_err = createErrl(READ_PGPE_HEADER, //modId
INVALID_MAGIC_NUMBER, //reasoncode
OCC_NO_EXTENDED_RC, //Extended reason code
ERRL_SEV_UNRECOVERABLE, //Severity
NULL, //Trace Buf
DEFAULT_TRACE_SIZE, //Trace Size
(uint32_t)magic_number, //userdata1
(uint32_t)(magic_number>>32)); //userdata2
REQUEST_RESET(l_err);
}
if(l_err == NULL)
{
// Read PGPE Beacon address from PGPE image header
G_pgpe_beacon_address = in32(PGPE_BEACON_ADDR_PTR);
MAIN_TRAC_IMP("Read PGPE Beacon Address[0x%08x]",
G_pgpe_beacon_address);
// Read active quads address, wof tables address, and wof tables len
g_amec->wof.active_quads_sram_addr = in32(PGPE_ACTIVE_QUAD_ADDR_PTR);
g_amec->wof.vfrt_tbls_main_mem_addr = in32(PGPE_WOF_TBLS_ADDR_PTR);
g_amec->wof.vfrt_tbls_len = in32(PGPE_WOF_TBLS_LEN_PTR);
MAIN_TRAC_IMP("Read WOF Tables Main Memory Address[0x%08x], Len[0x%08x],"
" Active Quads Address[0x%08x]",
g_amec->wof.vfrt_tbls_main_mem_addr,
g_amec->wof.vfrt_tbls_len,
g_amec->wof.active_quads_sram_addr );
// Extract important WOF data into global space
read_wof_header();
// Read OCC/PGPE Shared SRAM address and size
G_pgpe_shared_sram_address = in32(PGPE_SHARED_SRAM_ADDR_PTR);
G_pgpe_shared_sram_sz = in32(PGPE_SHARED_SRAM_SZ_PTR);
MAIN_TRAC_IMP("Read PGPE Shared SRAM Start Address[0x%08x], Size[0x%08x]",
G_pgpe_shared_sram_address, G_pgpe_shared_sram_sz);
// Read OCC Pstate table address and size
G_pgpe_pstate_table_address = in32(PGPE_PSTATE_TBL_ADDR_PTR);
G_pgpe_pstate_table_sz = in32(PGPE_PSTATE_TBL_SZ_PTR);
// PGPE Beacon is not implemented in simics yet
// the G_pgpe_shared_sram_address and G_pgpe_shared_sram_sz pointers don't
// have the proper values yet.
// @TODO: remove this condition when PGPE code is integrated. RTC: 163934
if(!G_simics_environment)
{
// define DTLB for OCC/PGPE shared SRAM, which enables access
// to OCC-PGPE Shared SRAM space, including pgpe_beacon
create_tlb_entry(G_pgpe_shared_sram_address, G_pgpe_shared_sram_sz);
}
}
return;
}
/*
* Function Specification
*
* Name: read_ppmr_header
*
* Description: read PPMR image header, and extract the
* OPPB HOMER offset and sturcture size..
*
* End Function Specification
*/
void read_ppmr_header(void)
{
int l_ssxrc = SSX_OK;
uint32_t l_reasonCode = 0;
uint32_t l_extReasonCode = 0;
// error log parameters, if any
uint32_t userdata1 = 0;
uint32_t userdata2 = 0;
// create a DTLB entry for the PPMR image header
create_tlb_entry(PPMR_ADDRESS_HOMER, sizeof(ppmr_header_t));
do{
// use block copy engine to read the PPMR header
BceRequest pba_copy;
// Set up a copy request
l_ssxrc = bce_request_create(&pba_copy, // block copy object
&G_pba_bcde_queue, // mainstore to sram copy engine
PPMR_ADDRESS_HOMER, // mainstore address
(uint32_t) &G_ppmr_header, // sram starting address
(size_t) sizeof(G_ppmr_header), // size of copy
SSX_WAIT_FOREVER, // no timeout
NULL, // no call back
NULL, // no call back arguments
ASYNC_REQUEST_BLOCKING); // blocking request
if(l_ssxrc != SSX_OK)
{
MAIN_TRAC_ERR("read_ppmr_header: BCDE request create failure rc=[%08X]", -l_ssxrc);
/*
* @errortype
* @moduleid READ_PPMR_HEADER
* @reasoncode SSX_GENERIC_FAILURE
* @userdata1 RC for BCE block-copy engine
* @userdata2 Internal function checkpoint
* @userdata4 ERC_BCE_REQUEST_CREATE_FAILURE
* @devdesc Failed to create BCDE request
*/
l_reasonCode = SSX_GENERIC_FAILURE;
l_extReasonCode = ERC_BCE_REQUEST_CREATE_FAILURE;
userdata1 = (uint32_t)(-l_ssxrc);
break;
}
// Do actual copying
l_ssxrc = bce_request_schedule(&pba_copy);
if(l_ssxrc != SSX_OK)
{
MAIN_TRAC_ERR("read_ppmr_header: BCE request schedule failure rc=[%08X]", -l_ssxrc);
/*
* @errortype
* @moduleid READ_PPMR_HEADER
* @reasoncode SSX_GENERIC_FAILURE
* @userdata1 RC for BCE block-copy engine
* @userdata4 ERC_BCE_REQUEST_SCHEDULE_FAILURE
* @devdesc Failed to read PPMR data by using BCDE
*/
l_reasonCode = SSX_GENERIC_FAILURE;
l_extReasonCode = ERC_BCE_REQUEST_SCHEDULE_FAILURE;
userdata1 = (uint32_t)(-l_ssxrc);
break;
}
if(G_ppmr_header.oppb_length != sizeof(OCCPstateParmBlock))
{
MAIN_TRAC_ERR("read_ppmr_header: OCCPstateParmBlock size mismatch:"
"PPMR header sz[0x%08x] PPMR struct sz[0x%08x]",
G_ppmr_header.oppb_length, sizeof(OCCPstateParmBlock));
/*
* @errortype
* @moduleid READ_PPMR_HEADER
* @reasoncode PGPE_FAILURE
* @userdata1 G_ppmr_header.oppb_length
* @userdata2 sizeof(OCCPstateParmBlock)
* @userdata4 ERC_PGPE_PPMR_OPPB_SIZE_MISMATCH
* @devdesc PPMR's OPPB size mismatches data structure's
*/
l_reasonCode = SSX_GENERIC_FAILURE;
l_extReasonCode = ERC_BCE_REQUEST_SCHEDULE_FAILURE;
userdata1 = G_ppmr_header.oppb_length;
userdata2 = sizeof(OCCPstateParmBlock);
break;
}
} while (0);
if ( l_reasonCode )
{
errlHndl_t l_errl = createErrl(READ_PPMR_HEADER, //modId
l_reasonCode, //reasoncode
l_extReasonCode, //Extended reason code
ERRL_SEV_UNRECOVERABLE, //Severity
NULL, //Trace Buf
0, //Trace Size
userdata1, //userdata1
userdata2); //userdata2
// Callout firmware
addCalloutToErrl(l_errl,
ERRL_CALLOUT_TYPE_COMPONENT_ID,
ERRL_COMPONENT_ID_FIRMWARE,
ERRL_CALLOUT_PRIORITY_HIGH);
REQUEST_RESET(l_errl);
return;
}
// Read OCC pstates parameter block
read_oppb_params((OCCPstateParmBlock*)G_ppmr_header.oppb_offset);
}
/*
* Function Specification
*
* Name: read_oppb_params
*
* Description: Read the OCC Pstates Parameter Block,
* and initializa Pstates Global Variables.
*
* End Function Specification
*/
void read_oppb_params(const OCCPstateParmBlock* oppb_offset)
{
int l_ssxrc = SSX_OK;
uint32_t l_reasonCode = 0;
uint32_t l_extReasonCode = 0;
create_tlb_entry( ((uint32_t)oppb_offset + (uint32_t)PPMR_ADDRESS_HOMER),
sizeof(OCCPstateParmBlock));
do{
// use block copy engine to read the PPMR header
BceRequest pba_copy;
// Set up a copy request
l_ssxrc = bce_request_create(&pba_copy, // block copy object
&G_pba_bcde_queue, // mainstore to sram copy engine
(uint32_t)PPMR_ADDRESS_HOMER +
(uint32_t)oppb_offset, // mainstore address
(uint32_t) &G_oppb, // sram starting address
(size_t) sizeof(OCCPstateParmBlock), // size of copy
SSX_WAIT_FOREVER, // no timeout
NULL, // no call back
NULL, // no call back arguments
ASYNC_REQUEST_BLOCKING); // blocking request
if(l_ssxrc != SSX_OK)
{
CMDH_TRAC_ERR("read_oppb_params: BCDE request create failure rc=[%08X]", -l_ssxrc);
/*
* @errortype
* @moduleid READ_OPPB_PARAMS
* @reasoncode SSX_GENERIC_FAILURE
* @userdata1 RC for BCE block-copy engine
* @userdata2 Internal function checkpoint
* @userdata4 ERC_BCE_REQUEST_CREATE_FAILURE
* @devdesc Failed to create BCDE request
*/
l_reasonCode = SSX_GENERIC_FAILURE;
l_extReasonCode = ERC_BCE_REQUEST_CREATE_FAILURE;
break;
}
// Do actual copying
l_ssxrc = bce_request_schedule(&pba_copy);
if(l_ssxrc != SSX_OK)
{
CMDH_TRAC_ERR("read_oppb_params: BCE request schedule failure rc=[%08X]", -l_ssxrc);
/*
* @errortype
* @moduleid READ_OPPB_PARAMS
* @reasoncode SSX_GENERIC_FAILURE
* @userdata1 RC for BCE block-copy engine
* @userdata4 ERC_BCE_REQUEST_SCHEDULE_FAILURE
* @devdesc Failed to read PPMR data by using BCDE
*/
l_reasonCode = SSX_GENERIC_FAILURE;
l_extReasonCode = ERC_BCE_REQUEST_SCHEDULE_FAILURE;
break;
}
} while (0);
// Read WOF addresses
MAIN_TRAC_IMP("Read PGPE Shared SRAM Start Address[0x%08x], Size[0x%08x]",
G_pgpe_shared_sram_address, G_pgpe_shared_sram_sz);
if ( l_ssxrc != SSX_OK )
{
errlHndl_t l_errl = createErrl(READ_OPPB_PARAMS, //modId
l_reasonCode, //reasoncode
l_extReasonCode, //Extended reason code
ERRL_SEV_UNRECOVERABLE, //Severity
NULL, //Trace Buf
0, //Trace Size
-l_ssxrc, //userdata1
0); //userdata2
// Callout firmware
addCalloutToErrl(l_errl,
ERRL_CALLOUT_TYPE_COMPONENT_ID,
ERRL_COMPONENT_ID_FIRMWARE,
ERRL_CALLOUT_PRIORITY_HIGH);
REQUEST_RESET(l_errl);
return;
}
// Copy over max frequency into G_proc_fmax_mhz
G_proc_fmax_mhz = G_oppb.frequency_max_khz / 1000;
// Used by amec for pcap calculation could use G_oppb.frequency_step_khz
// in PCAP calculationsinstead, but using a separate varaible speeds
// up PCAP relatedcalculations significantly, by eliminating slow
// division operations.
G_mhz_per_pstate = G_oppb.frequency_step_khz/1000;
TRAC_INFO("read_oppb_params: OCC Pstates Parameter Block read successfully");
}
/*
* Function Specification
*
* Name: gpe_reset
*
* Description: Force a GPE to start executing instructions at the reset vector
*
* End Function Specification
*/
void gpe_reset(uint32_t instance_id)
{
#define XCR_CMD_HRESET 0x60000000
#define XCR_CMD_TOGGLE_XSR 0x40000000
#define XCR_CMD_RESUME 0x20000000
#define GPE_SRAM_BASE 0xFFF00000
uint32_t l_gpe_sram_addr = (instance_id * 0x10000) + GPE_SRAM_BASE;