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WOF: Function to calculate core voltage and leakage
Change-Id: Ica95c4030c81c959e834797ef998af7d025cf250 RTC:130216 Depends-on: I33bce916dc2dffef6a6d616633a5f1266d7baa7e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35759 Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
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10 files changed

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‎src/occ_405/amec/amec_parm.h

Lines changed: 39 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
/* */
66
/* OpenPOWER OnChipController Project */
77
/* */
8-
/* Contributors Listed Below - COPYRIGHT 2011,2015 */
8+
/* Contributors Listed Below - COPYRIGHT 2011,2017 */
99
/* [+] International Business Machines Corp. */
1010
/* */
1111
/* */
@@ -69,10 +69,47 @@ typedef enum
6969
PARM_SOFT_FMIN,
7070
PARM_SOFT_FMAX,
7171
PARM_TOD,
72+
// WOF Parameters
73+
PARM_V_CORE,
74+
PARM_CORE_PWR_ON,
75+
PARM_CORES_ON_PER_QUAD,
76+
PARM_WOF_DISABLED,
77+
PARM_VOLT_VDD_SENSE,
78+
PARM_TEMPPROCTHERMC,
79+
PARM_TEMPNEST,
80+
PARM_TEMPQ,
81+
PARM_QUAD_X_PSTATES,
82+
PARM_IVRM_STATES,
83+
PARM_IDC_VDD,
84+
PARM_IDC_QUAD,
85+
PARM_VOLTAGE_IDX,
86+
PARM_ALL_CORES_OFF_ISO,
87+
PARM_ALL_CACHES_ON_ISO,
88+
PARM_QUAD_GOOD_CORES_ONLY,
89+
PARM_QUAD_ON_CORES,
90+
PARM_QUAD_BAD_OFF_CORES,
91+
PARM_NEST_MULT,
92+
PARM_CORE_MULT,
93+
PARM_QUAD_MULT,
94+
PARM_NEST_DELTA_TEMP,
95+
PARM_CORE_DELTA_TEMP,
96+
PARM_QUAD_DELTA_TEMP,
97+
PARM_TVPD_LEAK_OFF,
98+
PARM_TVPD_LEAK_ON,
99+
PARM_TVPD_LEAK_CACHE,
100+
PARM_REQ_ACTIVE_QUAD_UPDATE,
101+
PARM_PREV_REQ_ACTIVE_QUADS,
102+
PARM_CURR_PING_PONG_BUF,
103+
PARM_NEXT_PING_PONG_BUF,
104+
PARM_CURR_VFRT_MAIN_MEM_ADDR,
105+
PARM_ACTIVE_QUADS_SRAM_ADDR,
106+
PARM_VFRT_TBLS_MAIN_MEM_ADDR,
107+
PARM_VFRT_TBLS_LEN,
108+
// End WOF Parameters
72109
AMEC_PARM_NUMBER_OF_PARAMETERS
73110
} AMEC_PARM_ENUM;
74111

75-
typedef enum
112+
typedef enum
76113
{
77114
AMEC_PARM_TYPE_UINT8 = 0,
78115
AMEC_PARM_TYPE_UINT16,

‎src/occ_405/amec/amec_parm_table.c

Lines changed: 41 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
/* */
66
/* OpenPOWER OnChipController Project */
77
/* */
8-
/* Contributors Listed Below - COPYRIGHT 2011,2015 */
8+
/* Contributors Listed Below - COPYRIGHT 2011,2017 */
99
/* [+] International Business Machines Corp. */
1010
/* */
1111
/* */
@@ -138,6 +138,46 @@ amec_parm_t g_amec_parm_list[] = {
138138
AMEC_PARM_UINT16(PARM_SOFT_FMIN,"part_soft_fmin",&g_amec_sys.part_config.part_list[0].soft_fmin),
139139
AMEC_PARM_UINT16(PARM_SOFT_FMAX,"part_soft_fmax",&g_amec_sys.part_config.part_list[0].soft_fmax),
140140
AMEC_PARM_RAW(PARM_TOD,"apss_tod",&G_dcom_slv_inbox_doorbell_rx.tod,8),
141+
142+
143+
144+
// Begin WOF parameters
145+
AMEC_PARM_UINT32_ARRAY(PARM_V_CORE, "v_core_100uV", &g_amec_sys.wof.v_core_100uV, MAX_NUM_QUADS),
146+
AMEC_PARM_UINT32(PARM_CORE_PWR_ON, "core_pwr_on", &g_amec_sys.wof.core_pwr_on),
147+
AMEC_PARM_UINT8_ARRAY(PARM_CORES_ON_PER_QUAD, "coreson_per_quad", &g_amec_sys.wof.cores_on_per_quad, MAX_NUM_QUADS),
148+
AMEC_PARM_UINT16(PARM_WOF_DISABLED, "wof_disabled", &g_amec_sys.wof.wof_disabled),
149+
AMEC_PARM_UINT32(PARM_VOLT_VDD_SENSE, "volt_vdd_sense", &g_amec_sys.wof.volt_vdd_sense),
150+
AMEC_PARM_UINT16_ARRAY(PARM_TEMPPROCTHERMC, "tempprocthrmc", &g_amec_sys.wof.tempprocthrmc, MAX_NUM_CORES),
151+
AMEC_PARM_UINT16(PARM_TEMPNEST, "tempnest_sense", &g_amec_sys.wof.tempnest_sense),
152+
AMEC_PARM_UINT16_ARRAY(PARM_TEMPQ, "tempq", &g_amec_sys.wof.tempq, MAX_NUM_QUADS),
153+
AMEC_PARM_UINT8_ARRAY(PARM_QUAD_X_PSTATES, "quad_x_pstates", &g_amec_sys.wof.quad_x_pstates, MAX_NUM_QUADS),
154+
AMEC_PARM_UINT8(PARM_IVRM_STATES, "quad_ivrm_states", &g_amec_sys.wof.quad_ivrm_states),
155+
AMEC_PARM_UINT32(PARM_IDC_VDD, "idc_vdd", &g_amec_sys.wof.idc_vdd),
156+
AMEC_PARM_UINT32(PARM_IDC_QUAD, "idc_quad", &g_amec_sys.wof.idc_quad),
157+
AMEC_PARM_UINT8(PARM_VOLTAGE_IDX, "voltage_idx", &g_amec_sys.wof.voltage_idx),
158+
AMEC_PARM_UINT32(PARM_ALL_CORES_OFF_ISO, "allcores_off_iso", &g_amec_sys.wof.all_cores_off_iso),
159+
AMEC_PARM_UINT32(PARM_ALL_CACHES_ON_ISO, "allcaches_on_iso", &g_amec_sys.wof.all_caches_on_iso),
160+
AMEC_PARM_UINT16_ARRAY(PARM_QUAD_GOOD_CORES_ONLY, "quad_good_cores", &g_amec_sys.wof.quad_good_cores_only, MAX_NUM_QUADS),
161+
AMEC_PARM_UINT16_ARRAY(PARM_QUAD_ON_CORES, "quad_on_cores", &g_amec_sys.wof.quad_on_cores, MAX_NUM_QUADS),
162+
AMEC_PARM_UINT16_ARRAY(PARM_QUAD_BAD_OFF_CORES,"quadBadOffCores", &g_amec_sys.wof.quad_on_cores, MAX_NUM_QUADS),
163+
AMEC_PARM_UINT32(PARM_NEST_MULT, "nest_mult", &g_amec_sys.wof.nest_mult),
164+
AMEC_PARM_UINT32_ARRAY(PARM_CORE_MULT, "core_mult", &g_amec_sys.wof.core_mult, MAX_NUM_CORES),
165+
AMEC_PARM_UINT32_ARRAY(PARM_QUAD_MULT, "quad_mult", &g_amec_sys.wof.quad_mult, MAX_NUM_QUADS),
166+
AMEC_PARM_INT16(PARM_NEST_DELTA_TEMP, "nest_delta_temp", &g_amec_sys.wof.nest_delta_temp),
167+
AMEC_PARM_INT16_ARRAY(PARM_CORE_DELTA_TEMP, "core_delta_temp", &g_amec_sys.wof.core_delta_temp, MAX_NUM_CORES),
168+
AMEC_PARM_INT16_ARRAY(PARM_QUAD_DELTA_TEMP, "quad_delta_temp", &g_amec_sys.wof.quad_delta_temp, MAX_NUM_CORES),
169+
AMEC_PARM_UINT16(PARM_TVPD_LEAK_OFF, "tvpd_leak_off", &g_amec_sys.wof.tvpd_leak_off),
170+
AMEC_PARM_UINT16(PARM_TVPD_LEAK_ON, "tvpd_leak_on", &g_amec_sys.wof.tvpd_leak_on),
171+
AMEC_PARM_UINT16(PARM_TVPD_LEAK_CACHE, "tvpd_leak_cache", &g_amec_sys.wof.tvpd_leak_cache),
172+
AMEC_PARM_UINT8(PARM_REQ_ACTIVE_QUAD_UPDATE, "req_active_quad", &g_amec_sys.wof.req_active_quad_update),
173+
AMEC_PARM_UINT8(PARM_PREV_REQ_ACTIVE_QUADS, "prevActiveQuads", &g_amec_sys.wof.prev_req_active_quads),
174+
AMEC_PARM_UINT32(PARM_CURR_PING_PONG_BUF, "currPingPongBuf", &g_amec_sys.wof.curr_ping_pong_buf),
175+
AMEC_PARM_UINT32(PARM_NEXT_PING_PONG_BUF, "nextPingPongBuf", &g_amec_sys.wof.next_ping_pong_buf),
176+
AMEC_PARM_UINT32(PARM_CURR_VFRT_MAIN_MEM_ADDR, "vfrtMainMemAddr", &g_amec_sys.wof.curr_vfrt_main_mem_addr),
177+
AMEC_PARM_UINT32(PARM_ACTIVE_QUADS_SRAM_ADDR, "activQuadSramPtr", &g_amec_sys.wof.active_quads_sram_addr),
178+
AMEC_PARM_UINT32(PARM_VFRT_TBLS_MAIN_MEM_ADDR, "vfrtMainMemAddr", &g_amec_sys.wof.vfrt_tbls_main_mem_addr),
179+
AMEC_PARM_UINT32(PARM_VFRT_TBLS_LEN, "vfrt_tbls_len", &g_amec_sys.wof.vfrt_tbls_len),
180+
// End WOF parameters
141181
};
142182

143183
//Throw a compiler error when the enum and array are not both updated

‎src/occ_405/cmdh/cmdh_fsp_cmds_datacnfg.c

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
/* */
66
/* OpenPOWER OnChipController Project */
77
/* */
8-
/* Contributors Listed Below - COPYRIGHT 2011,2016 */
8+
/* Contributors Listed Below - COPYRIGHT 2011,2017 */
99
/* [+] International Business Machines Corp. */
1010
/* */
1111
/* */
@@ -44,6 +44,7 @@
4444
#include "memory.h"
4545
#include <avsbus.h>
4646
#include "p9_pstates_occ.h"
47+
#include <wof.h>
4748

4849
#define FREQ_FORMAT_PWR_MODE_NUM 6
4950
#define FREQ_FORMAT_BASE_DATA_SZ (sizeof(cmdh_store_mode_freqs_t) - sizeof(cmdh_fsp_cmd_header_t))
@@ -1094,14 +1095,21 @@ errlHndl_t data_store_avsbus_config(const cmdh_fsp_cmd_t * i_cmd_ptr,
10941095
l_invalid_data = TRUE;
10951096
}
10961097

1097-
if (l_invalid_data)
1098+
if (l_invalid_data || !G_avsbus_vdd_monitoring || !G_avsbus_vdn_monitoring)
10981099
{
10991100
cmdh_build_errl_rsp(i_cmd_ptr, o_rsp_ptr, ERRL_RC_INVALID_DATA, &l_err);
11001101
G_avsbus_vdd_monitoring = FALSE;
11011102
G_avsbus_vdn_monitoring = FALSE;
1103+
1104+
// If cannot use vdd/vdn, cannot run wof algorithm.
1105+
g_amec->wof.wof_disabled |= WOF_RC_NO_VDD_VDN_READ_MASK;
1106+
11021107
}
11031108
else
11041109
{
1110+
// We can use vdd/vdn. Clear NO_VDD_VDN_READ mask
1111+
g_amec->wof.wof_disabled &= ~WOF_RC_NO_VDD_VDN_READ_MASK;
1112+
11051113
avsbus_init();
11061114
}
11071115

‎src/occ_405/main.c

Lines changed: 20 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -79,10 +79,6 @@ extern uint32_t G_pgpe_beacon_address;
7979

8080
extern uint32_t G_proc_fmin_khz;
8181
extern uint32_t G_proc_fmax_khz;
82-
extern uint32_t G_wof_active_quads_sram_addr;
83-
extern uint32_t G_wof_tables_main_mem_addr;
84-
extern uint32_t G_wof_tables_len;
85-
extern bool G_run_wof_main;
8682
extern wof_header_data_t G_wof_header;
8783

8884
extern uint32_t G_khz_per_pstate;
@@ -93,8 +89,10 @@ extern uint8_t G_proc_pmax;
9389
IMAGE_HEADER (G_mainAppImageHdr,__ssx_boot,MAIN_APP_ID,ID_NUM_INVALID);
9490

9591
// PGPE Image Header Parameters
96-
uint32_t G_pgpe_shared_sram_address = 0;
97-
uint32_t G_pgpe_shared_sram_sz = 0;
92+
uint32_t G_pgpe_shared_sram_address;
93+
uint32_t G_pgpe_shared_sram_sz;
94+
uint32_t G_pgpe_pstate_table_address;
95+
uint32_t G_pgpe_pstate_table_sz;
9896

9997
ppmr_header_t G_ppmr_header; // PPMR Header layout format
10098
OCCPstateParmBlock G_oppb; // OCC Pstate Parameters Block Structure
@@ -513,9 +511,9 @@ void read_wof_header(void)
513511
// 128 byte aligned buffer to read the data
514512
temp_bce_request_buffer_t l_temp_bce_buff = {{0}};
515513

516-
uint32_t pad = G_wof_tables_main_mem_addr%128;
514+
uint32_t pad = g_amec->wof.vfrt_tbls_main_mem_addr%128;
517515
// Force WOF tables address is on 128 byte boundary
518-
uint32_t wof_main_mem_addr_128 = G_wof_tables_main_mem_addr - pad;
516+
uint32_t wof_main_mem_addr_128 = g_amec->wof.vfrt_tbls_main_mem_addr - pad;
519517
// Create request
520518
l_ssxrc = bce_request_create(&l_wof_header_req, // block copy object
521519
&G_pba_bcde_queue, // main to sram copy engine
@@ -581,6 +579,7 @@ void read_wof_header(void)
581579
* @moduleid READ_WOF_HEADER
582580
* @reasoncode INVALID_ACTIVE_QUAD_COUNT
583581
* @userdata1 Reported active quad count
582+
* @userdata4 Quad count failure
584583
* @devdesc Read an invalid number of active quads
585584
*/
586585
l_reasonCode = INVALID_ACTIVE_QUAD_COUNT;
@@ -604,7 +603,7 @@ void read_wof_header(void)
604603
commitErrl(&l_errl);
605604

606605
// We were unable to get the active quad count. Do not run wof algo.
607-
G_run_wof_main = false;
606+
g_amec->wof.wof_disabled |= WOF_RC_INVALID_ACTIVE_QUADS_MASK;
608607
}
609608

610609

@@ -632,8 +631,7 @@ void read_wof_header(void)
632631
commitErrl(&l_errl);
633632

634633
// We were unable to get the WOF header thus it should not be run.
635-
G_run_wof_main = false;
636-
634+
g_amec->wof.wof_disabled |= WOF_RC_NO_WOF_HEADER_MASK;
637635
return;
638636

639637
}
@@ -700,15 +698,15 @@ void read_pgpe_header(void)
700698
G_pgpe_beacon_address);
701699

702700
// Read active quads address, wof tables address, and wof tables len
703-
G_wof_active_quads_sram_addr = in32(PGPE_ACTIVE_QUAD_ADDR_PTR);
704-
G_wof_tables_main_mem_addr = in32(PGPE_WOF_TBLS_ADDR_PTR);
705-
G_wof_tables_len = in32(PGPE_WOF_TBLS_LEN_PTR);
701+
g_amec->wof.active_quads_sram_addr = in32(PGPE_ACTIVE_QUAD_ADDR_PTR);
702+
g_amec->wof.vfrt_tbls_main_mem_addr = in32(PGPE_WOF_TBLS_ADDR_PTR);
703+
g_amec->wof.vfrt_tbls_len = in32(PGPE_WOF_TBLS_LEN_PTR);
706704

707705
MAIN_TRAC_IMP("Read WOF Tables Main Memory Address[0x%08x], Len[0x%08x],"
708706
" Active Quads Address[0x%08x]",
709-
G_wof_tables_main_mem_addr,
710-
G_wof_tables_len,
711-
G_wof_active_quads_sram_addr );
707+
g_amec->wof.vfrt_tbls_main_mem_addr,
708+
g_amec->wof.vfrt_tbls_len,
709+
g_amec->wof.active_quads_sram_addr );
712710

713711
// Extract important WOF data into global space
714712
read_wof_header();
@@ -720,6 +718,11 @@ void read_pgpe_header(void)
720718
MAIN_TRAC_IMP("Read PGPE Shared SRAM Start Address[0x%08x], Size[0x%08x]",
721719
G_pgpe_shared_sram_address, G_pgpe_shared_sram_sz);
722720

721+
// Read OCC Pstate table address and size
722+
G_pgpe_pstate_table_address = in32(PGPE_PSTATE_TBL_ADDR_PTR);
723+
G_pgpe_pstate_table_sz = in32(PGPE_PSTATE_TBL_SZ_PTR);
724+
725+
723726
// PGPE Beacon is not implemented in simics yet
724727
// the G_pgpe_shared_sram_address and G_pgpe_shared_sram_sz pointers don't
725728
// have the proper values yet.

‎src/occ_405/occ_service_codes.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -122,6 +122,7 @@ enum occReasonCode
122122
GPE_REQUEST_TASK_TIMEOUT = 0xD6,
123123
GPE_REQUEST_RC_FAILURE = 0xD7,
124124

125+
WOF_VFRT_REQ_FAILURE = 0xD8,
125126
INVALID_MAGIC_NUMBER = 0xDA,
126127

127128
/// Success!

‎src/occ_405/pgpe/pgpe_interface.c

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
/* */
66
/* OpenPOWER OnChipController Project */
77
/* */
8-
/* Contributors Listed Below - COPYRIGHT 2011,2016 */
8+
/* Contributors Listed Below - COPYRIGHT 2011,2017 */
99
/* [+] International Business Machines Corp. */
1010
/* */
1111
/* */
@@ -36,6 +36,7 @@
3636
#include "proc_data_control.h"
3737
#include "occ_sys_config.h"
3838
#include "ssx.h"
39+
#include "wof.h"
3940

4041
extern opal_static_table_t G_opal_static_table;
4142

@@ -374,7 +375,7 @@ errlHndl_t pgpe_init_wof_vfrt(void)
374375
IPC_MSGID_405_WOF_VFRT, // Function ID
375376
&G_wof_vfrt_parms, // Task parameters
376377
SSX_WAIT_FOREVER, // Timeout (none)
377-
NULL, // Callback
378+
(AsyncRequestCallback)switch_ping_pong_buffer, // Callback
378379
NULL, // Callback arguments
379380
ASYNC_CALLBACK_IMMEDIATE); // Options
380381

‎src/occ_405/pgpe/pgpe_shared.h

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,8 @@
3131
// Offset addresses of PGPE Header parameters (relative to start address)
3232
#define PGPE_SHARED_SRAM_ADDR_OFFSET 0x0c
3333
#define PGPE_SHARED_SRAM_SZ_OFFSET 0x14
34+
#define PGPE_PSTATE_TBL_ADDR_OFFSET 0x40
35+
#define PGPE_PSTATE_TBL_SZ_OFFSET 0x44
3436
#define PGPE_BEACON_ADDR_OFFSET 0x48
3537
#define PGPE_ACTIVE_QUAD_ADDR_OFFSET 0x4c
3638
#define PGPE_WOF_TBLS_ADDR_OFFSET 0x50
@@ -53,7 +55,11 @@
5355
#define PGPE_WOF_TBLS_ADDR_PTR (PGPE_HEADER_ADDR + PGPE_WOF_TBLS_ADDR_OFFSET)
5456
#define PGPE_WOF_TBLS_LEN_PTR (PGPE_HEADER_ADDR + PGPE_WOF_TBLS_LEN_OFFSET)
5557

56-
// PMMR (Pstates PM region) in HOMMR
58+
// Pointers to Pstate tables in SRAM
59+
#define PGPE_PSTATE_TBL_ADDR_PTR (PGPE_HEADER_ADDR + PGPE_PSTATE_TBL_ADDR_OFFSET)
60+
#define PGPE_PSTATE_TBL_SZ_PTR (PGPE_HEADER_ADDR + PGPE_PSTATE_TBL_SZ_OFFSET)
61+
62+
// PPMR (Pstates PM region) in HOMMR
5763
#define PPMR_OPPM_ADDR_OFFSET 0x40 //offset of the OCC Pstates Parameter Block address in the PPMR header
5864
#define PPMR_OPPM_SZ_OFFSET 0x44 //offset of the OCC Pstates Parameter Block size in the PPMR header
5965

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