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WOF: Function to calculate core voltage and leakage
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Change-Id: Ica95c4030c81c959e834797ef998af7d025cf250
RTC:130216
Depends-on: I33bce916dc2dffef6a6d616633a5f1266d7baa7e
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35759
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
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@aalugore @wilbryan
aalugore authored and wilbryan committed Mar 1, 2017
1 parent 525318b commit a9a7cdf
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Showing 10 changed files with 808 additions and 85 deletions.
41 changes: 39 additions & 2 deletions src/occ_405/amec/amec_parm.h
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Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER OnChipController Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2011,2015 */
/* Contributors Listed Below - COPYRIGHT 2011,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -69,10 +69,47 @@ typedef enum
PARM_SOFT_FMIN,
PARM_SOFT_FMAX,
PARM_TOD,
// WOF Parameters
PARM_V_CORE,
PARM_CORE_PWR_ON,
PARM_CORES_ON_PER_QUAD,
PARM_WOF_DISABLED,
PARM_VOLT_VDD_SENSE,
PARM_TEMPPROCTHERMC,
PARM_TEMPNEST,
PARM_TEMPQ,
PARM_QUAD_X_PSTATES,
PARM_IVRM_STATES,
PARM_IDC_VDD,
PARM_IDC_QUAD,
PARM_VOLTAGE_IDX,
PARM_ALL_CORES_OFF_ISO,
PARM_ALL_CACHES_ON_ISO,
PARM_QUAD_GOOD_CORES_ONLY,
PARM_QUAD_ON_CORES,
PARM_QUAD_BAD_OFF_CORES,
PARM_NEST_MULT,
PARM_CORE_MULT,
PARM_QUAD_MULT,
PARM_NEST_DELTA_TEMP,
PARM_CORE_DELTA_TEMP,
PARM_QUAD_DELTA_TEMP,
PARM_TVPD_LEAK_OFF,
PARM_TVPD_LEAK_ON,
PARM_TVPD_LEAK_CACHE,
PARM_REQ_ACTIVE_QUAD_UPDATE,
PARM_PREV_REQ_ACTIVE_QUADS,
PARM_CURR_PING_PONG_BUF,
PARM_NEXT_PING_PONG_BUF,
PARM_CURR_VFRT_MAIN_MEM_ADDR,
PARM_ACTIVE_QUADS_SRAM_ADDR,
PARM_VFRT_TBLS_MAIN_MEM_ADDR,
PARM_VFRT_TBLS_LEN,
// End WOF Parameters
AMEC_PARM_NUMBER_OF_PARAMETERS
} AMEC_PARM_ENUM;

typedef enum
typedef enum
{
AMEC_PARM_TYPE_UINT8 = 0,
AMEC_PARM_TYPE_UINT16,
Expand Down
42 changes: 41 additions & 1 deletion src/occ_405/amec/amec_parm_table.c
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Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER OnChipController Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2011,2015 */
/* Contributors Listed Below - COPYRIGHT 2011,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -138,6 +138,46 @@ amec_parm_t g_amec_parm_list[] = {
AMEC_PARM_UINT16(PARM_SOFT_FMIN,"part_soft_fmin",&g_amec_sys.part_config.part_list[0].soft_fmin),
AMEC_PARM_UINT16(PARM_SOFT_FMAX,"part_soft_fmax",&g_amec_sys.part_config.part_list[0].soft_fmax),
AMEC_PARM_RAW(PARM_TOD,"apss_tod",&G_dcom_slv_inbox_doorbell_rx.tod,8),



// Begin WOF parameters
AMEC_PARM_UINT32_ARRAY(PARM_V_CORE, "v_core_100uV", &g_amec_sys.wof.v_core_100uV, MAX_NUM_QUADS),
AMEC_PARM_UINT32(PARM_CORE_PWR_ON, "core_pwr_on", &g_amec_sys.wof.core_pwr_on),
AMEC_PARM_UINT8_ARRAY(PARM_CORES_ON_PER_QUAD, "coreson_per_quad", &g_amec_sys.wof.cores_on_per_quad, MAX_NUM_QUADS),
AMEC_PARM_UINT16(PARM_WOF_DISABLED, "wof_disabled", &g_amec_sys.wof.wof_disabled),
AMEC_PARM_UINT32(PARM_VOLT_VDD_SENSE, "volt_vdd_sense", &g_amec_sys.wof.volt_vdd_sense),
AMEC_PARM_UINT16_ARRAY(PARM_TEMPPROCTHERMC, "tempprocthrmc", &g_amec_sys.wof.tempprocthrmc, MAX_NUM_CORES),
AMEC_PARM_UINT16(PARM_TEMPNEST, "tempnest_sense", &g_amec_sys.wof.tempnest_sense),
AMEC_PARM_UINT16_ARRAY(PARM_TEMPQ, "tempq", &g_amec_sys.wof.tempq, MAX_NUM_QUADS),
AMEC_PARM_UINT8_ARRAY(PARM_QUAD_X_PSTATES, "quad_x_pstates", &g_amec_sys.wof.quad_x_pstates, MAX_NUM_QUADS),
AMEC_PARM_UINT8(PARM_IVRM_STATES, "quad_ivrm_states", &g_amec_sys.wof.quad_ivrm_states),
AMEC_PARM_UINT32(PARM_IDC_VDD, "idc_vdd", &g_amec_sys.wof.idc_vdd),
AMEC_PARM_UINT32(PARM_IDC_QUAD, "idc_quad", &g_amec_sys.wof.idc_quad),
AMEC_PARM_UINT8(PARM_VOLTAGE_IDX, "voltage_idx", &g_amec_sys.wof.voltage_idx),
AMEC_PARM_UINT32(PARM_ALL_CORES_OFF_ISO, "allcores_off_iso", &g_amec_sys.wof.all_cores_off_iso),
AMEC_PARM_UINT32(PARM_ALL_CACHES_ON_ISO, "allcaches_on_iso", &g_amec_sys.wof.all_caches_on_iso),
AMEC_PARM_UINT16_ARRAY(PARM_QUAD_GOOD_CORES_ONLY, "quad_good_cores", &g_amec_sys.wof.quad_good_cores_only, MAX_NUM_QUADS),
AMEC_PARM_UINT16_ARRAY(PARM_QUAD_ON_CORES, "quad_on_cores", &g_amec_sys.wof.quad_on_cores, MAX_NUM_QUADS),
AMEC_PARM_UINT16_ARRAY(PARM_QUAD_BAD_OFF_CORES,"quadBadOffCores", &g_amec_sys.wof.quad_on_cores, MAX_NUM_QUADS),
AMEC_PARM_UINT32(PARM_NEST_MULT, "nest_mult", &g_amec_sys.wof.nest_mult),
AMEC_PARM_UINT32_ARRAY(PARM_CORE_MULT, "core_mult", &g_amec_sys.wof.core_mult, MAX_NUM_CORES),
AMEC_PARM_UINT32_ARRAY(PARM_QUAD_MULT, "quad_mult", &g_amec_sys.wof.quad_mult, MAX_NUM_QUADS),
AMEC_PARM_INT16(PARM_NEST_DELTA_TEMP, "nest_delta_temp", &g_amec_sys.wof.nest_delta_temp),
AMEC_PARM_INT16_ARRAY(PARM_CORE_DELTA_TEMP, "core_delta_temp", &g_amec_sys.wof.core_delta_temp, MAX_NUM_CORES),
AMEC_PARM_INT16_ARRAY(PARM_QUAD_DELTA_TEMP, "quad_delta_temp", &g_amec_sys.wof.quad_delta_temp, MAX_NUM_CORES),
AMEC_PARM_UINT16(PARM_TVPD_LEAK_OFF, "tvpd_leak_off", &g_amec_sys.wof.tvpd_leak_off),
AMEC_PARM_UINT16(PARM_TVPD_LEAK_ON, "tvpd_leak_on", &g_amec_sys.wof.tvpd_leak_on),
AMEC_PARM_UINT16(PARM_TVPD_LEAK_CACHE, "tvpd_leak_cache", &g_amec_sys.wof.tvpd_leak_cache),
AMEC_PARM_UINT8(PARM_REQ_ACTIVE_QUAD_UPDATE, "req_active_quad", &g_amec_sys.wof.req_active_quad_update),
AMEC_PARM_UINT8(PARM_PREV_REQ_ACTIVE_QUADS, "prevActiveQuads", &g_amec_sys.wof.prev_req_active_quads),
AMEC_PARM_UINT32(PARM_CURR_PING_PONG_BUF, "currPingPongBuf", &g_amec_sys.wof.curr_ping_pong_buf),
AMEC_PARM_UINT32(PARM_NEXT_PING_PONG_BUF, "nextPingPongBuf", &g_amec_sys.wof.next_ping_pong_buf),
AMEC_PARM_UINT32(PARM_CURR_VFRT_MAIN_MEM_ADDR, "vfrtMainMemAddr", &g_amec_sys.wof.curr_vfrt_main_mem_addr),
AMEC_PARM_UINT32(PARM_ACTIVE_QUADS_SRAM_ADDR, "activQuadSramPtr", &g_amec_sys.wof.active_quads_sram_addr),
AMEC_PARM_UINT32(PARM_VFRT_TBLS_MAIN_MEM_ADDR, "vfrtMainMemAddr", &g_amec_sys.wof.vfrt_tbls_main_mem_addr),
AMEC_PARM_UINT32(PARM_VFRT_TBLS_LEN, "vfrt_tbls_len", &g_amec_sys.wof.vfrt_tbls_len),
// End WOF parameters
};

//Throw a compiler error when the enum and array are not both updated
Expand Down
12 changes: 10 additions & 2 deletions src/occ_405/cmdh/cmdh_fsp_cmds_datacnfg.c
View file
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER OnChipController Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2011,2016 */
/* Contributors Listed Below - COPYRIGHT 2011,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -44,6 +44,7 @@
#include "memory.h"
#include <avsbus.h>
#include "p9_pstates_occ.h"
#include <wof.h>

#define FREQ_FORMAT_PWR_MODE_NUM 6
#define FREQ_FORMAT_BASE_DATA_SZ (sizeof(cmdh_store_mode_freqs_t) - sizeof(cmdh_fsp_cmd_header_t))
Expand Down Expand Up @@ -1094,14 +1095,21 @@ errlHndl_t data_store_avsbus_config(const cmdh_fsp_cmd_t * i_cmd_ptr,
l_invalid_data = TRUE;
}

if (l_invalid_data)
if (l_invalid_data || !G_avsbus_vdd_monitoring || !G_avsbus_vdn_monitoring)
{
cmdh_build_errl_rsp(i_cmd_ptr, o_rsp_ptr, ERRL_RC_INVALID_DATA, &l_err);
G_avsbus_vdd_monitoring = FALSE;
G_avsbus_vdn_monitoring = FALSE;

// If cannot use vdd/vdn, cannot run wof algorithm.
g_amec->wof.wof_disabled |= WOF_RC_NO_VDD_VDN_READ_MASK;

}
else
{
// We can use vdd/vdn. Clear NO_VDD_VDN_READ mask
g_amec->wof.wof_disabled &= ~WOF_RC_NO_VDD_VDN_READ_MASK;

avsbus_init();
}

Expand Down
37 changes: 20 additions & 17 deletions src/occ_405/main.c
View file
Expand Up @@ -79,10 +79,6 @@ extern uint32_t G_pgpe_beacon_address;

extern uint32_t G_proc_fmin_khz;
extern uint32_t G_proc_fmax_khz;
extern uint32_t G_wof_active_quads_sram_addr;
extern uint32_t G_wof_tables_main_mem_addr;
extern uint32_t G_wof_tables_len;
extern bool G_run_wof_main;
extern wof_header_data_t G_wof_header;

extern uint32_t G_khz_per_pstate;
Expand All @@ -93,8 +89,10 @@ extern uint8_t G_proc_pmax;
IMAGE_HEADER (G_mainAppImageHdr,__ssx_boot,MAIN_APP_ID,ID_NUM_INVALID);

// PGPE Image Header Parameters
uint32_t G_pgpe_shared_sram_address = 0;
uint32_t G_pgpe_shared_sram_sz = 0;
uint32_t G_pgpe_shared_sram_address;
uint32_t G_pgpe_shared_sram_sz;
uint32_t G_pgpe_pstate_table_address;
uint32_t G_pgpe_pstate_table_sz;

ppmr_header_t G_ppmr_header; // PPMR Header layout format
OCCPstateParmBlock G_oppb; // OCC Pstate Parameters Block Structure
Expand Down Expand Up @@ -513,9 +511,9 @@ void read_wof_header(void)
// 128 byte aligned buffer to read the data
temp_bce_request_buffer_t l_temp_bce_buff = {{0}};

uint32_t pad = G_wof_tables_main_mem_addr%128;
uint32_t pad = g_amec->wof.vfrt_tbls_main_mem_addr%128;
// Force WOF tables address is on 128 byte boundary
uint32_t wof_main_mem_addr_128 = G_wof_tables_main_mem_addr - pad;
uint32_t wof_main_mem_addr_128 = g_amec->wof.vfrt_tbls_main_mem_addr - pad;
// Create request
l_ssxrc = bce_request_create(&l_wof_header_req, // block copy object
&G_pba_bcde_queue, // main to sram copy engine
Expand Down Expand Up @@ -581,6 +579,7 @@ void read_wof_header(void)
* @moduleid READ_WOF_HEADER
* @reasoncode INVALID_ACTIVE_QUAD_COUNT
* @userdata1 Reported active quad count
* @userdata4 Quad count failure
* @devdesc Read an invalid number of active quads
*/
l_reasonCode = INVALID_ACTIVE_QUAD_COUNT;
Expand All @@ -604,7 +603,7 @@ void read_wof_header(void)
commitErrl(&l_errl);

// We were unable to get the active quad count. Do not run wof algo.
G_run_wof_main = false;
g_amec->wof.wof_disabled |= WOF_RC_INVALID_ACTIVE_QUADS_MASK;
}


Expand Down Expand Up @@ -632,8 +631,7 @@ void read_wof_header(void)
commitErrl(&l_errl);

// We were unable to get the WOF header thus it should not be run.
G_run_wof_main = false;

g_amec->wof.wof_disabled |= WOF_RC_NO_WOF_HEADER_MASK;
return;

}
Expand Down Expand Up @@ -700,15 +698,15 @@ void read_pgpe_header(void)
G_pgpe_beacon_address);

// Read active quads address, wof tables address, and wof tables len
G_wof_active_quads_sram_addr = in32(PGPE_ACTIVE_QUAD_ADDR_PTR);
G_wof_tables_main_mem_addr = in32(PGPE_WOF_TBLS_ADDR_PTR);
G_wof_tables_len = in32(PGPE_WOF_TBLS_LEN_PTR);
g_amec->wof.active_quads_sram_addr = in32(PGPE_ACTIVE_QUAD_ADDR_PTR);
g_amec->wof.vfrt_tbls_main_mem_addr = in32(PGPE_WOF_TBLS_ADDR_PTR);
g_amec->wof.vfrt_tbls_len = in32(PGPE_WOF_TBLS_LEN_PTR);

MAIN_TRAC_IMP("Read WOF Tables Main Memory Address[0x%08x], Len[0x%08x],"
" Active Quads Address[0x%08x]",
G_wof_tables_main_mem_addr,
G_wof_tables_len,
G_wof_active_quads_sram_addr );
g_amec->wof.vfrt_tbls_main_mem_addr,
g_amec->wof.vfrt_tbls_len,
g_amec->wof.active_quads_sram_addr );

// Extract important WOF data into global space
read_wof_header();
Expand All @@ -720,6 +718,11 @@ void read_pgpe_header(void)
MAIN_TRAC_IMP("Read PGPE Shared SRAM Start Address[0x%08x], Size[0x%08x]",
G_pgpe_shared_sram_address, G_pgpe_shared_sram_sz);

// Read OCC Pstate table address and size
G_pgpe_pstate_table_address = in32(PGPE_PSTATE_TBL_ADDR_PTR);
G_pgpe_pstate_table_sz = in32(PGPE_PSTATE_TBL_SZ_PTR);


// PGPE Beacon is not implemented in simics yet
// the G_pgpe_shared_sram_address and G_pgpe_shared_sram_sz pointers don't
// have the proper values yet.
Expand Down
1 change: 1 addition & 0 deletions src/occ_405/occ_service_codes.h
View file
Expand Up @@ -122,6 +122,7 @@ enum occReasonCode
GPE_REQUEST_TASK_TIMEOUT = 0xD6,
GPE_REQUEST_RC_FAILURE = 0xD7,

WOF_VFRT_REQ_FAILURE = 0xD8,
INVALID_MAGIC_NUMBER = 0xDA,

/// Success!
Expand Down
5 changes: 3 additions & 2 deletions src/occ_405/pgpe/pgpe_interface.c
View file
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER OnChipController Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2011,2016 */
/* Contributors Listed Below - COPYRIGHT 2011,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -36,6 +36,7 @@
#include "proc_data_control.h"
#include "occ_sys_config.h"
#include "ssx.h"
#include "wof.h"

extern opal_static_table_t G_opal_static_table;

Expand Down Expand Up @@ -374,7 +375,7 @@ errlHndl_t pgpe_init_wof_vfrt(void)
IPC_MSGID_405_WOF_VFRT, // Function ID
&G_wof_vfrt_parms, // Task parameters
SSX_WAIT_FOREVER, // Timeout (none)
NULL, // Callback
(AsyncRequestCallback)switch_ping_pong_buffer, // Callback
NULL, // Callback arguments
ASYNC_CALLBACK_IMMEDIATE); // Options

Expand Down
8 changes: 7 additions & 1 deletion src/occ_405/pgpe/pgpe_shared.h
View file
Expand Up @@ -31,6 +31,8 @@
// Offset addresses of PGPE Header parameters (relative to start address)
#define PGPE_SHARED_SRAM_ADDR_OFFSET 0x0c
#define PGPE_SHARED_SRAM_SZ_OFFSET 0x14
#define PGPE_PSTATE_TBL_ADDR_OFFSET 0x40
#define PGPE_PSTATE_TBL_SZ_OFFSET 0x44
#define PGPE_BEACON_ADDR_OFFSET 0x48
#define PGPE_ACTIVE_QUAD_ADDR_OFFSET 0x4c
#define PGPE_WOF_TBLS_ADDR_OFFSET 0x50
Expand All @@ -53,7 +55,11 @@
#define PGPE_WOF_TBLS_ADDR_PTR (PGPE_HEADER_ADDR + PGPE_WOF_TBLS_ADDR_OFFSET)
#define PGPE_WOF_TBLS_LEN_PTR (PGPE_HEADER_ADDR + PGPE_WOF_TBLS_LEN_OFFSET)

// PMMR (Pstates PM region) in HOMMR
// Pointers to Pstate tables in SRAM
#define PGPE_PSTATE_TBL_ADDR_PTR (PGPE_HEADER_ADDR + PGPE_PSTATE_TBL_ADDR_OFFSET)
#define PGPE_PSTATE_TBL_SZ_PTR (PGPE_HEADER_ADDR + PGPE_PSTATE_TBL_SZ_OFFSET)

// PPMR (Pstates PM region) in HOMMR
#define PPMR_OPPM_ADDR_OFFSET 0x40 //offset of the OCC Pstates Parameter Block address in the PPMR header
#define PPMR_OPPM_SZ_OFFSET 0x44 //offset of the OCC Pstates Parameter Block size in the PPMR header

Expand Down

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