chip_ec_attributes.xml

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<!-- $Source: src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml $ -->
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<!-- OpenPOWER sbe Project                                                  -->
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<!-- [+] International Business Machines Corp.                              -->
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<!-- IBM_PROLOG_END_TAG                                                     -->
<!--
    XML file specifying HWPF attributes.
    These are example Chip EC Feature attributes that specify chip features
    based on the EC level of a chip
-->

<attributes>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_P9_NO_NDL_IOVALID</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Returns true if the chip has no NDL IOValid bits
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_EARLYMODE_FIX</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Returns true if MPW2 bits should be set
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_CORE_TRACE_NOT_SCOMABLE</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Returns true if the core trace arrays are not dumpable via SCOM.
      Nimbus EC 0x10
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_TEST1</id>
    <targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_MEMBUF_CHIP</targetType>
    <description>
      Returns if a chip contains the TEST1 feature. True if either:
      Centaur EC 10
      Cumulus EC greater than 30
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_CENTAUR</name>
        <ec>
          <value>0x10</value>
          <test>EQUAL</test>
        </ec>
      </chip>
      <chip>
        <name>ENUM_ATTR_NAME_CUMULUS</name>
        <ec>
          <value>0x30</value>
          <test>GREATER_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_TEST2</id>
    <targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_MEMBUF_CHIP</targetType>
    <description>
      Returns if a chip contains the TEST2 feature. True if:
      Murano EC less than 20
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_FSI_GP_SHADOWS_OVERWRITE</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      DD1 attribute for assigning flushvalues to root_ctrl and perv_ctrl registers. True if:
      Nimbus EC less than 20
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_N3_FLUSH_MODE</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      DD1 update : Flush mode not initiated for N3. True if:
      Nimbus EC less than 20
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_VITL_CLOCK_GATING</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      DD1 only: disable local clock gating VITAL. This is used by the
      procedure for p9_sbe_tp_chiplet_init1 and p9_Sbe_chiplet_reset.
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_SDISN_SETUP</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Sdis_n set or clear : flushing LCBES condition woraround. True if:
      Nimbus EC less than 20
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_THREAD_REBALANCING</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: Thread rebalancing to lower SMT level not supported.
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW407180</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
        Filter pll setting differences.
        Cumulus matches nimbus dd2.
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW365079</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
       DD1 only config, issue: HW365079
       Planning on enabling it with an irritator.
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW367017</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
       HW367017 P9N DD1
       Collision with scrubber correcting a CE and a castout operation, resulting in cache corruption
       Scrubbing off for DD2 as well, HW405443
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN_OR_EQUAL</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW393692</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
        HW393692 - need to turn off NCU hardware checker (fir bit 2) for illegal tlbies/slbie formats for DD1.
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW372146</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
        HW372146 For turning off clock gating on nctlbsm
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW405413</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
       HW405413 : NCU sends data out of order
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW328175</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
       HW328175 : PB mode register does not reflect steady-state value
       of PB init
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW367321</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
        HW367321 clock gating bug on err_rpt
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW254454</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
        HW254454: In P9 DD1, DRAM_ABIST_DONE_DC is unused; SRAM_ABIST_DONE_DC is shared by sram and edram
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW375534</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
        Max 24 64-byte read buffers (HW375534)
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW366248</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
        FOR P9N DD1 Prefetch Limit needs to be scan init to 0 because SCOM is broken (HW366248)
            Always OR-ed with previous value. Essentially we can only set bits, not clear. So we want to scan init to 0.
            these are n1 n3
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW395756</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW395756
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW396288</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW396288 - Dispatch Serialize all mtmsrd
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW394497</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW394497 - Turn all mtfpscr/mffspcr ops Dispatch Serialize to enable speculative FPSCR. (HW374002)
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW394447_HW394186</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW394447 / HW394186
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW393129</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW393129
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW393318</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW393318 - Turn all decimal quad ops Dispatch Serialize.
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW393547</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW393547
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW393929_HW394578</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW393929 / HW394578
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW362088</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW362088
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW391334_HW391367</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW391334 / HW391367
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW387890</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW387890
         NOTE: should be turned back off if LSU gets stuck in a cyclical ntc_plz loop.
         This switch was added in RITB as part of a large, multiple-fix solution
         for the cycling ntc_plz with DEFAULT=OFF.
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW384613</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW384613
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW373955</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW373955
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW381889</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW381889 - Disable TM ROT mode
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW379315</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW379315 - Fix tiered hangbuster triggering ntc_plz
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW347876</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW347876 - default not correct
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_DISABLE_PAGE_WALK_CACHE_HITS</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW373955 - In Radix Mode: Page Walk Cache unsupported
                       HW361596 / HW371500 / HW373955 - In SDR1 mode and UPRT=1 mode:
                                  Disable Page Walk Cache hits
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_RFC02491</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: DD1 Defer -ldmx not supported (i.e. Garbage Collection RFC02491)
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW359913_HW356752</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW359913 / HW356752
                       ltptr not supported - will be treated as an illegal instruction
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW364229</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW364229 - enb_reduce_spec mode, causes a tlbie hang
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW330187</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW330187 - Instruction Fusion not supported
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW371453</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW371453
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW379562</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW379562 - Turn off store-forward to LQ
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW376310</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW376310 - Disable forcing TM loads to miss the DDIR1
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW371047</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW371047 - TMDIR disabled due to multi-threaded issue.
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW373589</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW373589 - Reject 2nd of lqarx pair ops if they are on back-to-back cycles.
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW373167</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW373167 - Problems with arbitrating between NTC and NTC+1 flush requests when one is
                       recoverable and the other involves trechkpt.
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW372808</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW372808 - TM hwsync does not wait on load
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW372208</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW372208 - larx missed bad dval
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW373137</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW373137 - Stop prefetch and invalidate erat collison causing erat multihits
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW371867</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW371867 - Performance enhancement that is too buggy to leave enabled
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW368478</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW368478 - S2Q clock gate has to be disabled
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW360131</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW360131 - POR value is an invalid combination and is not represented in the dial.
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW370085</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW370085 - IFU can send an erroneous 2nd "force miss" to the LSU on a shared translation,
                       causing an unnecessary table walk.
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW369677</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW369677 - Dynamic set delete not implemented
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW367863</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW367863 - Workaround when EAT thinks it's empty and IDU still reports that it's out
                       of itags.
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW365384</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW365384 - data prefetch clock gate needed
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW365576</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW365576 - Need to disable reset of LRQ deallocate bit
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW365510</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW365510 - TM merging in the LRQ not supported - disable with chicken switch
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_DISABLE_SPEC_STWCX</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW353069 / HW358383 / HW358418 / HW358662 / HW358824 / HW363605
                       Not doing Performance: MB State - Need to disable speculative stwcx
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW363926</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW363926 - Workaround for clockgating bug for Local Very Good Mode (performance)
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW339090_HW354135</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW339090 / HW354135 - Branch flush performance
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW361821</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW361821 - Icache way prediction must be disabled for all SMT modes except SMT1
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW380199</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW380199 - L2 store reordering induced consistency bug
                       Only set at safest risk level
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW396388</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW396388 - Disable recovery by default
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW399524</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW399524 disable functionality, can only be enabled on non-FP/VMX tests
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_SRAM_RELAXED_SETTINGS</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: adjust/relax SRAM timing parameters
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW369979</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW369979; Defer to DD2: [GRUB multi chiplet] l3_fir_reg_l3_hw_control_err L3 FIR bit 24 (mask control_err(2) by setting dial: err_rpt0_mask(2) to ON)
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW378093</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW378093; Defer to DD2: edram_info_capture_cfg defaults to wrong value
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW288205_HW392168</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW288205 (P8 CQ) : L3 PF Hang fix. Change behavior of L3 Prefetch Back-off mechanism
                       HW392168 (P9 CQ) : This bug existed in P8 and was set to 0x4. The bug was not fixed
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW406803</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: HW406803 : bug with calculating home region for LCO's using wrong bit44
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW392009</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: Enable work around for HW392009
      Auto Special Wakeup Disables [LMCR(12:13)]. Do not scan flush to 1s.
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW377094</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      DD1 only: HW377094 L2 stq and ncu stq deadlock. g/ord_g causes artificial dependency between barrier and snptlbcmp in NCU
                while lfsr bits being reused in L2 stq causes entry to never be selected due to high priority ld-hit-st override.
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW398015</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      DD1 only: HW398015 work around
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW396393</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      DD1 only: HW396393 rare TM fail condition.
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW374111</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      DD1 only: HW374111 snapshot doesn't work for domestic copy that hits the L2 cache. all 16 RC machines need to turn off clock gating
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW373819</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      DD1 only: HW373819 PEC SBCE could cause coherency problems when running in conjunction with copy/paste
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW371141_HW371628</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      DD1 only: HW371141 lvext causes unforseen cgc lockouts, bad for performance
                HW371628 coherency hole in LVEXT also found must turn off LVEXT.
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW370687</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      DD1 only: HW370687 xlate_addr_to_id clock gating bug
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW370692</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      DD1 only: HW370692 deadlock allowing snptlbcmp to pass around stcxf
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW394803</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      DD1 only: HW394803 - Fatal Venus: Critical section fail
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW370984</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      DD1 only: HW370984 - No wakeup from hypdbell to core 1 stopped in level 2 ESL=0 (SMT1 test)
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW376874</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      DD1 only: HW376874
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW319315</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      DD1 only: mask TFAC parity errors (HW319315)
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW385178</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      DD1 only: enable workarounds for HW385178 - Force SMT4 mode for Stop 1 and 2 SPR loss
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW393734</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      DD1 only: enable workarounds for HW393734 - Stop2 hang workaround
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW396520</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      DD1 only: enable workarounds for HW396520 (skip flushmode inhibit drop)
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW388878</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      DD1 only: enable workarounds for HW388878 (VCS)
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW376651</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: enable workarounds for HW376651
      Masks ahash parity error checker to avoid FiR when running EX1 only configs
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW389511</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      DD1 only: enable workarounds for HW389511 (PPM Reg collision)
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW386013</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: enable workarounds for HW386013 in FBC initfile
      pb_cfg_cent_opt3_mode must be configured as an smp to allow vas data
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW407123</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1,DD2: enable workarounds for HW407123 in FBC initfile
      Slow down xlink cmd rate to work around broken single link credit dial
      that would have prevented rcmd overflows
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN_OR_EQUAL</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_NMMU_NDD1</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Configure NMMU for Nimbus DD1
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_NMMU_PWC_DIS_DD2</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      PWC disable for DD2
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN_OR_EQUAL</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
    <attribute>
    <id>ATTR_CHIP_EC_FEATURE_NMMU_PDE_EN_DD2</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Enabling PDE fix for dd2 only, not needed going forward
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>EQUAL</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
    <attribute>
    <id>ATTR_CHIP_EC_FEATURE_NMMU_NOT_ISS734</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      NMMU does not require application of issue734 fixes
      Issue734 exists on Nimbus dd2.1+
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x21</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW378025</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: enable workarounds for HW378025 in INT initfile
      Shared credits in ATX can only be updated when clockgate is disabled
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW930007</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: enable workarounds for HW930007 in INT initfile
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW372116</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: enable workarounds for HW372116 in INT initfile
      Remote Ld credit in PC should be set to zero to avoid ATX dropped commands
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW395947</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: enable workarounds for HW395947 in INT initfile
      Workaround for relaxed write ordering causing SBT entry corruption
  </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW408972</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1,DD2: enable workarounds for HW408972 in INT initfile
      Workaround for missing escalation bug with group interrupts
  </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN_OR_EQUAL</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW397255</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: enable workaround for HW395947
      Disable cross-chip MC sync propogation
  </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_PSI_HALF_SPEED</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: enable half speed PSI link operation due to relaxed
      chip timing closure
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_LPC_RESET_GPIO</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      DD1 only: to do an LPC reset set the GPIO bits
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_PCIE_LOCK_PHASE_ROTATOR</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      DD1.00 only: lock phase rotator
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_PCIE_DISABLE_FDDC</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      DD1.01/DD1.02 only: disable DDC
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW393297</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      DD1 only: run XBUS at reduced frequency (14.4 instead of 16) to
                based on HW393297
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_SLOW_PCI_REF_CLOCK_ENABLE</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      DD1 only: enable use of SS PLL to provide reduced frequency reference clock
                (94 MHz, instead of nominal 100 MHz) for PCI PLL
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_SW387041</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      DD1 only: restrict NVLINK frequency to 20gbs
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW396230</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: set L3/NCU skip group scope via scan only
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW405880_LCO_IN_RETENTION</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1;  set to 0b000
      Numbus DD2+; set to 0b110
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW386657</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: set the optimal dial setups for LCO's via scan
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_DISABLE_CP_ME</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Disable cp_me from the L3 for Nimbus DD1 and DD2.0
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN_OR_EQUAL</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_UNTUNED_LARX_STCX_PERF</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1: Larx/stcx dials are non performance tuned
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_NOT_HW409069</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD2+: HW409069 load_larx protection not activated because of dtag_data_resp
      in hot lock load loop pvp test
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW383616</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: enable workaround for HW383616
      Restrict GP/SP high water mark
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW384245</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: enable workaround for HW384245
      Restrict TL DOB limit
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW388874</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: n3_br_fure is non-scannable
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW401184</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1: Silent Baron: TB and DEC SPRs stray apart with TOD enabled
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW401249</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1: mask EC local error from CC
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW397147</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1: Tired Grandpa -- CHKSW_DONT_PRIORITIZE_BRQ_MF
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW399388</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1: Intense Skunk -- CS_LOW_POWER_PRIORITY_MODE_DIS
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW399609</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1: Rich Starlight -- increase core hang limit to engage L2
                  random block gather LFSR
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW387254</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1: IMA interval timer overcounts based on missing edge detect
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW399919</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1: Major Queen
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW401811</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1: Silly Plutonium
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW400898</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1: Hungry Shark
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW398269</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1: Reckless Carpenter
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW399765</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1: NCU AMO load ordering error
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW363780</id>>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1: NPU incorrectly asserts FIR for any rcmd snoops that
      misses its table lookup, includes commands that it does not master
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW403465</id>>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1: L1 access latency increases when data footprint should still
                  be within L1 cache size. Revert L1 LRU changes
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW402145</id>>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1: Husky Dinosaur
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW393578</id>>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1: Red Snow
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW403075</id>>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1: Icy Sapphire
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW399624</id>>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1: Needy Kitten
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW405851</id>>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1: Distant Supernova
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW395939</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      For DD1, VAS has no BAR disable bit.  Adding attribute to enable non zero
      init for the MMIO BARs. Issue HW395939
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_P9N_NX_DD1</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Returns true if dd1.
      Less than Nimbus ec 0x20
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW403701</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1: Reduce rng pace from 2000->300 to work around grant unfairness
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW406130</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
        Nimbus DD1: Reduce number of active DMA read requests down from 16->8
        to work around erat access count bug
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW401552</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
        Nimbus DD1: Workaround clockgating bug with APC machines missing deassert
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW403585</id>>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1: Treacherous Dolphin
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW402019_PIBRESET_DELAY</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: Adding delay to wait for
      pibreset to complete
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_NDD1_ABIST_PARALLEL</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1: set ABIST engines to PARALLEL mode.
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_SETUP_BARS_NPU_DD1_ADDR</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      DD1 only: Use the DD1 register addresses for the PHY0 BAR registers, PHY1 BAR registers, and MMIO BAR registers
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_SKEWADJ_P9NDD1_INIT</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Inits for skewAdj in P9 ndd1. These are different from the default inits used starting in NDD2.
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_DCADJ_P9NDD1_INIT</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Inits for dutyCycleAdj in P9 ndd1. These are different from the default inits used starting in NDD2.
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW397129</id>>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Attribute for if we need a workaround for re-enabling the MC fastpath since on
      Nimbus DD1 is gets disabled.
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_MSS_HW392781_RDARRAY_CLKGATE</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Data integrity issue requires us to disable clockgate in read array for Nimbus DD1.0
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW400075</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Addresses issue where MDI bit was getting wrong values with threadmill and transactional data resulting in coherency issues.
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW398139</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Avoid powerbus early hangs by enabling prefetch drops to break out of fairness issue with prefetch ops
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW400932</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      ATAG info corruption on presp issue requires us to disable clockgate for Nimbus DD1.0
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW401780</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Need AMO caching disabled for multiple defects until Nimbus DD2.0
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW406577</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Noise window disabled in DD1 because continually reocurring intermittent UE's can cause us to hang on refreshes.
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW391162</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: spoof pb_init in cache contained mode
      Enables L2 checkers to monitor for transactions arbitrating
      to broadcast onto the fabric
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_SCAN_SICR_TLBIE_QUIESCE</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 only: scan ON NCU_TLBIE_QUISCE fence
      for non-cache contained modes.  Flush state corrected in HW
      for future revisions
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_CXA_P9NDD1_SPY_NAMES</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Use Nimbus DD1 CXA spy register definition names
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_DDRPHY_P9NDD1_SPY_NAMES</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Use Nimbus DD1 DDR PHY spy register definition names
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_MCA_P9NDD1_ASYNC</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Program MCA ECC logic to support Nimbus DD1
      asynchronus boundary crossing requirements
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_CORE_P9NDD1</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1 core spy behavior qualifier
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <!-- ******************************************************************** -->
  <!-- Memory Section                                                       -->
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_MCBIST_END_OF_RANK</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      MCBIST has a bug where it won't detect the end of a rank properly for
      a 1R DIMM during super-fast read.
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_MSS_WAT_DEBUG_ATTN</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      WAT Debug Attention work-around for Nimbus DD1.0
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_MSS_UT_EC_NIMBUS_LESS_THAN_TWO_OH</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Attribute used only for memory subsystem unit tests. Tells us whether
      the chip EC we're running on is less than 2.0 and we're on a Nimbus
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_MSS_WR_VREF</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      In DD1 Nimbus in the WR VREF algorithm, certain work-arounds are needed
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_DCD_WORKAROUND</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      In DD1 Nimbus, the sofware DCD calibration needs to be run, as it does not exist in HW
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_MSS_DQS_POLARITY</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      For Monza DDR port 2, one pair of DQS P/N is swapped polarity.
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_MSS_VREF_DAC</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      VREF DAC work-around for Nimbus DD1.0
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_MSS_TRAINING_BAD_BITS</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      For Nimbus pre DD1.02 we want to pass DDR training if we see 'correctable'
      errors. This isn't the case for post-DD1.02 where we want to pass/fail
      training based on the results from the PHY itself
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_MSS_CHECK_DISABLE_HW_VREF_CAL</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      In below DD2 Nimbus, the HW VREF calibration needs to be checked against the chip subversion to see if it can be run.
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_MSS_RUN_RD_CTR_WORKAROUND</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      In below DD2 Nimbus, a workaround after read centering might need to be run.
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_MSS_ODT_CONFIG</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      For Nimbus pre DD2.** we need to swap ODT2 and ODT3 values in the
      DDRPHY_SEQ_ODT_RD/WR_CONFIG registers due to a PHY erratum.
      Post DD2.** will have a hardware enabled fix for this (HW389360).
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_MSS_BLUE_WATERFALL_ADJUST</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      In DD1.** Nimbus, the blue waterfall can calibrate to an incorrect value. In DD2 Nimbus,
      This isn't the case as the HW will not allow this calibration value
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_MSS_CHECK_DIABLE_RD_VREF_CAL_VREFSENSE</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      In below DD2 Nimbus, the RD VREF cal VREF sense needs to be checked against the chip subversion to see if it should be run.
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_MSS_DLL_WORKAROUND</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Run DLL workaround algorithm to fix bad voltage settings pre DD2.0
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_MSS_RUN_DQS_LOOP</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
        In DD1.** Nimbus, if we get a DQS fail from DQS_ALIGN in draminit_training,
        we rerun DQS_ALIGN for the failing bit for a set number of times or until it passed
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <!-- ******************************************************************** -->
  <!-- End Memory Section                                                   -->
  <!-- ******************************************************************** -->

  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW384794</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Workaround for defect where clock enables to PHY were incorrectly driven
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW375732</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Workaround for Data mismatch discovered by Geyzer at certain async frequency ratios
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW411339</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Workaround for supporting memory to nest frequency ratios greater than 1.33
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_RNG_ADAPTEST_SETTINGS</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      The Random number generator has different settings in dd1 and dd2
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW389045</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Nimbus DD1: Update the TSEL shadow copy by scanning as it't not connected to the SCOM reg.
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW401131</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Since amo cache clean line disabled for dd2, fix for HW401131 must also be disabled.
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>GREATER_THAN_OR_EQUAL</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_RING_SAVE_MPIPL</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      For Nimbus DD2 we no longer need a workaround for Ring Save in MPIPL
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW404176_ASSERT_SCAN_CLK</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Cumulus only: MC chiplet requires scan clock in even cycle instead of odd
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_CUMULUS</name>
        <ec>
          <value>0x10</value>
          <test>GREATER_THAN_OR_EQUAL</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW406337</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Cumulus only: dropping MC chiplet fence during arrayinit
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_CUMULUS</name>
        <ec>
          <value>0x10</value>
          <test>GREATER_THAN_OR_EQUAL</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW399466</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Enable fix for HW399466 where all read data for amo smi ops is sent to rmw buffer.
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>GREATER_THAN_OR_EQUAL</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_HW355538</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Enable fix for HW355538 that enables write MDI to 1 for retry UE.
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>GREATER_THAN_OR_EQUAL</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Not workaround or defect related. Just new dials to be set that are new in memory controller for DD2.
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>GREATER_THAN_OR_EQUAL</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>

    <!-- ******************************************************************** -->
    <attribute>
    <id>ATTR_CHIP_EC_FEATURE_DD1_ANALOG</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      DD1 update : Scan init VDM and IVRM latch workarounds. True if:
      Nimbus EC less than 20
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_DD1_DPLL_SETTINGS</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      DD1 update : Scan init DPL Jump Values (SCOMMABLE in DD2). True if:
      Nimbus EC less than 20
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_INT_DD1</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Common Attribute for INT DD1 spys
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_DD1_FBC_SETTINGS</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      DD1 FBC setting differs from DD2, ex. lo_limit adjustment. True if:
      Nimbus EC less than 20
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_NIMBUS</name>
        <ec>
          <value>0x20</value>
          <test>LESS_THAN</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ******************************************************************** -->
  <attribute>
    <id>ATTR_CHIP_EC_FEATURE_P9C_SPY_ONLY</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Returns true if spy name has usage only in P9C.
      Spy Name of Cumulus
    </description>
    <chipEcFeature>
      <chip>
        <name>ENUM_ATTR_NAME_CUMULUS</name>
        <ec>
          <value>0x10</value>
          <test>GREATER_THAN_OR_EQUAL</test>
        </ec>
      </chip>
    </chipEcFeature>
  </attribute>
  <!-- ********************************************************************* -->
</attributes>