pervasive_attributes.xml

<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
<!-- This is an automatically generated prolog.                             -->
<!--                                                                        -->
<!-- $Source: src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml $ -->
<!--                                                                        -->
<!-- OpenPOWER sbe Project                                                  -->
<!--                                                                        -->
<!-- Contributors Listed Below - COPYRIGHT 2015,2017                        -->
<!-- [+] International Business Machines Corp.                              -->
<!--                                                                        -->
<!--                                                                        -->
<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
<!-- you may not use this file except in compliance with the License.       -->
<!-- You may obtain a copy of the License at                                -->
<!--                                                                        -->
<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
<!--                                                                        -->
<!-- Unless required by applicable law or agreed to in writing, software    -->
<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
<!-- implied. See the License for the specific language governing           -->
<!-- permissions and limitations under the License.                         -->
<!--                                                                        -->
<!-- IBM_PROLOG_END_TAG                                                     -->
<!-- This is an automatically generated file. -->
<!-- File: pervasive_attributes.xml. -->
<!-- XML file specifying attributes used by HW Procedures. Attributes are taken from model pervasive -->
<!--pervasive_attributes.xml-->
<attributes>

<attribute>
  <id>ATTR_CLOCK_PLL_MUX</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description>setup clock mux settings</description>
  <valueType>uint32</valueType>
  <platInit/>
  <!-- TODO: Story 155081
       Not supposed to be writeable, PPE needs to resolve this issue in
       p9_sbe_attr_setup.C -->
  <writeable/>
</attribute>

<attribute>
  <id>ATTR_CLOCK_PLL_MUX0</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description>Clock Mux#0 settings</description>
  <valueType>uint8</valueType>
  <platInit/>
</attribute>

<attribute>
  <id>ATTR_I2C_BUS_DIV_REF</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description>Ref clock I2C bus divider consumed by code running out of OTPROM</description>
  <valueType>uint16</valueType>
  <persistRuntime/>
  <platInit/>
  <writeable/>
</attribute>

<attribute>
  <id>ATTR_EQ_GARD</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description>Capturing EQ Gard value</description>
  <valueType>uint8</valueType>
  <persistRuntime/>
  <platInit/>
  <writeable/>
</attribute>

<attribute>
  <id>ATTR_EC_GARD</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description>Capturing EC Gard Value</description>
  <valueType>uint32</valueType>
  <persistRuntime/>
  <platInit/>
  <writeable/>
</attribute>

<attribute>
  <id>ATTR_ISTEP_MODE</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description>Indicates istep IPL</description>
  <valueType>uint8</valueType>
  <enum>NON_IPL = 0x0,IPL = 0x1</enum>
  <persistRuntime/>
  <platInit/>
</attribute>

<attribute>
  <id>ATTR_SBE_RUNTIME_MODE</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description>Indicates that SBE should go directly to runtime functionality</description>
  <valueType>uint8</valueType>
  <enum>FALSE = 0x0,TRUE = 0x1</enum>
  <persistRuntime/>
  <platInit/>
</attribute>

<attribute>
  <id>ATTR_IS_SP_MODE</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description>Indicates whether we are connected to FSP or not</description>
  <valueType>uint8</valueType>
  <enum>FSP_LESS = 0x0,FSP = 0x1</enum>
  <persistRuntime/>
  <platInit/>
  <writeable/>
</attribute>

<attribute>
  <id>ATTR_SBE_FFDC_ENABLE</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description>Indicates whether SBE should collect FFDC</description>
  <valueType>uint8</valueType>
  <enum>FALSE = 0x0,TRUE = 0x1</enum>
  <persistRuntime/>
  <platInit/>
</attribute>

<attribute>
  <id>ATTR_SBE_INTERNAL_FFDC_ENABLE</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description>Indicates that the SBE should send back internal FFDC on any
      chipOp failure response</description>
  <valueType>uint8</valueType>
  <enum>FALSE = 0x0,TRUE = 0x1</enum>
  <persistRuntime/>
  <platInit/>
</attribute>

<attribute>
  <id>ATTR_NEST_PLL_BUCKET</id>
  <targetType>TARGET_TYPE_SYSTEM</targetType>
  <description>Select Nest I2C and pll setting from one of the supported frequencies</description>
  <valueType>uint8</valueType>
  <persistRuntime/>
  <platInit/>
  <writeable/>
</attribute>

<attribute>
  <id>ATTR_BOOT_FREQ_MULT</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description>EQ boot frequency multiplier

  The equation for this setting is BOOT_FREQ(MHz)/(REFCLK/DPLL_DIVIDER) where
  the DPLL DIVIDER is planned for being set to 8.  The value needs to be loaded
  right justified.  The value's right most 11 bits (becoming 0:10) is written
  as bits 17:27 of PPM DPLL freq ctrl register. Bits 0:7 become DPLL.MULT_INTG(0:7)
  and bits 8:10 are DPLL.MULT_FRAC(0:2).

  As an example: 3000MHz / (133MHz/8) = 3000 / 16.667 = ~180 => 0xB4
  </description>
  <valueType>uint16</valueType>
  <persistRuntime/>
  <platInit/>
  <writeable/>
</attribute>

<attribute>
  <id>ATTR_RISK_LEVEL</id>
  <targetType>TARGET_TYPE_SYSTEM</targetType>
  <description>HWP/Init "risk level" enabled. Used by HB to pass to HB driven
      HWPs</description>
  <valueType>uint8</valueType>
  <enum>FALSE = 0x0,TRUE = 0x1</enum>
  <persistRuntime/>
  <platInit/>
  <writeable/>
</attribute>

<attribute>
  <id>ATTR_DISABLE_HBBL_VECTORS</id>
  <targetType>TARGET_TYPE_SYSTEM</targetType>
  <description>BootLoader HWP flag to not place 12K exception vectors.
  This flag is only applicable when security is disabled.</description>
  <valueType>uint8</valueType>
  <enum>FALSE = 0x0,TRUE = 0x1</enum>
  <persistRuntime/>
  <platInit/>
  <writeable/>
</attribute>

<attribute>
  <id>ATTR_BACKUP_SEEPROM_SELECT</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description>Set with Primary SEEPROM</description>
  <valueType>uint8</valueType>
  <persistRuntime/>
  <platInit/>
</attribute>

<attribute>
  <id>ATTR_BOOT_FLAGS</id>
  <targetType>TARGET_TYPE_SYSTEM</targetType>
  <description>Switch to using a flag to indicate SEEPROM side SBE</description>
  <valueType>uint32</valueType>
  <persistRuntime/>
  <platInit/>
  <writeable/>
</attribute>

<attribute>
  <id>ATTR_BOOT_FREQ_MHZ</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description>EQ boot frequency</description>
  <valueType>uint32</valueType>
  <persistRuntime/>
  <platInit/>
  <writeable/>
</attribute>

<attribute>
  <id>ATTR_BRANCH_PIBMEM_ADDR</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description></description>
  <valueType>uint8</valueType>
  <persistRuntime/>
  <platInit/>
</attribute>

<attribute>
  <id>ATTR_CHIP_REGIONS_TO_ENABLE</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description></description>
  <valueType>uint32</valueType>
</attribute>

<attribute>
  <id>ATTR_DEVICE_ID</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description></description>
  <valueType>uint8</valueType>
  <persistRuntime/>
  <platInit/>
</attribute>

<attribute>
  <id>ATTR_ECID</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description>Bits 0 to 63 of the ECID in array entry 0 and bits 64 to 127 in ECID array entry 1
  Created from running the mss_get_cen_ecid.C
  Firmware shares some code with the processor,
  so the attribute is named so they can point at a target and have common function.</description>
  <valueType>uint64</valueType>
  <writeable/>
  <odmVisable/>
  <odmChangeable/>
  <array> 2</array>
</attribute>

<attribute>
  <id>ATTR_I2C_BUS_DIV_NEST</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description>I2C Bus speed based on nest freq, ref clock</description>
  <valueType>uint8</valueType>
  <persistRuntime/>
  <platInit/>
</attribute>

<attribute>
  <id>ATTR_LEN_OF_SEEPROM_DATA</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description></description>
  <valueType>uint8</valueType>
  <persistRuntime/>
  <platInit/>
</attribute>

<attribute>
  <id>ATTR_MB_BIT_RATE_DIVISOR_PLL</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description></description>
  <valueType>uint8</valueType>
  <persistRuntime/>
  <platInit/>
</attribute>

<attribute>
  <id>ATTR_MB_BIT_RATE_DIVISOR_REFCLK</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description></description>
  <valueType>uint8</valueType>
  <persistRuntime/>
  <platInit/>
</attribute>

<attribute>
  <id>ATTR_MC_SYNC_MODE</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description>MC mesh to use Nest mesh or not</description>
  <valueType>uint8</valueType>
  <persistRuntime/>
  <writeable/>
  <initToZero/>
  <enum>IN_SYNC = 1, NOT_IN_SYNC = 0</enum>
</attribute>

<attribute>
  <id>ATTR_PG</id>
  <targetType>TARGET_TYPE_PERV</targetType>
  <description>
      Chiplet Partial good info attribute
      This should be a direct copy of the data from the PG keyword of VPD.
  </description>
  <valueType>uint16</valueType>
  <platInit/>
</attribute>

<attribute>
  <id>ATTR_PROC_PB_BNDY_DMIPLL_DATA</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description>Ring image for pb_bndy_dmipll ring creator: platform firmware notes:</description>
  <valueType>uint8</valueType>
  <persistRuntime/>
  <platInit/>
</attribute>

<attribute>
  <id>ATTR_PROC_PB_BNDY_DMIPLL_FOR_DCCAL_DATA</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description>Ring image for pb_bndy_dmipll ring for DC cal creator: platform firmware notes:</description>
  <valueType>uint8</valueType>
  <persistRuntime/>
  <platInit/>
</attribute>

<attribute>
  <id>ATTR_PROC_PERV_BNDY_PLL_DATA</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description>Ring image for perv_bndy_pll ring containing filter plls and xb_pll,nest_pll creator: platform firmware notes:</description>
  <valueType>uint8</valueType>
  <persistRuntime/>
  <platInit/>
</attribute>

<attribute>
  <id>ATTR_PROC_SBE_MASTER_CHIP</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description>Indicates if SBE on this chip is serving as hosboot drawer master</description>
  <valueType>uint8</valueType>
  <enum>FALSE = 0x0,TRUE = 0x1</enum>
  <persistRuntime/>
  <platInit/>
  <writeable/>
</attribute>

<attribute>
  <id>ATTR_SBE_SEEPROM_I2C_DEVICE_ADDRESS</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description></description>
  <valueType>uint64</valueType>
</attribute>

<attribute>
  <id>ATTR_SBE_SEEPROM_I2C_PORT</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description></description>
  <valueType>uint64</valueType>
</attribute>

<attribute>
  <id>ATTR_START_PIBMEM_ADDR</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description></description>
  <valueType>uint8</valueType>
  <persistRuntime/>
  <platInit/>
</attribute>

<attribute>
  <id>ATTR_START_SEEPROM_ADDR</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description></description>
  <valueType>uint8</valueType>
  <persistRuntime/>
  <platInit/>
</attribute>

<attribute>
  <id>ATTR_WAIT_N0</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description></description>
  <valueType>uint8</valueType>
  <persistRuntime/>
  <platInit/>
</attribute>

<attribute>
  <id>ATTR_WAIT_N1</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description></description>
  <valueType>uint8</valueType>
  <persistRuntime/>
  <platInit/>
</attribute>

<attribute>
  <id>ATTR_WAIT_N2</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description></description>
  <valueType>uint8</valueType>
  <persistRuntime/>
  <platInit/>
</attribute>

<attribute>
  <id>ATTR_WAIT_N3</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description></description>
  <valueType>uint8</valueType>
  <persistRuntime/>
  <platInit/>
</attribute>

<attribute>
  <id>ATTR_SYS_FORCE_ALL_CORES</id>
  <targetType>TARGET_TYPE_SYSTEM</targetType>
  <description>Indicate that p9_sbe_select_ex should force selection to ALL good
    EX chiplets having good cores even if only a single EX chiplet mode is executed.
  </description>
  <valueType>uint8</valueType>
  <persistRuntime/>
  <platInit/>
  <writeable/>
</attribute>

<attribute>
  <id>ATTR_MASTER_CORE</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description>Indicates the master boot core chiplet selected by p9_sbe_select_ex.
  </description>
  <valueType>uint8</valueType>
  <persistRuntime/>
  <platInit/>
  <writeable/>
</attribute>

<attribute>
  <id>ATTR_MASTER_EX</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description>Indicates the EX targert associated with the master boot core selected
    by p9_sbe_select_ex.
  </description>
  <valueType>uint8</valueType>
  <persistRuntime/>
  <platInit/>
  <writeable/>
</attribute>

<attribute>
  <id>ATTR_SECURITY_ENABLE</id>
  <targetType>TARGET_TYPE_SYSTEM</targetType>
  <description>Holds the state of Security Access Bit (SAB)</description>
  <valueType>uint8</valueType>
  <platInit/>
  <writeable/>
</attribute>

<attribute>
  <id>ATTR_SECURITY_MODE</id>
  <targetType>TARGET_TYPE_SYSTEM</targetType>
  <description>SBE context: If SBE image has ATTR_SECURITY_MODE == 0b1, leave
    SAB bit as is.  Otherwise (ATTR_SECURITY_MODE == 0b0), query mailbox scratch
    register 3 bit 6 and if set, clear the SAB bit. Non-SBE context: If
    ATTR_SECURITY_MODE == 0b1, do not attempt to clear the SAB bit via the FSI
    path.  Otherwise (ATTR_SECURITY_MODE == 0b0), attempt to clear the SAB bit
    via the FSI path.  Customer level chips will silently ignore such a request,
    whereas early lab versions may honor it for debug purposes.
  </description>
  <valueType>uint8</valueType>
  <platInit/>
  <writeable/>
  <initToZero/>
</attribute>

<attribute>
  <id>ATTR_PFET_OFF_CONTROLS</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description>To disable force pfet off control from fuse status</description>
  <valueType>uint32</valueType>
  <platInit/>
  <initToZero/>
</attribute>

<!-- TODO: Story 155081
     Not supposed to be writeable, PPE needs to resolve this issue in
     p9_sbe_attr_setup.C -->
<attribute>
    <id>ATTR_OBUS_RATIO_VALUE</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>Holds Obus ratio value
        0b00     Normal speed.
        0b01     Half speed.
    </description>
    <valueType>uint8</valueType>
    <persistRuntime/>
    <platInit/>
    <writeable/>
</attribute>

<attribute>
    <id>ATTR_PIBMEM_REPAIR0</id>
    <targetType>TARGET_TYPE_SYSTEM</targetType>
    <description>Pibmem repair attribute 0</description>
    <valueType>uint64</valueType>
    <persistRuntime/>
    <platInit/>
    <writeable/>
</attribute>

 <attribute>
     <id>ATTR_PIBMEM_REPAIR1</id>
     <targetType>TARGET_TYPE_SYSTEM</targetType>
     <description>Pibmem repair attribute 1</description>
     <valueType>uint64</valueType>
     <persistRuntime/>
     <platInit/>
     <writeable/>
</attribute>

 <attribute>
     <id>ATTR_PIBMEM_REPAIR2</id>
     <targetType>TARGET_TYPE_SYSTEM</targetType>
     <description>Pibmem repair attribute 2</description>
     <valueType>uint64</valueType>
     <persistRuntime/>
     <platInit/>
     <writeable/>
</attribute>

<attribute>
  <id>ATTR_SENSEADJ_STEP</id>
  <targetType>TARGET_TYPE_EQ</targetType>
  <description>IPL for skew adjust and duty cycle adjust</description>
  <valueType>uint8</valueType>
  <writeable/>
</attribute>

<attribute>
    <id>ATTR_CP_FILTER_BYPASS</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>To skip the locking sequence and check for lock of CP filter PLL</description>
    <valueType>uint8</valueType>
    <platInit/>
    <!-- TODO: Story 155081
         Not supposed to be writeable, PPE needs to resolve this issue in
         p9_sbe_attr_setup.C -->
    <writeable/>
</attribute>

<attribute>
    <id>ATTR_SS_FILTER_BYPASS</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>To skip the locking sequence and check for lock of SS filter PLL</description>
    <valueType>uint8</valueType>
    <platInit/>
    <!-- TODO: Story 155081
         Not supposed to be writeable, PPE needs to resolve this issue in
         p9_sbe_attr_setup.C -->
    <writeable/>
</attribute>

<attribute>
    <id>ATTR_IO_FILTER_BYPASS</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>To skip the locking sequence and check for lock of IO filter PLL</description>
    <valueType>uint8</valueType>
    <platInit/>
    <!-- TODO: Story 155081
         Not supposed to be writeable, PPE needs to resolve this issue in
         p9_sbe_attr_setup.C -->
    <writeable/>
</attribute>

<attribute>
    <id>ATTR_DPLL_BYPASS</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>Skip locking sequence and check for lock of DPLL</description>
    <valueType>uint8</valueType>
    <platInit/>
    <!-- TODO: Story 155081
         Not supposed to be writeable, PPE needs to resolve this issue in
         p9_sbe_attr_setup.C -->
    <writeable/>
</attribute>

<attribute>
    <id>ATTR_NEST_MEM_X_O_PCI_BYPASS</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>Skip the locking sequence and check for lock of NEST/MEM/XBUS/OBUS/PCI PLLs</description>
    <valueType>uint8</valueType>
    <platInit/>
    <!-- TODO: Story 155081
         Not supposed to be writeable, PPE needs to resolve this issue in
         p9_sbe_attr_setup.C -->
    <writeable/>
</attribute>

<attribute>
  <id>ATTR_TARGET_HAS_POWER</id>
  <targetType>TARGET_TYPE_PERV</targetType>
  <description>Functional Target has power</description>
  <initToZero></initToZero>
  <valueType>uint8</valueType>
  <writeable/>
  <persistRuntime/>
</attribute>

<attribute>
  <id>ATTR_TARGET_HAS_CLOCK</id>
  <targetType>TARGET_TYPE_PERV</targetType>
  <description>Functional Target has clock</description>
  <initToZero></initToZero>
  <valueType>uint8</valueType>
  <writeable/>
  <persistRuntime/>
</attribute>

<attribute>
  <id>ATTR_TARGET_IS_SCOMMABLE</id>
  <targetType>TARGET_TYPE_PERV</targetType>
  <initToZero></initToZero>
  <description>Functional Target is scommable</description>
  <valueType>uint8</valueType>
  <writeable/>
  <persistRuntime/>
</attribute>

<attribute>
  <id>ATTR_SBE_SYS_CONFIG</id>
  <targetType>TARGET_TYPE_SYSTEM</targetType>
  <description>System Configurtion information - 1 indicates a chip present</description>
  <valueType>uint64</valueType>
  <platInit/>
  <writeable/>
</attribute>

<attribute>
  <id>ATTR_CP_REFCLOCK_RCVR_TERM</id>
  <targetType>TARGET_TYPE_SYSTEM</targetType>
  <description>
      Defines system specific value of processor refclock receiver termination
  </description>
  <enum>NONE = 0, FIFTY_OHM = 1</enum>
  <valueType>uint8</valueType>
  <platInit/>
  <persistRuntime/>
</attribute>

<attribute>
  <id>ATTR_IO_REFCLOCK_RCVR_TERM</id>
  <targetType>TARGET_TYPE_SYSTEM</targetType>
  <description>
      Defines system specific value of PCI refclock receiver termination
  </description>
  <enum>NONE = 0, FIFTY_OHM = 1, ONE_HUNDRED_OHM = 3</enum>
  <valueType>uint8</valueType>
  <platInit/>
  <persistRuntime/>
</attribute>

<attribute>
  <id>ATTR_SECUREBOOT_PROTECT_DECONFIGURED_TPM</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description>To deconfigure a TPM in a secure system - 01 to set TDP bit</description>
  <valueType>uint8</valueType>
  <platInit/>
</attribute>

<attribute>
  <id>ATTR_SECTOR_BUFFER_STRENGTH</id>
  <targetType>TARGET_TYPE_SYSTEM</targetType>
  <description>Sector buffer strength</description>
  <valueType>uint8</valueType>
  <platInit/>
</attribute>

<attribute>
  <id>ATTR_PULSE_MODE_ENABLE</id>
  <targetType>TARGET_TYPE_SYSTEM</targetType>
  <description>enable the pulse mode</description>
  <valueType>uint8</valueType>
  <platInit/>
</attribute>

<attribute>
  <id>ATTR_PULSE_MODE_VALUE</id>
  <targetType>TARGET_TYPE_SYSTEM</targetType>
  <description>value for pulse mode</description>
  <valueType>uint8</valueType>
  <platInit/>
</attribute>

<attribute>
  <id>ATTR_NDL_MESHCTRL_SETUP</id>
  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
  <description>Control NDL training:meshctrl setup</description>
  <valueType>uint8</valueType>
  <persistRuntime/>
  <writeable/>
</attribute>

</attributes>