pm_plat_attributes.xml

<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
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<!-- $Source: src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml $ -->
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<!-- OpenPOWER sbe Project                                                  -->
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<!-- [+] International Business Machines Corp.                              -->
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<!-- IBM_PROLOG_END_TAG                                                     -->
<!-- pm_plat_attributes.xml -->
<!--                                                                        -->
<!-- XML file specifying Power Management HWPF attributes.                  -->
<!-- These attributes are initialized by the platform.                      -->
<attributes>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_EXTERNAL_VRM_STEPSIZE</id>
    <targetType>TARGET_TYPE_SYSTEM</targetType>
    <!-- <<<<<<< PROC_CHIP POSSIBLE -->
    <description>
      Step size (binary in microvolts) to take upon external VRM voltage
      transitions. The value set here must take into account where internal
      VRMs are enabled or not as, when they are enabled, the step size must
      account for the tracking (eg PFET strength recalculation) for the step.

      Consumer: p9_pstate_parameter_block ->
                        Pstate Parameter Block (PSPB) for PGPE

      Provided by the Machine Readable Workbook after system characterization.
    </description>
    <valueType>uint32</valueType>
    <platInit/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_EXTERNAL_VRM_STEPDELAY</id>
    <targetType>TARGET_TYPE_SYSTEM</targetType>
    <!-- <<<<<<< PROC_CHIP POSSIBLE -->
    <description>
      Step delay (binary in microseconds) after a voltage change

      Consumer: p9_pstate_parameter_block ->
                        Pstate Parameter Block (PSPB) for PGPE

      Provided by the Machine Readable Workbook after system characterization.
    </description>
    <valueType>uint32</valueType>
    <platInit/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_EXTERNAL_VRM_TRANSITION_START_NS</id>
    <targetType>TARGET_TYPE_SYSTEM</targetType>
    <description>
    Delay (binary in nanoseconds) from the time the VRM receives the write
    voltage command until the voltage actually moves.   This value is used for
    both increasing and decreasing transitions as part of the overall voltage
    transition time calculation.
    Firmware provides a default value of 8000ns (eg 8us)) if this attribute is
    zero.  Note: the smallest possible delay is limited to 1ns.

    Consumer: p9_pstate_parameter_block ->
                        Pstate Parameter Block (PSPB) for PGPE

      Provided by the Machine Readable Workbook after system characterization.
    </description>
    <valueType>uint32</valueType>
    <initToZero/>
    <platInit/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_EXTERNAL_VRM_TRANSITION_RATE_INC_UV_PER_US</id>
    <targetType>TARGET_TYPE_SYSTEM</targetType>
    <description>
    Transition rate (binary in microVolts per microsecond) of the VRM for an
    increasing voltage transition.   This is used as part of the overall voltage
    transition time calculation
    Firmware provides a default value of 10000 uV/us (eg 10mV/us) if this
    attribute is zero.  Note: the fastest possible rate is limited to 1uV/us.

    Consumer: p9_pstate_parameter_block ->
                        Pstate Parameter Block (PSPB) for PGPE

      Provided by the Machine Readable Workbook after system characterization.
    </description>
    <valueType>uint32</valueType>
    <initToZero/>
    <platInit/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_EXTERNAL_VRM_TRANSITION_RATE_DEC_UV_PER_US</id>
    <targetType>TARGET_TYPE_SYSTEM</targetType>
    <description>
    Transition rate (binary in microVolts per microsecond) of the VRM for an
    decreasing voltage transition.   This is used as part of the overall voltage
    transition time calculation
    Firmware provides a default value of 10000 uV/us (eg 10mV/us) if this
    attribute is zero. Note: the fastest possible rate is limited to 1uV/us.

    Consumer: p9_pstate_parameter_block ->
                        Pstate Parameter Block (PSPB) for PGPE

      Provided by the Machine Readable Workbook after system characterization.
    </description>
    <valueType>uint32</valueType>
    <initToZero/>
    <platInit/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_EXTERNAL_VRM_TRANSITION_STABILIZATION_TIME_NS</id>
    <targetType>TARGET_TYPE_SYSTEM</targetType>
    <description>
    Time (binary in nanoseconds) to allow the voltage rail to stabilize before
    considering the transition to be fully complete.  This value is used for
    both increasing and decreasing transitions as part of the overall voltage
    transition time calculation.
    Firmware provides a default value of 5000ns (5us) if this attribute is zero.
    Note: the smallest delay is limited to 1ns.

    Consumer: p9_pstate_parameter_block ->
                        Pstate Parameter Block (PSPB) for PGPE

      Provided by the Machine Readable Workbook after system characterization.
    </description>
    <valueType>uint32</valueType>
    <initToZero/>
    <platInit/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_AVSBUS_FREQUENCY</id>

    <targetType>TARGET_TYPE_SYSTEM</targetType>
    <!-- <<<<<<< PROC_CHIP POSSIBLE -->
    <description>
      AVSBus Clock Frequency (binary in KHz)

      Consumer: p9_ocb_init.C

      Overridden by the Machine Readable Workbook.

      If default of 0 is read, HWP will set AVSBus frequency to 1MHz.
    </description>
    <valueType>uint32</valueType>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_VDD_AVSBUS_BUSNUM</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Defines the AVSBus (0 or 1) which has the core VDD rail VRM

      Producer:  Machine Readable Workbook
      Consumers: p9_set_evid;
                 p9_set_voltage (tool);
                 p9_build_pstate_datablock ->
                        Pstate Parameter Block (PSPB) for PGPE

     *MOST* systems use Bus 0 for VDD.  If this is not the case, the value
     must be appropriately set by the platform (eg MRWB or equivalent
    </description>
    <valueType>uint8</valueType>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_VDN_AVSBUS_BUSNUM</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Defines the AVSBus (0 or 1) which has the chip VDN rail VRM

      Producer:  Machine Readable Workbook
      Consumers: p9_set_evid;
                 p9_set_voltage (tool);
                 p9_build_pstate_datablock ->
                        Pstate Parameter Block (PSPB) for PGPE

     *MOST* systems use Bus 1 for VDD.  If this is not the case, the value
     must be appropriately set by the platform (eg MRWB or equivalent)
    </description>
    <valueType>uint8</valueType>
    <platInit/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_VCS_AVSBUS_BUSNUM</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Defines the AVSBus (0 or 1) which has the chip VCS rail VRM

      Producer:  Machine Readable Workbook
      Consumers: p9_set_evid;
                 p9_set_voltage (tool);
                 p9_build_pstate_datablock ->
                        Pstate Parameter Block (PSPB) for PGPE

    For systems where VCS is not connected via AVSBus, set to 0xFF.
    </description>
    <valueType>uint8</valueType>
    <platInit/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_VDD_AVSBUS_RAIL</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
     Defines the AVSBus rail selector number (0 - 15) for the VDD VRM on the bus
     defined by ATTR_AVSBUS_VDD_BUSNUM.

      Producer:  Machine Readable Workbook
      Consumers: p9_set_evid;
                 p9_set_voltage (tool);
                 p9_build_pstate_datablock ->
                        Pstate Parameter Block (PSPB) for PGPE

     *MOST* systems use Rail 0 for VDD for the bus on which they are connected.
     If this is not the case, the value must be appropriately set by the platform
     (eg MRWB or equivalent)
    </description>
    <valueType>uint8</valueType>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_VDN_AVSBUS_RAIL</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
     Defines the AVSBus rail selector number (0 - 15) for the VDN VRM on the bus
     defined by ATTR_AVSBUS_VDN_BUSNUM.

      Producer:  Machine Readable Workbook
      Consumers:
      p9_set_avsbus_voltage (tool);
                 p9_build_pstate_datablock ->
                        Pstate Parameter Block (PSPB) for PGPE

     *MOST* systems use Rail 0 for VDN for the bus on which they are connected.
     If this is not the case, the value must be appropriately set by the platform
     (eg MRWB or equivalent)
    </description>
    <valueType>uint8</valueType>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
 <attribute>
   <id>ATTR_VCS_AVSBUS_RAIL</id>
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description>
    Defines the AVSBus rail selector number (0 - 15) for the VCS VRM on the bus
    defined by ATTR_AVSBUS_VCS_BUSNUM.

     Producer:  Machine Readable Workbook
     Consumers:
     p9_set_avsbus_voltage (tool);
            p9_build_pstate_datablock ->
               Pstate Parameter Block (PSPB) for PGPE

   </description>
   <valueType>uint8</valueType>
   <platInit/>
    <initToZero/>  <!-- This here strictly to allocate the attribute in Cronus -->
 </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_VCS_I2C_BUSNUM</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Defines the I2C bus number (0 - 15) that has the VCS VRM.

      Producer:  Machine Readable Workbook
      Consumers: p9_set_evid;
                 p9_set_voltage (tool)
    </description>
    <valueType>uint8</valueType>
    <platInit/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_VCS_I2C_RAIL</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Defines the I2C rail selector number (0 - 15) for the VCS VRM on the
      bus defined by ATTR_VCS_I2C_BUSNUM.

      Producer:  Machine Readable Workbook
      Consumers: p9_set_evid;
                 p9_set_voltage (tool)
    </description>
    <valueType>uint8</valueType>
    <platInit/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_VDD_BOOT_VOLTAGE</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Voltage (binary in 1mV units) to apply to the VDD VRM for booting.  Value
      chosen is system dependent and is a combination of the part's Vital Product
      Data (VPD) (typically the PowerSave value) and the minimum allowed for
      correct operation of the fabric bus.

      Producer: p9_setup_evid (first pass)

      Consumer: p9_setup_evid (second pass)
    </description>
    <valueType>uint32</valueType>
    <writeable/>
  </attribute>
    <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_VDN_BOOT_VOLTAGE</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Voltage (binary in 1mV units) to apply to the VDN VRM for booting.  Value
      chosen is system dependent and is a combination of the part's Vital Product
      Data (VPD) (typically the PowerSave value) and the minimum allowed for
      correct operation of the fabric bus.

      Producer: p9_setup_evid (first pass)

      Consumer: p9_setup_evid (second pass)
    </description>
    <valueType>uint32</valueType>
    <writeable/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_VCS_BOOT_VOLTAGE</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Voltage (binary in 1mV units) to apply to the VCS VRM for booting.  Value
      chosen is system dependent and is a combination of the part's Vital Product
      Data (VPD) (typically the PowerSave value) and the minimum allowed for
      correct operation of the fabric bus.

      Producer: p9_setup_evid (first pass)

      Consumer: p9_setup_evid (second pass)
    </description>
    <valueType>uint32</valueType>
    <writeable/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_SPIPSS_FREQUENCY</id>
    <targetType>TARGET_TYPE_SYSTEM</targetType>
    <description>
      SPIPSS Clock Frequency (binary in KHz)

      Valid range: 500KHz to 2500KHz

      Consumer: p9_pss_init

      Overridden by the Machine Readable Workbook.

      If default of 0 is read, HWP will set SPIPSS frequency to 10MHz.
    </description>
    <valueType>uint32</valueType>
    <platInit/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_PM_APSS_CHIP_SELECT</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Defines which of the PSS chip selects (0 or 1) that the APSS is connected

      Provided by the Machine Readable Workbook.
      Consumer: p9_pm_pss_init
    </description>
    <valueType>uint8</valueType>
    <enum>NONE = 0xFF, CS0 = 0x00, CS1 = 0x01</enum>
    <platInit/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_PROC_R_LOADLINE_VDD_UOHM</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Impedance (binary microOhms) of the load line from a processor VDD VRM to the
      Processor Module pins.  This value is applied to each processor instance.

      Producer: Machine Readable Workbook (per the power subsystem design)

      Consumers: p9_pstate_parameter_block
    </description>
    <valueType>uint32</valueType>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_PROC_R_DISTLOSS_VDD_UOHM</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Impedance (binary in microOhms) of the VDD distribution loss sense point
      to the circuit. This value is applied to each processor instance.

      Producer: Machine Readable Workbook (per the power subsystem design)

      Consumers: p9_pstate_parameter_block
    </description>
    <valueType>uint32</valueType>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_PROC_VRM_VOFFSET_VDD_UV</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Offset voltage (binary in microvolts) to apply to the VDD VRM distribution
      to the processor module.  This value is applied to each processor instance.

      Note:  no loadline may be present in the system; thus, a value of 0 is
      legal.

      Producer: Machine Readable Workbook (per the power subsystem design)

      Consumers: p9_pstate_parameter_block
    </description>
    <valueType>uint32</valueType>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_PROC_R_LOADLINE_VDN_UOHM</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Impedance (binary microOhms) of the load line from a processor VDN VRM to
      the Processor Module pins.  This value is applied to each processor
      instance.

      Note:  no loadline may be present in the system; thus, a value of 0 is
      legal.

      Producer: Machine Readable Workbook (per the power subsystem design)

      Consumers: p9_pstate_parameter_block
    </description>
    <valueType>uint32</valueType>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_PROC_R_DISTLOSS_VDN_UOHM</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Impedance (binary in microOhms) of the VDN distribution loss sense point
      to the circuit. This value is applied to each processor instance.

      Producer: Machine Readable Workbook (per the power subsystem design)

      Consumers: p9_pstate_parameter_block
    </description>
    <valueType>uint32</valueType>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_PROC_VRM_VOFFSET_VDN_UV</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Offset voltage (binary in microvolts) to apply to the VDN VRM distribution
      to the processor module.  This value is applied to each processor instance.

      Producer: Machine Readable Workbook (per the power subsystem design)

      Consumers: p9_pstate_parameter_block
    </description>
    <valueType>uint32</valueType>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_PROC_R_LOADLINE_VCS_UOHM</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Impedance (binary microOhms) of the load line from a processor VCS VRM to
      the Processor Module pins.  This value is applied to each processor
      instance.

      Note:  no loadline may be present in the system; thus, a value of 0 is
      legal.

      Producer: Machine Readable Workbook (per the power subsystem design)

      Consumers: p9_pstate_parameter_block
    </description>
    <valueType>uint32</valueType>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_PROC_R_DISTLOSS_VCS_UOHM</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Impedance (binary in microOhms) of the VCS distribution loss sense point
      to the circuit. This value is applied to each processor instance.

      Producer:  Machine Readable Workbook (via the power subsystem design per
      system)

      Consumer: p9_pstate_parameter_block
    </description>
    <valueType>uint32</valueType>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_PROC_VRM_VOFFSET_VCS_UV</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Offset voltage (binary in microvolts) to apply to the VCS VRM distribution
      to the processor module.  This value is applied to each processor instance.

      Producer:  Machine Readable Workbook (via the power subsystem design per
      system)

      Consumer: FSP
    </description>
    <valueType>uint32</valueType>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_FREQ_BIAS_ULTRATURBO</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
     UltraTurbo Frequency Bias - % of bias (signed twos complement in 0.5
     percent steps) used in calculating the frequency associated with a Pstate
     - both Global and Local.

     Producer:  Attribute Overrides by Lab/Mfg Characterization Team

     Consumer: p9_pstate_parameter_block
    </description>
    <valueType>int8</valueType>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_FREQ_BIAS_TURBO</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
     Turbo Frequency Bias - % of bias (signed twos complement in 0.5 percent
     steps) used in calculating the frequency associated with a Pstate - both
     Global and Local.

     Producer:  Attribute Overrides by Lab/Mfg Characterization Team

     Consumer: p9_pstate_parameter_block
    </description>
    <valueType>int8</valueType>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_FREQ_BIAS_NOMINAL</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
     Nominal Frequency Bias - % of bias (signed twos complement in 0.5 percent
     steps) used in calculating the frequency associated with a Pstate - both
     Global and Local.

     Producer:  Attribute Overrides by Lab/Mfg Characterization Team

     Consumer: p9_pstate_parameter_block
    </description>
    <valueType>int8</valueType>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_FREQ_BIAS_POWERSAVE</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
     PowerSave Frequency Bias - % of bias (signed twos complement in 0.5 percent
     steps) used in calculating the frequency associated with a Pstate - both
     Global and Local.

     Producer:  Attribute Overrides by Lab/Mfg Characterization Team

     Consumer: p9_pstate_parameter_block
    </description>
    <valueType>int8</valueType>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_VOLTAGE_EXT_VDD_BIAS_ULTRATURBO</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
     UltraTurbo VDD Voltage Bias - % of bias (signed twos complement in 0.5
     percent steps) that is applied to the UltraTurbo VPD point used in
     calculating the Global Pstate values.

     Producer:  Attribute Overrides by Lab/Mfg Characterization Team

     Consumer: p9_pstate_parameter_block
    </description>
    <valueType>int8</valueType>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_VOLTAGE_EXT_VDD_BIAS_TURBO</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
     Turbo VDD Voltage Bias - % of bias (signed twos complement in 0.5 percent
     steps) that is applied to the UltraTurbo VPD point used in calculating the
     Global Pstate values.

     Producer:  Attribute Overrides by Lab/Mfg Characterization Team

     Consumer: p9_pstate_parameter_block
    </description>
    <valueType>int8</valueType>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_VOLTAGE_EXT_VDD_BIAS_NOMINAL</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
     Nominal VDD Voltage Bias - % of bias (signed twos complement in 0.5 percent
     steps) that is applied to the UltraTurbo VPD point used in calculating the
     Global Pstate values.

     Producer:  Attribute Overrides by Lab/Mfg Characterization Team

     Consumer: p9_pstate_parameter_block
    </description>
    <valueType>int8</valueType>
    <platInit/>
    <initToZero/>
  </attribute>
    <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_VOLTAGE_EXT_VDD_BIAS_POWERSAVE</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
     PowerSave VDD Voltage Bias - % of bias (signed twos complement in 0.5
     percent steps) that is applied to the UltraTurbo VPD point used in
     calculating the Global Pstate values.

     Producer:  Attribute Overrides by Lab/Mfg Characterization Team

     Consumer: p9_pstate_parameter_block

    </description>
    <valueType>int8</valueType>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_VOLTAGE_EXT_VCS_BIAS</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
     VCS Voltage Bias - % of bias (signed twos complement in 0.5 percent
     steps) that is applied to the VCS value stored in the UltraTurbo VPD
     point for setting the VCS rail.

     Producer:  Attribute Overrides by Lab/Mfg Characterization Team

     Consumer: p9_pstate_parameter_block

     Platform default:  0
    </description>
    <valueType>int8</valueType>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_VOLTAGE_EXT_VDN_BIAS</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
     VDN Voltage Bias - % of bias (signed twos complement in 0.5 percent
     steps) that is applied to the VDN value stored in the VPD for setting the
     VDN rail.

     Producer:  Attribute Overrides by Lab/Mfg Characterization Team

     Consumer: p9_pstate_parameter_block

     Platform default:  0
    </description>
    <valueType>int8</valueType>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_VOLTAGE_INT_VDD_BIAS_ULTRATURBO</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
     TODO (RTC 136996) NEED TO LOOK AT PERCENTAGE IMPLEMENTATION IN CME CODE AS
     WELL AS THE IVRM VOLTAGE CALCULATION PROCESS
     UltraTurbo Internal VDD Voltage Bias - % of bias (signed twos complement in
     0.5 percent steps) that is applied to the voltage computed (Vout) as part
     of the Local Pstate.  Note: the Vin Effective that models the Vin to the
     PFETs (i.e  accounting for system parameter losses) may include biassing
     based on ATTR_VOLTAGE_VDD_BIAS_ULTRATURBO.

     Producer:  Attribute Overrides by Lab/Mfg Characterization Team

     Consumer: p9_pstate_parameter_block

     Platform default:  0
    </description>
    <valueType>int8</valueType>
    <platInit/>
    <initToZero/>
  </attribute>
    <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_VOLTAGE_INT_VDD_BIAS_TURBO</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
     TODO (RTC 136996) NEED TO LOOK AT PERCENTAGE IMPLEMENTATION IN CME CODE AS
     WELL AS THE IVRM VOLTAGE CALCULATION PROCESS
     TURBO Internal VDD Voltage Bias - % of bias (signed twos complement in 0.5
     percent steps) that is applied to the voltage computed (Vout) as part of
     the Local Pstate.  Note: the Vin Effective that models the Vin to the PFETs
     (i.e  accounting for system parameter losses) may include biassing based on
     ATTR_VOLTAGE_VDD_BIAS_TURBO.

     Producer:  Attribute Overrides by Lab/Mfg Characterization Team

     Consumer: p9_pstate_parameter_block

     Platform default:  0
    </description>
    <valueType>int8</valueType>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_VOLTAGE_INT_VDD_BIAS_NOMINAL</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
     TODO (RTC 136996) NEED TO LOOK AT PERCENTAGE IMPLEMENTATION IN CME CODE AS
     WELL AS THE IVRM VOLTAGE CALCULATION PROCESS
     Nominal Internal VDD Voltage Bias - % of bias (signed twos complement in
     0.5 percent steps) that is applied to the voltage computed (Vout) as part
     of the Local Pstate.  Note: the Vin Effective that models the Vin to the
     PFETs (i.e  accounting for system parameter losses) may include biassing
     based on ATTR_VOLTAGE_VDD_BIAS_NOMINAL.

     Producer:  Attribute Overrides by Lab/Mfg Characterization Team

     Consumer: p9_pstate_parameter_block

     Platform default:  0
    </description>
    <valueType>int8</valueType>
    <platInit/>
    <initToZero/>
  </attribute>
    <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_VOLTAGE_INT_VDD_BIAS_POWERSAVE</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
     TODO (RTC 136996) NEED TO LOOK AT PERCENTAGE IMPLEMENTATION IN CME CODE AS
     WELL AS THE IVRM VOLTAGE CALCULATION PROCESS
     PowerSave Internal VDD Voltage Bias - % of bias (signed twos complement in
     0.5 percent steps) that is applied to the voltage computed (Vout) as part of
     the Local Pstate.  Note: the Vin Effective that models the Vin to the PFETs
     (i.e  accounting for system parameter losses) may include biassing based on
     ATTR_VOLTAGE_VDD_BIAS_POWERSAVE.

     Producer:  Attribute Overrides by Lab/Mfg Characterization Team

     Consumer: p9_pstate_parameter_block

     Platform default:  0
    </description>
    <valueType>int8</valueType>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_STOP4_DISABLE</id>
    <targetType>TARGET_TYPE_SYSTEM</targetType>
    <description>Control CME response to execution of PowerPC STOP instruction

    if OFF, treat STOP4 as STOP4
    if ON, treat STOP4 as STOP2

    Producer: Work-around tools

    Consumer:  p9_hcode_image_build.C

    Platform default:  OFF
    </description>
    <valueType>uint8</valueType>
    <enum>OFF=0, ON=1</enum>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_STOP5_DISABLE</id>
    <targetType>TARGET_TYPE_SYSTEM</targetType>
    <description> Control CME response to execution of PowerPC STOP instruction
    if OFF, treat STOP5 as STOP5
    if ON,  treat STOP5 as STOP4

    Producer: ???

    Consumer:  p9_hcode_image_build.C

    Platform default: ON
    </description>
    <valueType>uint8</valueType>
    <enum>OFF=0, ON=1</enum>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_STOP8_DISABLE</id>
    <targetType>TARGET_TYPE_SYSTEM</targetType>
    <description>Control CME response to execution of PowerPC STOP instruction

    if OFF, treat STOP8 as STOP8
    if ON, treat STOP8 as STOP4

    Producer: Work-around tools

    Consumer:  p9_hcode_image_build.C

    Platform default:  OFF
    </description>
    <valueType>uint8</valueType>
    <enum>OFF=0, ON=1</enum>
    <platInit/>
    <initToZero/>
  </attribute>
    <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_STOP11_DISABLE</id>
    <targetType>TARGET_TYPE_SYSTEM</targetType>
    <description>Control CME response to execution of PowerPC STOP instruction

    if OFF, treat STOP11 as STOP11
    if ON, treat STOP11 as STOP8

    Producer: Work-around tools

    Consumer:  p9_hcode_image_build.C

    Platform default:  OFF
    </description>
    <valueType>uint8</valueType>
    <enum>OFF=0, ON=1</enum>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_SYSTEM_IVRMS_ENABLED</id>
    <targetType>TARGET_TYPE_SYSTEM</targetType>
    <description>System control to allow (if all other attribute tests yield
    true values) or categorically disallow IVRM enablement

    Producer: MRWB

    Consumers: p9_build_pstate_datablock ->
                      Pstate Parameter Block (PSPB) for PGPE/OCC
                      CME Quad Pstate Region (CQPR) for CM Quad Manager

    Platform default: FALSE
    </description>
    <valueType>uint8</valueType>
    <enum>FALSE=0, TRUE=1</enum>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_SYSTEM_WOF_ENABLED</id>
    <targetType>TARGET_TYPE_SYSTEM</targetType>
    <description>System control to allow Work Load Optimized Frequency (WOF)
    algorithms to modify frequency based on active core count and other inputs.

    Producer: MRWB

    Consumers: p9_build_pstate_datablock ->
                      Pstate Parameter Block (PSPB) for PGPE/OCC

    Platform default:   FALSE
    </description>
    <valueType>uint8</valueType>
    <enum>FALSE=0, TRUE=1</enum>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_WOF_ENABLE_FRATIO</id>
    <targetType>TARGET_TYPE_SYSTEM</targetType>
    <description>
    If wof_enabled, defines the Frequency Ratio calculation performed.
    (THIS IS NOT SUPPORTED IN P9 GA1!).
    </description>
    <valueType>uint8</valueType>
    <enum>FIXED=0, STEPPED=1</enum>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_WOF_ENABLE_VRATIO</id>
    <targetType>TARGET_TYPE_SYSTEM</targetType>
    <description>
    If wof_enabled, defines the Voltage Ratio calculation performed.
    THIS IS NOT SUPPORTED AT PRESENT. GA1 SUPPORT IS TBD).
    </description>
    <valueType>uint8</valueType>
    <enum>FIXED=0, STEPPED=1</enum>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_WOF_VRATIO_SELECT</id>
    <targetType>TARGET_TYPE_SYSTEM</targetType>
    <description>
    If wof_enabled AND ATTR_WOF_ENABLE_VRATIO = CALCULATED, this attribute
    selects the Vratio calculation type.
    ACTIVE_CORES: Vratio is the number of active cores to the
    number of good cores
    FULL: Vratio is Vaverage to Vclip(Fclip) where Vclip(Fclip) is
    the normal interpolated regulator voltage (including load line uplife @ RDP
    current) derated with presently measured Idd current (from the AVSBus) and
    the loadline.

    </description>
    <valueType>uint8</valueType>
    <enum>ACTIVE_CORES=0, FULL=1</enum>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_PBAX_GROUPID</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Receive PBAX Groupid. Value that indicates this PBA's PBAX Group affinity.
      This is matched to pbax_groupid of the PMISC Address phase.

      Provided by the Machine Readable Workbook.

      Platform default:  Nimbus systems = 0
    </description>
    <valueType>uint8</valueType>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_PBAX_CHIPID</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
      Receive PBAX Chipid. Value that indicates this PBA's PBAX Chipid within
      the PBAX node.  Is matched to pbax_chipid of the Address phase if
      pbax_type=unicast.

      Provided by the Machine Readable Workbook.

      Platform default:  Nimbus systems - set so value in ATTR_FABRIC_GROUP_ID
    </description>
    <valueType>uint8</valueType>
    <platInit/>
    <initToZero/>  <!-- This here strictly to allocate the attribute in Cronus -->
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_PBAX_BRDCST_ID_VECTOR</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
    Receive PBAX Broadcast Group. Vector that is indexed when decoded PMISC
    pbax_type=broadcast with the decoded PMISC pbax_chipid value.  If the
    bit in this vector at the decoded bit location is a 1, then this receive
    engine will participate in the broadcast operation.

    Override attribute.  Platform value of 0 indiates the OCC firmware will
    perform this function.
    </description>
    <valueType>uint8</valueType>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
     <id>ATTR_POUNDV_BUCKET_NUM_OVERRIDE</id>
    <targetType>TARGET_TYPE_EQ</targetType>
    <description>
        1 if override of poundv bucket num is available.
        0 if override is unavailable.
    </description>
    <initToZero/>
    <valueType>uint8</valueType>
    <platInit/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
      <id>ATTR_POUNDV_BUCKET_NUM</id>
      <targetType>TARGET_TYPE_EQ</targetType>
      <description>
          Attribute in place to allow override of which POUNDV
          bucket to use to set power management data.
          1 = Bucket A
          2 = Bucket B
          3 = Bucket C
          4 = Bucket D
          5 = Bucket E
          6 = Bucket F
      </description>
      <initToZero/>
      <valueType>uint8</valueType>
      <platInit/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
      <id>ATTR_POUNDV_BUCKET_DATA</id>
      <targetType>TARGET_TYPE_EQ</targetType>
      <description>
      Power Management data for Quad targets. Stored as an array of bytes.
      The data is read directly from VPD and stored in this attribute without
      being altered.

      NOTE: you may need to handle correcting endiannessif you are using this
      attribute.
      </description>
      <valueType>uint8</valueType>
      <initToZero/>
      <array>61</array>
      <platInit/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
      <id>ATTR_POUNDW_BUCKET_DATA</id>
      <targetType>TARGET_TYPE_EQ</targetType>
      <description>
      Power Management data for Quad targets. Stored as an array of bytes.
      The data is read directly from VPD and stored in this attribute without
      being altered.

      NOTE: you may need to handle correcting endianness if you are using this
      attribute.
      </description>
      <valueType>uint8</valueType>
      <initToZero/>
      <array>61</array>
      <platInit/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
      <id>ATTR_WOF_TABLE_DATA</id>
      <targetType>TARGET_TYPE_SYSTEM</targetType>
      <description>
       WOF data from PNOR which contains WOF header data + VFRT data (vfrt header +
       data for 8 Vdn, 21Vdd and 6 Quads)
       Consumed by p9_pstate_parameter_block procedure
      </description>
      <valueType>uint8</valueType>
      <initToZero/>
      <array>131072</array>
      <platInit/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
      <id>ATTR_DUMP_STOP_INFO_SUPPRESS_ERROR_TRACE</id>
      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
      <description>
          if set to 1, FAPI_ERR records are suppressed from being produced by
          p9_dump_stop_info.
      </description>
      <valueType>uint8</valueType>
      <initToZero/>
      <platInit/>
  </attribute>
   <!-- ********************************************************************* -->
  <attribute>
      <id>ATTR_DUMP_STOP_INFO_ENABLE_ERRORLOG</id>
      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
      <description>
          if set to 1, p9_dump_stop_info output will be written to error logs
      </description>
      <valueType>uint8</valueType>
      <initToZero/>
      <platInit/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
      <id>ATTR_VDM_ENABLE</id>
      <targetType>TARGET_TYPE_SYSTEM</targetType>
      <description>
      Controls the enablement of Voltage Droop Monitors (VDM) in the system.

      Producer:  Machine Readable Workbook

      Consumers:
        p9_pstate_parameter_block to set flag for CME QuadManager Hcode
            reaction
        p9_hcd_cache procedures to power on VDMs before CME booting
      </description>
      <valueType>uint8</valueType>
      <enum>OFF = 0x00, ON = 0x01</enum>
      <initToZero/>
      <platInit/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
      <id>ATTR_VDM_DROOP_SMALL_OVERRIDE</id>
      <targetType>TARGET_TYPE_SYSTEM</targetType>
      <description>
          Voltage Droop Monitor (VDM) Small Threshold Select Value per VPD point
          The enum indicates a negative value below the VDM setting that will
          trigger a small droop event.

          Array of 5 entries:
            0 = PowerSave, 1 = Nominal; 2 = Turbo; 3 = UltraTurbo; 4 = Enable

          If index 4 is non-zero, the other entries are considered valid.

          Producer: MRWB.
      </description>
      <valueType>uint8</valueType>
      <enum>
          OFF  = 0x00,
          8mV  = 0x01,
          16mV = 0x02,
          24mV = 0x03,
          32mV = 0x04,
          40mV = 0x05,
          48mV = 0x06,
          56mV = 0x07,
          64mV = 0x08,
          72mV = 0x09,
          80mV = 0x0A,
          88mV = 0x0B,
          92mV = 0x0C,
          96mV = 0x0D
      </enum>
      <array>5</array>
      <initToZero/>
      <platInit/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
      <id>ATTR_VDM_DROOP_LARGE_OVERRIDE</id>
      <targetType>TARGET_TYPE_SYSTEM</targetType>
      <description>
      Voltage Droop Monitor (VDM) Large Threshold Select Value per VPD point
      The enum indicates a negative value below the VDM setting that will
      trigger a large droop event.

      Array of 5 entries:
        0 = PowerSave, 1 = Nominal; 2 = Turbo; 3 = UltraTurbo; 4 = Enable

      If index 4 is non-zero, the other entries are considered valid.

      Producer: Firmware override
      </description>
      <valueType>uint8</valueType>
      <enum>
          OFF  = 0x00,
          8mV  = 0x01,
          16mV = 0x02,
          24mV = 0x03,
          32mV = 0x04,
          40mV = 0x05,
          48mV = 0x06,
          56mV = 0x07,
          64mV = 0x08,
          72mV = 0x09,
          80mV = 0x0A,
          88mV = 0x0B,
          92mV = 0x0C,
          96mV = 0x0D
      </enum>
      <array>5</array>
      <initToZero/>
      <platInit/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
      <id>ATTR_VDM_DROOP_EXTREME_OVERRIDE</id>
      <targetType>TARGET_TYPE_SYSTEM</targetType>
      <description>
      Voltage Droop Monitor (VDM) Extreme Threshold Select Value per VPD point.
      The enum indicates a negative value below the VDM setting that will
      trigger an extreme droop event.

      Array of 5 entries:
        0 = PowerSave, 1 = Nominal; 2 = Turbo; 3 = UltraTurbo; 4 = Enable

      If index 4 is non-zero, the other entries are considered valid.

      Producer: MRWB.
      </description>
      <valueType>uint8</valueType>
      <enum>
          OFF  = 0x00,
          8mV  = 0x01,
          16mV = 0x02,
          24mV = 0x03,
          32mV = 0x04,
          40mV = 0x05,
          48mV = 0x06,
          56mV = 0x07,
          64mV = 0x08,
          72mV = 0x09,
          80mV = 0x0A,
          88mV = 0x0B,
          92mV = 0x0C,
          96mV = 0x0D
      </enum>
      <array>5</array>
      <initToZero/>
      <platInit/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
      <id>ATTR_VDM_OVERVOLT_OVERRIDE</id>
      <targetType>TARGET_TYPE_SYSTEM</targetType>
      <description>
      Voltage Droop Monitor (VDM) OverVoltage Threshold Select Value per VPD
      point. The enum indicates a positive value above the VDM setting that will
      indicate an overvolt droop condition.

      Array of 5 entries:
        0 = PowerSave, 1 = Nominal; 2 = Turbo; 3 = UltraTurbo; 4 = Enable

      If index 4 is non-zero, the other entries are considered valid.

      Producer: MRWB.
      </description>
      <valueType>uint8</valueType>
      <enum>
          FORCE = 0x00,
          8mV   = 0x01,
          16mV  = 0x02,
          24mV  = 0x03,
          32mV  = 0x04,
          40mV  = 0x05,
          48mV  = 0x06,
          56mV  = 0x07,
          64mV  = 0x08
      </enum>
      <array>5</array>
      <initToZero/>
      <platInit/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
      <id>ATTR_VDM_FMAX_OVERRIDE_KHZ</id>
      <targetType>TARGET_TYPE_SYSTEM</targetType>
      <description>

          Producer: MRWB.
      </description>
      <valueType>uint16</valueType>
      <array>5</array>
      <initToZero/>
      <platInit/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
      <id>ATTR_VDM_FMIN_OVERRIDE_KHZ</id>
      <targetType>TARGET_TYPE_SYSTEM</targetType>
      <description>


          Producer: MRWB.
      </description>
      <valueType>uint16</valueType>
      <array>5</array>
      <initToZero/>
      <platInit/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
      <id>ATTR_VDM_VID_COMPARE_OVERRIDE_MV</id>
      <targetType>TARGET_TYPE_SYSTEM</targetType>
      <description>
      Voltage Droop Monitor (VDM) Voltage Compare Voltage to expect when no
      droop is present (binary in mV)

      Array of 5 entries:
        0 = PowerSave, 1 = Nominal; 2 = Turbo; 3 = UltraTurbo; 4 = Enable

      If index 4 is non-zero, the other entries are considered valid.

      Producer: MRWB.
      </description>
      <valueType>uint8</valueType>
      <array>5</array>
      <initToZero/>
      <platInit/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
      <id>ATTR_DPLL_DYNAMIC_FMAX_ENABLE</id>
      <description>
      Allow increased dynamic frequency in response to excess voltage margin
      Controlled by VDM_OVERVOLT threshold value in VDM Configuration Register.

      Producer: MRWB.
      </description>
      <targetType>TARGET_TYPE_SYSTEM</targetType>
      <valueType>uint8</valueType>
      <enum>
          OFF = 0x00,ON = 0x01
      </enum>
      <initToZero/>
      <platInit/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
      <id>ATTR_DPLL_DYNAMIC_FMIN_ENABLE</id>
      <description>
      Allow decreased dynamic frequency in response to loss of voltage margin.
      Controlled by VDM_DROOP_SMALL threshold value in VDM Configuration
      Register.

      Producer: MRWB.
      </description>
      <targetType>TARGET_TYPE_SYSTEM</targetType>
      <valueType>uint8</valueType>
      <enum>
          OFF = 0x00,ON = 0x01
      </enum>
      <initToZero/>
      <platInit/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
      <id>ATTR_DPLL_DROOP_PROTECT_ENABLE</id>
      <description>
      Enable instantaneous frequency reduction in response to droop events
      Controlled by VDM_DROOP_SMALL, _LARGE and _XTREME threshold values in VDM
      Configuration Register. The amount of reduction is controlled by chip
      initialization values

      Producer: MRWB.
      </description>
      <targetType>TARGET_TYPE_SYSTEM</targetType>
      <valueType>uint8</valueType>
      <enum>
          OFF = 0x00,ON = 0x01
      </enum>
      <platInit/>
      <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
      <id>ATTR_DPLL_VDM_RESPONSE</id>
      <targetType>TARGET_TYPE_SYSTEM</targetType>
      <description>
      Indicates the response of the DPLL frequency upon VDM events.  This
      control will only apply if ATTR_DPLL_VDM_JUMP_ENABLE is ON;
      Hardware WOF =  DROOP_PROTECT_OVERVOLT (slew to Fmax if margin exists)

      Producer: MRWB.
      </description>
      <valueType>uint8</valueType>
      <enum>
          STATIC_FREQ = 0x00,
          STATIC_DROOP_PROTECT = 0x01,
          DROOP_PROTECT_OVERVOLT = 0x02,
          DYNAMIC_FREQ = 0x04
      </enum>
      <initToZero/>
      <platInit/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
      <id>ATTR_IVRM_DEADZONE_MV</id>
      <targetType>TARGET_TYPE_SYSTEM</targetType>
      <description>
      Override value for the value of the deadzone where the iVRM cannot regulate
      (binary in millivolts).

      The deadzone is the difference between the voltage from the external VRM
      after load line and other losses are removed and the request regulation
      voltage.  If this difference is smaller than the value of this attribute,
      the iVRM is forced in to bypass to use the external voltage.

      Producer: MRWB.

      Consumer: p9_pstate_parameter_block ->
                    CME pstate parameter block
                    PGPE pstate parameter block

      Handling: p9_pstate_parameter_block reads this attribute. If zero, the
      value of 50 (0x32) is used. If non-zero, this value is used.

      </description>
      <valueType>uint8</valueType>
      <initToZero/>
      <platInit/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
      <id>ATTR_IVRM_STRENGTH_LOOKUP</id>
      <targetType>TARGET_TYPE_SYSTEM</targetType>
      <description>
      Lookup table used to as part of determining the PFET width to use based
      on the voltage across the PFET header.

      Producer: MRWB via the iVRM team

      Consumer: p9_pstate_parameter_block ->
                    CME pstate parameter block
                    PGPE pstate parameter block

      </description>
      <valueType>uint8</valueType>
      <array>64</array>
      <platInit/>
      <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
      <id>ATTR_IVRM_VIN_MULTIPLIER</id>
      <targetType>TARGET_TYPE_SYSTEM</targetType>
      <description>Multiplier used with the strength lookup to determine the IVRM
      PFET width.

      Producer: MRWB via the iVRM team

      Consumer: p9_pstate_parameter_block ->
                    CME pstate parameter block
                    PGPE pstate parameter block
      </description>
      <valueType>uint8</valueType>
      <array>64</array>
      <initToZero/>
      <platInit/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
      <id>ATTR_IVRM_VIN_MAX_MV</id>
      <targetType>TARGET_TYPE_SYSTEM</targetType>
      <description>Override voltage maximum that is used for the IVRM PFET width
      calculation.  Setting to 0 will use the default 1100mV.  Setting this to a
      non-zero value will cause this value to be used instead.

      Producer: MRWB.

      Consumer: p9_pstate_parameter_block ->
                    CME pstate parameter block
                    PGPE pstate parameter block
      </description>
      <valueType>uint16</valueType>
      <platInit/>
      <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
      <id>ATTR_IVRM_STEP_DELAY_NS</id>
      <targetType>TARGET_TYPE_SYSTEM</targetType>
      <description>Time (in nanoseconds) to wait between IVRM steps that are
      part of a larger transition to the ultimate destination voltage.  The
      value of 0 is valid to indicate that no delay is necessary.

      Producer: MRWB.

      Consumer: p9_pstate_parameter_block ->
                    CME pstate parameter block
                    PGPE pstate parameter block
      </description>
      <valueType>uint16</valueType>
      <platInit/>
      <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
      <id>ATTR_IVRM_STABILIZATION_DELAY_NS</id>
      <targetType>TARGET_TYPE_SYSTEM</targetType>
      <description>
      Time (in nanoseconds) to wait after the iVRMs indicate "done" in the event
      extra time is required.

      Producer: MRWB.

      Consumer: p9_pstate_parameter_block ->
                    CME pstate parameter block
                    PGPE pstate parameter block
      </description>
      <valueType>uint16</valueType>
      <platInit/>
      <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_TDP_RDP_CURRENT_FACTOR</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description> TODO RTC 157943 -- Placeholder description
    This overrides the RDP to TDP Scaling Factor IQ VPD field that is used for
    Workload Optimized Frequency (WOF) voltage uplifting.

    Consumers: p9_pstate_parameter_block

    </description>
    <valueType>uint32</valueType>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
      <id>ATTR_SYSTEM_RESCLK_ENABLE</id>
      <targetType>TARGET_TYPE_SYSTEM</targetType>
      <description>
      Controls the enablement of resonant clocking in the system.

      Producer:  Machine Readable Workbook

      Consumers:
        p9_pstate_parameter_block to set flag for CME QuadManager Hcode
            reaction
      </description>
      <valueType>uint8</valueType>
      <enum>OFF = 0x00, ON = 0x01</enum>
      <initToZero/>
      <platInit/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_SYSTEM_RESCLK_STEP_DELAY</id>
    <targetType>TARGET_TYPE_SYSTEM</targetType>
    <description>
    Minimum delay (in nanoseconds) between clock grid management transition
    steps

    Producer: MRWB from clock team
    Consumers: p9_build_pstate_datablock ->
                      CME Quad Pstate Region (CQPR) for CM Quad Manager

    Platform default:   0
    </description>
    <valueType>uint16</valueType>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_SYSTEM_RESCLK_FREQ_REGIONS</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
    Frequency discontinuity region points that defines the lower edge of a
    Resonant Region and where F[i] LT F[i+1] and 0 LE i LE 7.
    This yields:
       ATTR_RESCLK_FREQ_REGIONS[0] LE Region 0 LT ATTR_RESCLK_FREQ_REGIONS[1]
       ATTR_RESCLK_FREQ_REGIONS[1] LE Region 1 LT ATTR_RESCLK_FREQ_REGIONS[2]
       ATTR_RESCLK_FREQ_REGIONS[2] LE Region 2 LT ATTR_RESCLK_FREQ_REGIONS[3]
       etc.

    Producer: MRWB from clock team

    Consumers: p9_pstate_parameter_block
    </description>
    <valueType>uint16</valueType>
    <array>8</array>
    <initToZero/>
    <writeable/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_SYSTEM_RESCLK_FREQ_REGION_INDEX</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
    Defines the index into ATTR_RESCLK_VALUE[] to use for the frequency region.

    The frequency associated with the region is defined by
    ATTR_RESCLK_FREQ_REGIONS[i] and ATTR_RESCLK_FREQ_REGIONS[i+1] for
    0 LE i LE 7.

    Producer: MRWB from clock team

    Consumers: p9_pstate_parameter_block
    </description>
    <valueType>uint8</valueType>
    <array>8</array>
    <initToZero/>
    <writeable/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_SYSTEM_RESCLK_VALUE</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
    Array of Clock strength values that will we written in QACCR by CME Hcode

    Producer: MRWB from clock team

    Consumers: p9_pstate_parameter_block
    </description>
    <valueType>uint16</valueType>
    <array>64</array>
    <initToZero/>
    <writeable/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_SYSTEM_RESCLK_L3_VALUE</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
    Array of L3 Clock strength values to be used going between "High and Normal
    Voltage" and "Low Voltage" mode.   Low Voltage mode is define by
    ATTR_RESCLK_L3_VOLTAGE_THRESHOLD_MV.

    Entry 0 = "High and Normal Voltage" setting
    Entry 3 = "High and Normal Voltage" setting

    Entry 1 = transitional setting defined by the clock team
    Entry 2 = transitional setting defined by the clock team

    Contents of each entry will be written directly into L3 control bits in the
    QACCR(16:23) a RMW operations.  If the circuits demand a grey code whereby
    only 1 bit of this field can change at a time, the entries must be deal with
    such encoding.  The Hcode that these values does not perform that function;
    it merely steps from 0->3 when going below the voltage defined by
    ATTR_RESCLK_L3_VOLTAGE_THRESHOLD_MV and then steps 3->0 when going at or
    above the voltage defined by ATTR_RESCLK_L3_VOLTAGE_THRESHOLD_MV.

    Producer: MRWB from clock team

    Consumers: p9_pstate_parameter_block
    </description>
    <valueType>uint8</valueType>
    <array>4</array>
    <initToZero/>
    <writeable/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
    <id>ATTR_SYSTEM_RESCLK_L3_VOLTAGE_THRESHOLD_MV</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>
    Voltage value (in millivolts) whereby voltage below this value will have
    the L3 clock strength moved to "Low" mode while values at or above this
    value will have the L3 clock strength moved to "High" mode.  The L3 clock
    strength values put in the hardware for this mode transtion are defined by
    ATTR_RESCLK_L3_VALUE.

    Producer: MRWB from clock team

    Consumers: p9_pstate_parameter_block
    </description>
    <valueType>uint16</valueType>
    <initToZero/>
    <writeable/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
      <id>ATTR_SYSTEM_RING_DBG_MODE</id>
      <description>
      Debug modes supported for CME/SGPE Scan layout in HOMER.
      </description>
      <targetType>TARGET_TYPE_SYSTEM</targetType>
      <valueType>uint8</valueType>
      <enum>
          SCAN_RING_NO_DEBUG = 0x00, SCAN_RING_TRACE_DEBUG = 0x01, SCAN_RING_DEEP_DEBUG = 0x02
      </enum>
      <initToZero/>
      <platInit/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
     <id>ATTR_PERF_24x7_INVOCATION_TIME_MS</id>
     <description>
     Time between invocations of the 24x7 performance collection function on
     GPE1.  The time (in milliseconds) is derived as  2^PERF_24x7_INVOCATION_TIME_MS
     with 0 indicating the function is OFF.

     Consumer: p9_hcode_image_build.c ->
                  SGPE Header field

     Provided by the Machine Readable Workbook to tune the collection.

     Platform default:  1
     </description>
     <targetType>TARGET_TYPE_SYSTEM</targetType>
     <valueType>uint8</valueType>
     <initToZero/>
     <platInit/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
     <id>ATTR_CME_INSTRUCTION_TRACE_ENABLE</id>
     <description>
     Enables the SGPE Hcode to enable the CME instruction traces into the L3
     Trace array for debug.  Note:  all configured CMEs will be put into this
     mode if this attribute is ON.

     Consumer: p9_hcode_image_build.c ->
                  SGPE Header field

     Platform default:  OFF
     </description>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <valueType>uint8</valueType>
     <enum>
        OFF = 0x00, ON = 0x01
    </enum>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
     <id>ATTR_CME_CHTM_TRACE_ENABLE</id>
     <description>
     Enables the SGPE Hcode to enable the CME instruction traces into the CHTM
     for debug.  Note:  all configured CMEs will be put into this
     mode if this attribute is ON.

     Consumer: p9_hcode_image_build.c ->
                  SGPE Header field

     Platform default:  OFF
     </description>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <valueType>uint8</valueType>
     <enum>
        OFF = 0x00, ON = 0x01
    </enum>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
     <id>ATTR_CME_CHTM_TRACE_MEMORY_CONFIG</id>
     <description>
     CHTM Trace Memory Configuration value goes directly into CHTM_MEM register.
     User is responsible to put correct data for each bit field of the register.

     Consumer: p9_hcode_image_build.c ->
                  SGPE Header field

     Platform default:  0
     </description>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <valueType>uint64</valueType>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
     <id>ATTR_PGPE_HCODE_FUNCTION_ENABLE</id>
     <description>
     Enables the PGPE Hcode to physically perform frequency and voltage operations
     based on constructed parameters (eg #V VPD, system parameters, biases, WPF
     VFRTs. etc).  If OFF, the PGPE provides an immedicate good response to all
     Pstate/WOF IPC operations from the OCC for firmware integration testing purposes.

     Consumer: p9_hcode_image_build.c ->
                  PGPE Header field

     Platform default:  OFF
     <!--
        @todo RTC 169662 at some point in the program, this default may be switched to
         the opposite setting.  However, coordination needs to occur with all CIs
         as this will enable functions that may not be modeled across the board.
     -->
     </description>
     <targetType>TARGET_TYPE_SYSTEM</targetType>
     <valueType>uint8</valueType>
     <enum>
        OFF = 0x00, ON = 0x01
    </enum>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
     <id>ATTR_POUND_W_STATIC_DATA_ENABLE</id>
     <description>

     Enables pstate parameter block code to use the static #W data
     Consumer: p9_pstate_parameter_block.C ->

     Platform default:  OFF
     <!--
        @todo RTC 169662 at some point in the program, this default may be switched to
         the opposite setting.  However, coordination needs to occur with all CIs
         as this will enable functions that may not be modeled across the board.
     -->
     </description>
     <targetType>TARGET_TYPE_SYSTEM</targetType>
     <valueType>uint8</valueType>
     <enum>
        OFF = 0x00, ON = 0x01
    </enum>
    <platInit/>
    <initToZero/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
     <id>ATTR_AUX_FUNC_INVOCATION_TIME_MS</id>
     <description>
     Time between invocations of auxiliary function on
     GPE1.  The time (in milliseconds) is derived as  2^ATTR_AUX_FUNC_INVOCATION_TIME_MS
     with 0 indicating the function is OFF.

     Consumer: p9_hcode_image_build.c ->
                  SGPE Header field

     Provided by the Machine Readable Workbook to tune the collection.

     Platform default:  1
     </description>
     <targetType>TARGET_TYPE_SYSTEM</targetType>
     <valueType>uint8</valueType>
     <initToZero/>
     <platInit/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
     <id>ATTR_SYS_VFRT_STATIC_DATA_ENABLE</id>
     <description>

     Enables pstate parameter block code to use the static system vfrt data
     Consumer: p9_pstate_parameter_block.C ->

     Platform default:  OFF
     <!--
        @todo RTC 169662 at some point in the program, this default may be switched to
         the opposite setting.  However, coordination needs to occur with all CIs
         as this will enable functions that may not be modeled across the board.
     -->
     </description>
     <targetType>TARGET_TYPE_SYSTEM</targetType>
     <valueType>uint8</valueType>
     <enum>
        OFF = 0x00, ON = 0x01
    </enum>
    <initToZero/>
    <platInit/>
  </attribute>
  <!-- ********************************************************************* -->
  <attribute>
     <id>ATTR_NEST_LEAKAGE_PERCENT</id>
     <description>
     SYSTEM Attribute
     Nest leakage percentage used to calculate the Core leakage.
     Will eventually be read into OCC Pstate Parameter Block
     so the OCC can see it for it's calculations.
     Valid Values: 0% thru 100%
     Producer: Machine Readable Workbook
     Consumer: OCC Firmware
     </description>
     <targetType>TARGET_TYPE_SYSTEM</targetType>
     <valueType>uint8</valueType>
     <initToZero/>
     <platInit/>
  </attribute>
  <!-- ********************************************************************* -->

  <attribute>
      <id>ATTR_VDM_VID_COMPARE_BIAS_0P5PCT</id>
      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
      <description>
      VDM Voltage Compare Bias - % of bias (signed twos
      complement in
      0.5 percent steps) that is applied to the #W VDM
      VID Compare before placement in the respective Pstate
      Paramter Blocks that will be consumed
      by Hcode.
      Array of 4 entries: 0 = PowerSave, 1 =
      Nominal; 2 = Turbo; 3 = UltraTurbo
      If index 4 is non-zero, the
      other entries are considered
      valid.Producer:MRWB.
      </description>
      <valueType>int8</valueType>
      <array>4</array>
      <initToZero/>
      <platInit/>
  </attribute> 

</attributes>