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L3 updates -- p9_sbe_mcs_setup, p9_revert_sbe_mcs_setup
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p9_revert_sbe_mcs_setup
  query ATTR_CHIP_UNIT_POS to eliminate dependence on platform
  getChildren() call returning targets in chip unit position order

p9_sbe_mcs_setup
  merge specialization definitions for set_hb_dcbz_config
  add FFDC collection

p9_sbe_mcs_setup_errors
  add FFDC, callout actions

Change-Id: I26bae24d7686bbba78c5844197a17295ce0de167
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41108
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41112
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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@jjmcgill @sgupta2m
jjmcgill authored and sgupta2m committed Jun 19, 2017
1 parent 1bcfe26 commit d27f5c3
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203 changes: 86 additions & 117 deletions src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C
View file
Expand Up @@ -25,8 +25,6 @@
///
/// @file p9_sbe_mcs_setup.C
/// @brief Configure MC unit to support HB execution (FAPI2)
///

///
/// @author Joe McGill <jmcgill@us.ibm.com>
///
Expand All @@ -35,7 +33,7 @@
// *HWP HWP Owner: Joe McGill <jmcgill@us.ibm.com>
// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
// *HWP Team: Nest
// *HWP Level: 2
// *HWP Level: 3
// *HWP Consumed by: SBE
//

Expand All @@ -48,37 +46,27 @@
#include <p9_mc_scom_addresses.H>
#include <p9_mc_scom_addresses_fld.H>


//------------------------------------------------------------------------------
// Constant definitions
//------------------------------------------------------------------------------
const uint8_t MCS_MCFGP_BASE_ADDRESS_START_BIT = 8;

//------------------------------------------------------------------------------
// Function prototypes
// Function definitions
//------------------------------------------------------------------------------

///
/// @brief Set hostboot dcbz MC configuration for one unit target
/// @brief Set hostboot dcbz configuration for one unit target
///
/// @tparam T template parameter, passed in target.
/// @param[in] i_target Reference to an MC target (MCS/MI)
/// @param[in] i_chip_base_address Chip non-mirrored base address
////// @return FAPI2_RC_SUCCESS if success, else error code.
/// @return FAPI2_RC_SUCCESS if success, else error code.
///
template<fapi2::TargetType T>
fapi2::ReturnCode set_hb_dcbz_config(const fapi2::Target<T>& i_target,
const uint64_t i_chip_base_address);


//------------------------------------------------------------------------------
// Function definitions
//------------------------------------------------------------------------------


// specialization for MCS target type
template<>
fapi2::ReturnCode set_hb_dcbz_config(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
const uint64_t i_chip_base_address)
fapi2::ReturnCode set_hb_dcbz_config(
const fapi2::Target<T>& i_target,
const uint64_t i_chip_base_address)
{
FAPI_DBG("Start");
fapi2::buffer<uint64_t> l_mcfgp;
Expand All @@ -87,7 +75,8 @@ fapi2::ReturnCode set_hb_dcbz_config(const fapi2::Target<fapi2::TARGET_TYPE_MCS>
fapi2::buffer<uint64_t> l_mcfirmask_and;
fapi2::buffer<uint64_t> l_mcaction;

// MCFGP -- set BAR valid, configure single MC group with minimum size at chip base address
// MCFGP -- set BAR valid, configure single MC group with minimum size at
// chip base address
FAPI_TRY(fapi2::getScom(i_target, MCS_MCFGP, l_mcfgp),
"Error from getScom (MCS_MCFGP)");
l_mcfgp.setBit<MCS_MCFGP_VALID>();
Expand Down Expand Up @@ -124,7 +113,6 @@ fapi2::ReturnCode set_hb_dcbz_config(const fapi2::Target<fapi2::TARGET_TYPE_MCS>
"Error from putScom (MCS_MCPERF1)");

// Unmask MC FIR

// Set MC Fault Isolation Action1 Register
l_mcaction.setBit<MCS_MCFIR_MC_INTERNAL_RECOVERABLE_ERROR>();
FAPI_TRY(fapi2::putScom(i_target, MCS_MCFIRACT1, l_mcaction),
Expand All @@ -137,80 +125,13 @@ fapi2::ReturnCode set_hb_dcbz_config(const fapi2::Target<fapi2::TARGET_TYPE_MCS>
l_mcfirmask_and.clearBit<MCS_MCFIR_MC_INTERNAL_NONRECOVERABLE_ERROR>();
l_mcfirmask_and.clearBit<MCS_MCFIR_POWERBUS_PROTOCOL_ERROR>();
l_mcfirmask_and.clearBit<MCS_MCFIR_MULTIPLE_BAR>();
l_mcfirmask_and.clearBit<MCS_MCFIR_INVALID_ADDRESS>();
FAPI_TRY(fapi2::putScom(i_target, MCS_MCFIRMASK_AND, l_mcfirmask_and),
"Error from putScom (MCS_MCFIRMASK_AND)");

fapi_try_exit:
FAPI_DBG("End");
return fapi2::current_err;
}


// specialization for MI target type
template<>
fapi2::ReturnCode set_hb_dcbz_config(const fapi2::Target<fapi2::TARGET_TYPE_MI>& i_target,
const uint64_t i_chip_base_address)
{
FAPI_DBG("Start");
fapi2::buffer<uint64_t> l_mcfgp;
fapi2::buffer<uint64_t> l_mcmode1;
fapi2::buffer<uint64_t> l_mcperf1;
fapi2::buffer<uint64_t> l_mcfirmask_and;
fapi2::buffer<uint64_t> l_mcaction;

// MCFGP -- set BAR valid, configure single MC group with minimum size at chip base address
FAPI_TRY(fapi2::getScom(i_target, MCS_MCFGP, l_mcfgp),
"Error from getScom (MCS_MCFGP)");
l_mcfgp.setBit<MCS_MCFGP_VALID>();
l_mcfgp.clearBit<MCS_MCFGP_MC_CHANNELS_PER_GROUP,
MCS_MCFGP_MC_CHANNELS_PER_GROUP_LEN>();
l_mcfgp.clearBit<MCS_MCFGP_CHANNEL_0_GROUP_MEMBER_IDENTIFICATION,
MCS_MCFGP_CHANNEL_0_GROUP_MEMBER_IDENTIFICATION_LEN>();
l_mcfgp.clearBit<MCS_MCFGP_GROUP_SIZE, MCS_MCFGP_GROUP_SIZE_LEN>();
// group base address field covers RA 8:31
l_mcfgp.insert(i_chip_base_address,
MCS_MCFGP_GROUP_BASE_ADDRESS,
MCS_MCFGP_GROUP_BASE_ADDRESS_LEN,
MCS_MCFGP_BASE_ADDRESS_START_BIT);
FAPI_TRY(fapi2::putScom(i_target, MCS_MCFGP, l_mcfgp),
"Error from putScom (MCS_MCFGP)");

// MCMODE1 -- disable speculation, cmd bypass, fp command bypass
FAPI_TRY(fapi2::getScom(i_target, MCS_MCMODE1, l_mcmode1),
"Error from getScom (MCS_MCMODE1)");
l_mcmode1.setBit<MCS_MCMODE1_DISABLE_ALL_SPEC_OPS>();
l_mcmode1.setBit<MCS_MCMODE1_DISABLE_SPEC_OP,
MCS_MCMODE1_DISABLE_SPEC_OP_LEN>();
l_mcmode1.setBit<MCS_MCMODE1_DISABLE_COMMAND_BYPASS,
MCS_MCMODE1_DISABLE_COMMAND_BYPASS_LEN>();
l_mcmode1.setBit<MCS_MCMODE1_DISABLE_FP_COMMAND_BYPASS>();
FAPI_TRY(fapi2::putScom(i_target, MCS_MCMODE1, l_mcmode1),
"Error from putScom (MCS_MCMODE1)");

// MCS_MCPERF1 -- disable fast path
FAPI_TRY(fapi2::getScom(i_target, MCS_MCPERF1, l_mcperf1),
"Error from getScom (MCS_MCPERF1)");
l_mcperf1.setBit<MCS_MCPERF1_DISABLE_FASTPATH>();
FAPI_TRY(fapi2::putScom(i_target, MCS_MCPERF1, l_mcperf1),
"Error from putScom (MCS_MCPERF1)");

// Unmask MC FIR

// Set MC Fault Isolation Action1 Register
l_mcaction.setBit<MCS_MCFIR_MC_INTERNAL_RECOVERABLE_ERROR>();
FAPI_TRY(fapi2::putScom(i_target, MCS_MCFIRACT1, l_mcaction),
"Error from putScom (MCS_MCFIRACT1)");
if (T != fapi2::TARGET_TYPE_MI)
{
// unimplemented for Cumulus/MI type
l_mcfirmask_and.clearBit<MCS_MCFIR_INVALID_ADDRESS>();
}

// Clear FIR bits in MC Fault Isolation Mask Register
l_mcfirmask_and.flush<1>();
l_mcfirmask_and.clearBit<MCS_MCFIR_COMMAND_LIST_TIMEOUT>();
l_mcfirmask_and.clearBit<MCS_MCFIR_MC_INTERNAL_RECOVERABLE_ERROR>();
l_mcfirmask_and.clearBit<MCS_MCFIR_MC_INTERNAL_NONRECOVERABLE_ERROR>();
l_mcfirmask_and.clearBit<MCS_MCFIR_POWERBUS_PROTOCOL_ERROR>();
l_mcfirmask_and.clearBit<MCS_MCFIR_MULTIPLE_BAR>();
// There is no MCS_MCFIR_INVALID_ADDRESS for cumulus.
// l_mcfirmask_and.clearBit<MCS_MCFIR_INVALID_ADDRESS>();
FAPI_TRY(fapi2::putScom(i_target, MCS_MCFIRMASK_AND, l_mcfirmask_and),
"Error from putScom (MCS_MCFIRMASK_AND)");

Expand All @@ -221,45 +142,90 @@ fapi_try_exit:


// HWP entry point
fapi2::ReturnCode p9_sbe_mcs_setup(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
fapi2::ReturnCode
p9_sbe_mcs_setup(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
{
FAPI_INF("Start");

uint8_t l_is_master_sbe;
uint8_t l_is_mpipl;
uint8_t l_ipl_type;
uint64_t l_chip_base_address_nm0, l_chip_base_address_nm1, l_chip_base_address_m, l_chip_base_address_mmio;
uint64_t l_hostboot_hrmor_offset;
fapi2::ATTR_PROC_SBE_MASTER_CHIP_Type l_is_master_sbe;
fapi2::ATTR_IS_MPIPL_Type l_is_mpipl;
fapi2::ATTR_SYSTEM_IPL_PHASE_Type l_ipl_type;

auto l_mcs_chiplets = i_target.getChildren<fapi2::TARGET_TYPE_MCS>();
auto l_mi_chiplets = i_target.getChildren<fapi2::TARGET_TYPE_MI>();
const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;

// configure one MC on master chip (only if IPL is loading hostboot, and is not memory
// preserving)
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_SBE_MASTER_CHIP, i_target, l_is_master_sbe),
// configure one MC on master chip (only if IPL is loading hostboot, and is
// not memory preserving)
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_SBE_MASTER_CHIP,
i_target,
l_is_master_sbe),
"Error from FAPI_ATTR_GET (ATTR_PROC_SBE_MASTER_CHIP)");
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_MPIPL, FAPI_SYSTEM, l_is_mpipl),
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_MPIPL,
FAPI_SYSTEM,
l_is_mpipl),
"Error from FAPI_ATTR_GET (ATTR_IS_MPIPL)");
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_IPL_PHASE, FAPI_SYSTEM, l_ipl_type),
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_IPL_PHASE,
FAPI_SYSTEM,
l_ipl_type),
"Error from FAPI_ATTR_GET (ATTR_SYSTEM_IPL_PHASE)");

if ((l_ipl_type == fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_HB_IPL) &&
l_is_master_sbe &&
!l_is_mpipl)
(l_is_master_sbe == fapi2::ENUM_ATTR_PROC_SBE_MASTER_CHIP_TRUE) &&
(l_is_mpipl == fapi2::ENUM_ATTR_IS_MPIPL_FALSE))
{
uint64_t l_chip_base_address_nm0;
uint64_t l_chip_base_address_nm1;
uint64_t l_chip_base_address_m;
uint64_t l_chip_base_address_mmio;
uint64_t l_hostboot_hrmor_offset;

#ifdef __PPE__

// assert that a viable MCS/MI chiplet is found to service dcbz on the
// master processor
FAPI_ASSERT(l_mcs_chiplets.size() || l_mi_chiplets.size(),
fapi2::P9_SBE_MCS_SETUP_NO_MC_FOUND_ERR().set_CHIP(i_target),
"No functional MC unit target found");
if (!l_mcs_chiplets.size() &&
!l_mi_chiplets.size())
{
// collect PG FFDC
uint16_t l_n1_pg = 0xFFFF;
uint16_t l_n3_pg = 0xFFFF;

for (auto l_tgt : i_target.getChildren<fapi2::TARGET_TYPE_PERV>(
static_cast<fapi2::TargetFilter>(
fapi2::TARGET_FILTER_NEST_WEST |
fapi2::TARGET_FILTER_NEST_EAST),
fapi2::TARGET_STATE_FUNCTIONAL))
{
uint8_t l_attr_chip_unit_pos = 0;
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS,
l_tgt,
l_attr_chip_unit_pos),
"Error from FAPI_ATTR_GET (ATTR_CHIP_UNIT_POS)");
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PG,
l_tgt,
((l_attr_chip_unit_pos == N3_CHIPLET_ID) ?
(l_n3_pg) :
(l_n1_pg))),
"Error from FAPI_ATTR_GET(ATTR_PG)");
}

FAPI_ASSERT(false,
fapi2::P9_SBE_MCS_SETUP_NO_MC_FOUND_ERR()
.set_CHIP(i_target)
.set_IS_MASTER_SBE(l_is_master_sbe)
.set_IS_MPIPL(l_is_mpipl)
.set_IPL_TYPE(l_ipl_type)
.set_N1_PG(l_n1_pg)
.set_N3_PG(l_n3_pg),
"No functional MC unit target found on master chip");
}

#endif

// determine base address
// = (drawer non-mirrored base address) + (hostboot HRMOR offset)
// min MCS base size is 4GB, local HB will always be below
// = (drawer non-mirrored base address) + (hostboot HRMOR offset)
// min MCS base size is 4GB, local HB will always be below
FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_target,
EFF_FBC_GRP_ID_ONLY,
l_chip_base_address_nm0,
Expand All @@ -268,7 +234,8 @@ fapi2::ReturnCode p9_sbe_mcs_setup(const fapi2::Target<fapi2::TARGET_TYPE_PROC_C
l_chip_base_address_mmio),
"Error from p9_fbc_utils_get_chip_base_addrs");

FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HOSTBOOT_HRMOR_OFFSET, FAPI_SYSTEM,
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HOSTBOOT_HRMOR_OFFSET,
FAPI_SYSTEM,
l_hostboot_hrmor_offset),
"Error from FAPI_ATTR_GET (ATTR_HOSTBOOT_HRMOR_OFFSET)");

Expand All @@ -277,14 +244,16 @@ fapi2::ReturnCode p9_sbe_mcs_setup(const fapi2::Target<fapi2::TARGET_TYPE_PROC_C

if (l_mcs_chiplets.size())
{
FAPI_TRY(set_hb_dcbz_config(l_mcs_chiplets.front(),
l_chip_base_address_nm0),
FAPI_TRY(set_hb_dcbz_config<fapi2::TARGET_TYPE_MCS>(
l_mcs_chiplets.front(),
l_chip_base_address_nm0),
"Error from set_hb_dcbz_config (MCS)");
}
else if (l_mi_chiplets.size())
{
FAPI_TRY(set_hb_dcbz_config(l_mi_chiplets.front(),
l_chip_base_address_nm0),
FAPI_TRY(set_hb_dcbz_config<fapi2::TARGET_TYPE_MI>(
l_mi_chiplets.front(),
l_chip_base_address_nm0),
"Error from set_hb_dcbz_config (MI)");
}
else
Expand Down
11 changes: 7 additions & 4 deletions src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.H
View file
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER sbe Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2016 */
/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -37,7 +37,7 @@
// *HWP HWP Owner: Joe McGill <jmcgill@us.ibm.com>
// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
// *HWP Team: Nest
// *HWP Level: 2
// *HWP Level: 3
// *HWP Consumed by: SBE
//

Expand All @@ -56,7 +56,8 @@
//------------------------------------------------------------------------------

/// function pointer typedef definition for HWP call support
typedef fapi2::ReturnCode (*p9_sbe_mcs_setup_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
typedef fapi2::ReturnCode (*p9_sbe_mcs_setup_FP_t)(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);

//------------------------------------------------------------------------------
// Function prototypes
Expand All @@ -71,7 +72,9 @@ extern "C"
/// @param[in] i_target Reference to processor chip target
/// @return fapi::ReturnCode, FAPI2_RC_SUCCESS if success, else error code.

fapi2::ReturnCode p9_sbe_mcs_setup(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target);
fapi2::ReturnCode p9_sbe_mcs_setup(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target);

} // extern "C"

#endif // _P9_SBE_MCS_SETUP_H_
20 changes: 17 additions & 3 deletions src/import/chips/p9/procedures/xml/error_info/p9_sbe_mcs_setup_errors.xml
View file
Expand Up @@ -5,7 +5,7 @@
<!-- -->
<!-- OpenPOWER sbe Project -->
<!-- -->
<!-- Contributors Listed Below - COPYRIGHT 2015,2016 -->
<!-- Contributors Listed Below - COPYRIGHT 2015,2017 -->
<!-- [+] International Business Machines Corp. -->
<!-- -->
<!-- -->
Expand All @@ -25,10 +25,24 @@
<hwpErrors>
<!-- ******************************************************************** -->
<hwpError>
<sbeError/>
<rc>RC_P9_SBE_MCS_SETUP_NO_MC_FOUND_ERR</rc>
<description>There is no functional MC chiplet (MCS/MI) present on the master chip</description>
<description>
There is no functional MCS/MI unit target configured on the master chip
</description>
<ffdc>CHIP</ffdc>
<ffdc>IS_MASTER_SBE</ffdc>
<ffdc>IS_MPIPL</ffdc>
<ffdc>IPL_TYPE</ffdc>
<ffdc>N1_PG</ffdc>
<ffdc>N3_PG</ffdc>
<callout>
<target>CHIP</target>
<priority>HIGH</priority>
</callout>
<callout>
<procedure>CODE</procedure>
<priority>LOW</priority>
</callout>
</hwpError>
<!-- ******************************************************************** -->
</hwpErrors>
Expand Down

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