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fsp.c
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fsp.c
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/* Copyright 2013-2014 IBM Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
* implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* Service Processor handling code
*
* XXX This mixes PSI and FSP and currently only supports
* P7/P7+ PSI and FSP1
*
* If we are going to support P8 PSI and FSP2, we probably want
* to split the PSI support from the FSP support proper first.
*/
#include <stdarg.h>
#include <processor.h>
#include <io.h>
#include <fsp.h>
#include <lock.h>
#include <interrupts.h>
#include <gx.h>
#include <device.h>
#include <trace.h>
#include <timebase.h>
#include <cpu.h>
#include <errorlog.h>
#include <opal.h>
#include <opal-msg.h>
#include <ccan/list/list.h>
DEFINE_LOG_ENTRY(OPAL_RC_FSP_POLL_TIMEOUT, OPAL_PLATFORM_ERR_EVT, OPAL_FSP,
OPAL_PLATFORM_FIRMWARE, OPAL_ERROR_PANIC, OPAL_NA);
#define FSP_TRACE_MSG
#define FSP_TRACE_EVENT
#define FSP_MAX_IOPATH 4
enum fsp_path_state {
fsp_path_bad,
fsp_path_backup,
fsp_path_active,
};
struct fsp_iopath {
enum fsp_path_state state;
void *fsp_regs;
struct psi *psi;
};
enum fsp_mbx_state {
fsp_mbx_idle, /* Mailbox ready to send */
fsp_mbx_send, /* Mailbox sent, waiting for ack */
fsp_mbx_crit_op, /* Critical operation in progress */
fsp_mbx_prep_for_reset, /* Prepare for reset sent */
fsp_mbx_hir_seq_done, /* HIR sequence done, link forced down */
fsp_mbx_err, /* Mailbox in error state, waiting for r&r */
fsp_mbx_rr, /* Mailbox in r&r */
};
struct fsp {
struct fsp *link;
unsigned int index;
enum fsp_mbx_state state;
struct fsp_msg *pending;
unsigned int iopath_count;
int active_iopath; /* -1: no active IO path */
struct fsp_iopath iopath[FSP_MAX_IOPATH];
};
enum ipl_state {
ipl_initial = 0x00000000,
ipl_opl_sent = 0x00000001,
ipl_got_continue = 0x00000002,
ipl_got_new_role = 0x00000004,
ipl_got_caps = 0x00000008,
ipl_got_fsp_functional = 0x00000010
};
static enum ipl_state ipl_state = ipl_initial;
static struct fsp *first_fsp;
static struct fsp *active_fsp;
static u16 fsp_curseq = 0x8000;
static u64 *fsp_tce_table;
#define FSP_INBOUND_SIZE 0x00100000UL
static void *fsp_inbound_buf = NULL;
static u32 fsp_inbound_off;
static struct lock fsp_lock = LOCK_UNLOCKED;
static struct lock fsp_poll_lock = LOCK_UNLOCKED;
static u64 fsp_cmdclass_resp_bitmask;
static u64 timeout_timer;
static u64 fsp_hir_timeout;
#define FSP_CRITICAL_OP_TIMEOUT 128
#define FSP_DRCR_CLEAR_TIMEOUT 128
/* LID numbers. For now we hijack some of pHyp's own until i figure
* out the whole business with the MasterLID
*/
#define KERNEL_LID_PHYP 0x80a00701
#define KERNEL_LID_OPAL 0x80f00101
#define INITRAMFS_LID_OPAL 0x80f00102
/*
* We keep track on last logged values for some things to print only on
* value changes, but also to relieve pressure on the tracer which
* doesn't do a very good job at detecting repeats when called from
* many different CPUs
*/
static u32 disr_last_print;
static u32 drcr_last_print;
static u32 hstate_last_print;
void fsp_handle_resp(struct fsp_msg *msg);
struct fsp_cmdclass {
int timeout;
bool busy;
struct list_head msgq;
struct list_head clientq;
struct list_head rr_queue; /* To queue up msgs during R/R */
u64 timesent;
};
static struct fsp_cmdclass fsp_cmdclass_rr;
static struct fsp_cmdclass fsp_cmdclass[FSP_MCLASS_LAST - FSP_MCLASS_FIRST + 1]
= {
#define DEF_CLASS(_cl, _to) [_cl - FSP_MCLASS_FIRST] = { .timeout = _to }
DEF_CLASS(FSP_MCLASS_SERVICE, 16),
DEF_CLASS(FSP_MCLASS_PCTRL_MSG, 16),
DEF_CLASS(FSP_MCLASS_PCTRL_ABORTS, 16),
DEF_CLASS(FSP_MCLASS_ERR_LOG, 16),
DEF_CLASS(FSP_MCLASS_CODE_UPDATE, 40),
DEF_CLASS(FSP_MCLASS_FETCH_SPDATA, 16),
DEF_CLASS(FSP_MCLASS_FETCH_HVDATA, 16),
DEF_CLASS(FSP_MCLASS_NVRAM, 16),
DEF_CLASS(FSP_MCLASS_MBOX_SURV, 2),
DEF_CLASS(FSP_MCLASS_RTC, 16),
DEF_CLASS(FSP_MCLASS_SMART_CHIP, 20),
DEF_CLASS(FSP_MCLASS_INDICATOR, 180),
DEF_CLASS(FSP_MCLASS_HMC_INTFMSG, 16),
DEF_CLASS(FSP_MCLASS_HMC_VT, 16),
DEF_CLASS(FSP_MCLASS_HMC_BUFFERS, 16),
DEF_CLASS(FSP_MCLASS_SHARK, 16),
DEF_CLASS(FSP_MCLASS_MEMORY_ERR, 16),
DEF_CLASS(FSP_MCLASS_CUOD_EVENT, 16),
DEF_CLASS(FSP_MCLASS_HW_MAINT, 16),
DEF_CLASS(FSP_MCLASS_VIO, 16),
DEF_CLASS(FSP_MCLASS_SRC_MSG, 16),
DEF_CLASS(FSP_MCLASS_DATA_COPY, 16),
DEF_CLASS(FSP_MCLASS_TONE, 16),
DEF_CLASS(FSP_MCLASS_VIRTUAL_NVRAM, 16),
DEF_CLASS(FSP_MCLASS_TORRENT, 16),
DEF_CLASS(FSP_MCLASS_NODE_PDOWN, 16),
DEF_CLASS(FSP_MCLASS_DIAG, 16),
DEF_CLASS(FSP_MCLASS_PCIE_LINK_TOPO, 16),
DEF_CLASS(FSP_MCLASS_OCC, 16),
};
static void fsp_trace_msg(struct fsp_msg *msg, u8 dir __unused)
{
union trace fsp __unused;
#ifdef FSP_TRACE_MSG
size_t len = offsetof(struct trace_fsp_msg, data[msg->dlen]);
fsp.fsp_msg.dlen = msg->dlen;
fsp.fsp_msg.word0 = msg->word0;
fsp.fsp_msg.word1 = msg->word1;
fsp.fsp_msg.dir = dir;
memcpy(fsp.fsp_msg.data, msg->data.bytes, msg->dlen);
trace_add(&fsp, TRACE_FSP_MSG, len);
#endif /* FSP_TRACE_MSG */
assert(msg->dlen <= sizeof(fsp.fsp_msg.data));
}
static struct fsp *fsp_get_active(void)
{
/* XXX Handle transition between FSPs */
return active_fsp;
}
static u64 fsp_get_class_bit(u8 class)
{
/* Alias classes CE and CF as the FSP has a single queue */
if (class == FSP_MCLASS_IPL)
class = FSP_MCLASS_SERVICE;
return 1ul << (class - FSP_MCLASS_FIRST);
}
static struct fsp_cmdclass *__fsp_get_cmdclass(u8 class)
{
struct fsp_cmdclass *ret;
/* RR class is special */
if (class == FSP_MCLASS_RR_EVENT)
return &fsp_cmdclass_rr;
/* Bound check */
if (class < FSP_MCLASS_FIRST || class > FSP_MCLASS_LAST)
return NULL;
/* Alias classes CE and CF as the FSP has a single queue */
if (class == FSP_MCLASS_IPL)
class = FSP_MCLASS_SERVICE;
ret = &fsp_cmdclass[class - FSP_MCLASS_FIRST];
/* Unknown class */
if (ret->timeout == 0)
return NULL;
return ret;
}
static struct fsp_cmdclass *fsp_get_cmdclass(struct fsp_msg *msg)
{
u8 c = msg->word0 & 0xff;
return __fsp_get_cmdclass(c);
}
static struct fsp_msg *__fsp_allocmsg(void)
{
return zalloc(sizeof(struct fsp_msg));
}
struct fsp_msg *fsp_allocmsg(bool alloc_response)
{
struct fsp_msg *msg;
msg = __fsp_allocmsg();
if (!msg)
return NULL;
if (alloc_response) {
msg->resp = __fsp_allocmsg();
if (!msg->resp) {
free(msg);
return NULL;
}
}
return msg;
}
void __fsp_freemsg(struct fsp_msg *msg)
{
free(msg);
}
void fsp_freemsg(struct fsp_msg *msg)
{
if (msg && msg->resp)
__fsp_freemsg(msg->resp);
__fsp_freemsg(msg);
}
void fsp_cancelmsg(struct fsp_msg *msg)
{
bool need_unlock = false;
struct fsp_cmdclass* cmdclass = fsp_get_cmdclass(msg);
struct fsp *fsp = fsp_get_active();
if (fsp->state != fsp_mbx_rr) {
prerror("FSP: Message cancel allowed only when"
"FSP is in reset\n");
return;
}
if (!cmdclass)
return;
/* Recursive locking */
need_unlock = lock_recursive(&fsp_lock);
list_del(&msg->link);
msg->state = fsp_msg_cancelled;
if (need_unlock)
unlock(&fsp_lock);
}
static void fsp_wreg(struct fsp *fsp, u32 reg, u32 val)
{
struct fsp_iopath *iop;
if (fsp->active_iopath < 0)
return;
iop = &fsp->iopath[fsp->active_iopath];
if (iop->state == fsp_path_bad)
return;
out_be32(iop->fsp_regs + reg, val);
}
static u32 fsp_rreg(struct fsp *fsp, u32 reg)
{
struct fsp_iopath *iop;
if (fsp->active_iopath < 0)
return 0xffffffff;
iop = &fsp->iopath[fsp->active_iopath];
if (iop->state == fsp_path_bad)
return 0xffffffff;
return in_be32(iop->fsp_regs + reg);
}
static void fsp_reg_dump(void)
{
#define FSP_DUMP_ONE(x) \
prlog(PR_DEBUG, " %20s: %x\n", #x, fsp_rreg(fsp, x));
struct fsp *fsp = fsp_get_active();
if (!fsp)
return;
prlog(PR_DEBUG, "FSP #%d: Register dump (state=%d)\n",
fsp->index, fsp->state);
FSP_DUMP_ONE(FSP_DRCR_REG);
FSP_DUMP_ONE(FSP_DISR_REG);
FSP_DUMP_ONE(FSP_MBX1_HCTL_REG);
FSP_DUMP_ONE(FSP_MBX1_FCTL_REG);
FSP_DUMP_ONE(FSP_MBX2_HCTL_REG);
FSP_DUMP_ONE(FSP_MBX2_FCTL_REG);
FSP_DUMP_ONE(FSP_SDES_REG);
FSP_DUMP_ONE(FSP_HDES_REG);
FSP_DUMP_ONE(FSP_HDIR_REG);
FSP_DUMP_ONE(FSP_HDIM_SET_REG);
FSP_DUMP_ONE(FSP_PDIR_REG);
FSP_DUMP_ONE(FSP_PDIM_SET_REG);
FSP_DUMP_ONE(FSP_SCRATCH0_REG);
FSP_DUMP_ONE(FSP_SCRATCH1_REG);
FSP_DUMP_ONE(FSP_SCRATCH2_REG);
FSP_DUMP_ONE(FSP_SCRATCH3_REG);
}
static void fsp_notify_rr_state(u32 state)
{
struct fsp_client *client, *next;
struct fsp_cmdclass *cmdclass = __fsp_get_cmdclass(FSP_MCLASS_RR_EVENT);
assert(cmdclass);
list_for_each_safe(&cmdclass->clientq, client, next, link)
client->message(state, NULL);
}
static void fsp_reset_cmdclass(void)
{
int i;
struct fsp_msg *msg;
/*
* The FSP is in reset and hence we can't expect any response
* to outstanding messages that we've already sent. Clear the
* bitmap to reflect that.
*/
fsp_cmdclass_resp_bitmask = 0;
for (i = 0; i <= (FSP_MCLASS_LAST - FSP_MCLASS_FIRST); i++) {
struct fsp_cmdclass *cmdclass = &fsp_cmdclass[i];
cmdclass->busy = false;
cmdclass->timesent = 0;
/* Make sure the message queue is empty */
while(!list_empty(&cmdclass->msgq)) {
msg = list_pop(&cmdclass->msgq, struct fsp_msg,
link);
list_add_tail(&cmdclass->rr_queue, &msg->link);
}
}
}
static bool fsp_in_hir(struct fsp *fsp)
{
switch (fsp->state) {
case fsp_mbx_crit_op:
case fsp_mbx_prep_for_reset:
return true;
default:
return false;
}
}
static bool fsp_in_reset(struct fsp *fsp)
{
switch (fsp->state) {
case fsp_mbx_hir_seq_done: /* FSP reset triggered */
case fsp_mbx_err: /* Will be reset soon */
case fsp_mbx_rr: /* Mbx activity stopped pending reset */
return true;
default:
return false;
}
}
static bool fsp_hir_state_timeout(void)
{
u64 now = mftb();
if (tb_compare(now, fsp_hir_timeout) == TB_AAFTERB)
return true;
return false;
}
static void fsp_set_hir_timeout(u32 seconds)
{
u64 now = mftb();
fsp_hir_timeout = now + secs_to_tb(seconds);
}
static bool fsp_crit_op_in_progress(struct fsp *fsp)
{
u32 disr = fsp_rreg(fsp, FSP_DISR_REG);
if (disr & FSP_DISR_CRIT_OP_IN_PROGRESS)
return true;
return false;
}
/* Notify the FSP that it will be reset soon by writing to the DRCR */
static void fsp_prep_for_reset(struct fsp *fsp)
{
u32 drcr = fsp_rreg(fsp, FSP_DRCR_REG);
prlog(PR_TRACE, "FSP: Writing reset to DRCR\n");
drcr_last_print = drcr;
fsp_wreg(fsp, FSP_DRCR_REG, (drcr | FSP_PREP_FOR_RESET_CMD));
fsp->state = fsp_mbx_prep_for_reset;
fsp_set_hir_timeout(FSP_DRCR_CLEAR_TIMEOUT);
}
static void fsp_hir_poll(struct fsp *fsp, struct psi *psi)
{
u32 drcr;
switch (fsp->state) {
case fsp_mbx_crit_op:
if (fsp_crit_op_in_progress(fsp)) {
if (fsp_hir_state_timeout())
prerror("FSP: Critical operation timeout\n");
/* XXX What do do next? Check with FSP folks */
} else {
fsp_prep_for_reset(fsp);
}
break;
case fsp_mbx_prep_for_reset:
drcr = fsp_rreg(fsp, FSP_DRCR_REG);
if (drcr != drcr_last_print) {
prlog(PR_TRACE, "FSP: DRCR changed, old = %x,"
" new = %x\n",
drcr_last_print, drcr);
drcr_last_print = drcr;
}
if (drcr & FSP_DRCR_ACK_MASK) {
if (fsp_hir_state_timeout()) {
prerror("FSP: Ack timeout. Triggering reset\n");
psi_reset_fsp(psi);
fsp->state = fsp_mbx_hir_seq_done;
}
} else {
prlog(PR_TRACE, "FSP: DRCR ack received."
" Triggering reset\n");
psi_reset_fsp(psi);
fsp->state = fsp_mbx_hir_seq_done;
}
break;
default:
break;
}
}
/*
* This is the main entry for the host initiated reset case.
* This gets called when:
* a. Surveillance ack is not received in 120 seconds
* b. A mailbox command doesn't get a response within the stipulated time.
*/
static void __fsp_trigger_reset(void)
{
struct fsp *fsp = fsp_get_active();
u32 disr;
/* Already in one of the error processing states */
if (fsp_in_hir(fsp) || fsp_in_reset(fsp))
return;
prerror("FSP: fsp_trigger_reset() entry\n");
drcr_last_print = 0;
/*
* Check if we are allowed to reset the FSP. We aren't allowed to
* reset the FSP if the FSP_DISR_DBG_IN_PROGRESS is set.
*/
disr = fsp_rreg(fsp, FSP_DISR_REG);
if (disr & FSP_DISR_DBG_IN_PROGRESS) {
prerror("FSP: Host initiated reset disabled\n");
return;
}
/*
* Check if some critical operation is in progress as indicated
* by FSP_DISR_CRIT_OP_IN_PROGRESS. Timeout is 128 seconds
*/
if (fsp_crit_op_in_progress(fsp)) {
prlog(PR_NOTICE, "FSP: Critical operation in progress\n");
fsp->state = fsp_mbx_crit_op;
fsp_set_hir_timeout(FSP_CRITICAL_OP_TIMEOUT);
} else
fsp_prep_for_reset(fsp);
}
void fsp_trigger_reset(void)
{
lock(&fsp_lock);
__fsp_trigger_reset();
unlock(&fsp_lock);
}
/*
* Called when we trigger a HIR or when the FSP tells us via the DISR's
* RR bit that one is impending. We should therefore stop all mbox activity.
*/
static void fsp_start_rr(struct fsp *fsp)
{
struct fsp_iopath *iop;
if (fsp->state == fsp_mbx_rr)
return;
/* We no longer have an active path on that FSP */
if (fsp->active_iopath >= 0) {
iop = &fsp->iopath[fsp->active_iopath];
iop->state = fsp_path_bad;
fsp->active_iopath = -1;
}
fsp->state = fsp_mbx_rr;
disr_last_print = 0;
hstate_last_print = 0;
/*
* Mark all command classes as non-busy and clear their
* timeout, then flush all messages in our staging queue
*/
fsp_reset_cmdclass();
/* Notify clients. We have to drop the lock here */
unlock(&fsp_lock);
fsp_notify_rr_state(FSP_RESET_START);
lock(&fsp_lock);
/*
* Unlike earlier, we don't trigger the PSI link polling
* from this point. We wait for the PSI interrupt to tell
* us the FSP is really down and then start the polling there.
*/
}
/*
* Called on normal/quick shutdown to give up the PSI link
*/
void fsp_reset_links(void)
{
struct fsp *fsp = fsp_get_active();
struct fsp_iopath *iop;
if (!fsp)
return;
/* Already in one of the error states? */
if (fsp_in_hir(fsp) || fsp_in_reset(fsp))
return;
iop = &fsp->iopath[fsp->active_iopath];
prlog(PR_NOTICE, "FSP #%d: Host initiated shutdown."
" Giving up the PSI link\n", fsp->index);
psi_disable_link(iop->psi);
return;
}
static void fsp_trace_event(struct fsp *fsp, u32 evt,
u32 data0, u32 data1, u32 data2, u32 data3)
{
union trace tfsp __unused;
#ifdef FSP_TRACE_EVENT
size_t len = sizeof(struct trace_fsp_event);
tfsp.fsp_evt.event = evt;
tfsp.fsp_evt.fsp_state = fsp->state;
tfsp.fsp_evt.data[0] = data0;
tfsp.fsp_evt.data[1] = data1;
tfsp.fsp_evt.data[2] = data2;
tfsp.fsp_evt.data[3] = data3;
trace_add(&tfsp, TRACE_FSP_EVENT, len);
#endif /* FSP_TRACE_EVENT */
}
static void fsp_handle_errors(struct fsp *fsp)
{
u32 hstate;
struct fsp_iopath *iop;
struct psi *psi;
u32 disr;
if (fsp->active_iopath < 0) {
prerror("FSP #%d: fsp_handle_errors() with no active IOP\n",
fsp->index);
return;
}
iop = &fsp->iopath[fsp->active_iopath];
if (!iop->psi) {
prerror("FSP: Active IOP with no PSI link !\n");
return;
}
psi = iop->psi;
/*
* If the link is not up, start R&R immediately, we do call
* psi_disable_link() in this case as while the link might
* not be up, it might still be enabled and the PSI layer
* "active" bit still set
*/
if (!psi_check_link_active(psi)) {
/* Start R&R process */
fsp_trace_event(fsp, TRACE_FSP_EVT_LINK_DOWN, 0, 0, 0, 0);
prerror("FSP #%d: Link down, starting R&R\n", fsp->index);
fsp_start_rr(fsp);
return;
}
/* Link is up, check for other conditions */
disr = fsp_rreg(fsp, FSP_DISR_REG);
/* If in R&R, log values */
if (disr != disr_last_print) {
fsp_trace_event(fsp, TRACE_FSP_EVT_DISR_CHG, disr, 0, 0, 0);
prlog(PR_TRACE, "FSP #%d: DISR stat change = 0x%08x\n",
fsp->index, disr);
disr_last_print = disr;
}
/* On a deferred mbox error, trigger a HIR
* Note: We may never get here since the link inactive case is handled
* above and the other case is when the iop->psi is NULL, which is
* quite rare.
*/
if (fsp->state == fsp_mbx_err) {
prerror("FSP #%d: Triggering HIR on mbx_err\n",
fsp->index);
fsp_trigger_reset();
return;
}
/*
* If we get here as part of normal flow, the FSP is telling
* us that there will be an impending R&R, so we stop all mbox
* activity. The actual link down trigger is via a PSI
* interrupt that may arrive in due course.
*/
if (disr & FSP_DISR_FSP_IN_RR) {
/*
* If we get here with DEBUG_IN_PROGRESS also set, the
* FSP is in debug and we should *not* reset it now
*/
if (disr & FSP_DISR_DBG_IN_PROGRESS)
return;
/*
* When the linux comes back up, we still see that bit
* set for a bit, so just move on, nothing to see here
*/
if (fsp->state == fsp_mbx_rr)
return;
if (fsp_dpo_pending) {
/*
* If we are about to process a reset when DPO
* is pending, its possible that the host has
* gone down, and OPAL is on its way down and
* hence will not see the subsequent PSI interrupt.
* So, just give up the link here.
*/
prlog(PR_NOTICE, "FSP #%d: FSP reset with DPO pending."
" Giving up PSI link\n",
fsp->index);
psi_disable_link(psi);
} else {
prlog(PR_NOTICE, "FSP #%d: FSP in Reset."
" Waiting for PSI interrupt\n",
fsp->index);
}
fsp_start_rr(fsp);
}
/*
* However, if any of Unit Check or Runtime Termintated or
* Flash Terminated bits is also set, the FSP is asking us
* to trigger a HIR so it can try to recover via the DRCR route.
*/
if (disr & FSP_DISR_HIR_TRIGGER_MASK) {
fsp_trace_event(fsp, TRACE_FSP_EVT_SOFT_RR, disr, 0, 0, 0);
if (disr & FSP_DISR_FSP_UNIT_CHECK)
prlog(PR_DEBUG, "FSP: DISR Unit Check set\n");
else if (disr & FSP_DISR_FSP_RUNTIME_TERM)
prlog(PR_DEBUG, "FSP: DISR Runtime Terminate set\n");
else if (disr & FSP_DISR_FSP_FLASH_TERM)
prlog(PR_DEBUG, "FSP: DISR Flash Terminate set\n");
prlog(PR_NOTICE, "FSP: Triggering host initiated reset"
" sequence\n");
/* Clear all interrupt conditions */
fsp_wreg(fsp, FSP_HDIR_REG, FSP_DBIRQ_ALL);
/* Make sure this happened */
fsp_rreg(fsp, FSP_HDIR_REG);
fsp_trigger_reset();
return;
}
/*
* We detect an R&R complete indication, acknolwedge it
*/
if (disr & FSP_DISR_FSP_RR_COMPLETE) {
/*
* Acking this bit doens't make it go away immediately, so
* only do it while still in R&R state
*/
if (fsp->state == fsp_mbx_rr) {
fsp_trace_event(fsp, TRACE_FSP_EVT_RR_COMPL, 0,0,0,0);
prlog(PR_NOTICE, "FSP #%d: Detected R&R complete,"
" acking\n", fsp->index);
/* Clear HDATA area */
fsp_wreg(fsp, FSP_MBX1_HDATA_AREA, 0xff);
/* Ack it (XDN) and clear HPEND & counts */
fsp_wreg(fsp, FSP_MBX1_HCTL_REG,
FSP_MBX_CTL_PTS |
FSP_MBX_CTL_XDN |
FSP_MBX_CTL_HPEND |
FSP_MBX_CTL_HCSP_MASK |
FSP_MBX_CTL_DCSP_MASK);
/*
* Mark the mbox as usable again so we can process
* incoming messages
*/
fsp->state = fsp_mbx_idle;
/* Also clear R&R complete bit in DISR */
fsp_wreg(fsp, FSP_DISR_REG, FSP_DISR_FSP_RR_COMPLETE);
psi_enable_fsp_interrupt(psi);
}
}
/*
* XXX
*
* Here we detect a number of errors, should we initiate
* and R&R ?
*/
hstate = fsp_rreg(fsp, FSP_HDES_REG);
if (hstate != hstate_last_print) {
fsp_trace_event(fsp, TRACE_FSP_EVT_HDES_CHG, hstate, 0, 0, 0);
prlog(PR_DEBUG, "FSP #%d: HDES stat change = 0x%08x\n",
fsp->index, hstate);
hstate_last_print = hstate;
}
if (hstate == 0xffffffff)
return;
/* Clear errors */
fsp_wreg(fsp, FSP_HDES_REG, FSP_DBERRSTAT_CLR1);
/*
* Most of those errors shouldn't have happened, we just clear
* the error state and return. In the long run, we might want
* to start retrying commands, switching FSPs or links, etc...
*
* We currently don't set our mailbox to a permanent error state.
*/
if (hstate & FSP_DBERRSTAT_ILLEGAL1)
prerror("FSP #%d: Illegal command error !\n", fsp->index);
if (hstate & FSP_DBERRSTAT_WFULL1)
prerror("FSP #%d: Write to a full mbox !\n", fsp->index);
if (hstate & FSP_DBERRSTAT_REMPTY1)
prerror("FSP #%d: Read from an empty mbox !\n", fsp->index);
if (hstate & FSP_DBERRSTAT_PAR1)
prerror("FSP #%d: Parity error !\n", fsp->index);
}
/*
* This is called by fsp_post_msg() to check if the mbox
* is in a state that allows sending of a message
*
* Due to the various "interesting" contexts fsp_post_msg()
* can be called from, including recursive locks from lock
* error messages or console code, this should avoid doing
* anything more complex than checking a bit of state.
*
* Specifically, we cannot initiate an R&R and call back into
* clients etc... from this function.
*
* The best we can do is to se the mbox in error state and
* handle it later during a poll or interrupts.
*/
static bool fsp_check_can_send(struct fsp *fsp)
{
struct fsp_iopath *iop;
struct psi *psi;
/* Look for FSP in non-idle state */
if (fsp->state != fsp_mbx_idle)
return false;
/* Look for an active IO path */
if (fsp->active_iopath < 0)
goto mbox_error;
iop = &fsp->iopath[fsp->active_iopath];
if (!iop->psi) {
prerror("FSP: Active IOP with no PSI link !\n");
goto mbox_error;
}
psi = iop->psi;
/* Check if link has gone down. This will be handled later */
if (!psi_check_link_active(psi)) {
prerror("FSP #%d: Link seems to be down on send\n", fsp->index);
goto mbox_error;
}
/* XXX Do we want to check for other error conditions ? */
return true;
/*
* An error of some case occurred, we'll handle it later
* from a more normal "poll" context
*/
mbox_error:
fsp->state = fsp_mbx_err;
return false;
}
static bool fsp_post_msg(struct fsp *fsp, struct fsp_msg *msg)
{
u32 ctl, reg;
int i, wlen;
prlog(PR_INSANE, "FSP #%d: fsp_post_msg (w0: 0x%08x w1: 0x%08x)\n",
fsp->index, msg->word0, msg->word1);
/* Note: We used to read HCTL here and only modify some of
* the bits in it. This was bogus, because we would write back
* the incoming bits as '1' and clear them, causing fsp_poll()
* to then miss them. Let's just start with 0, which is how
* I suppose the HW intends us to do.
*/
/* Set ourselves as busy */
fsp->pending = msg;
fsp->state = fsp_mbx_send;
msg->state = fsp_msg_sent;
/* We trace after setting the mailbox state so that if the
* tracing recurses, it ends up just queuing the message up
*/
fsp_trace_msg(msg, TRACE_FSP_MSG_OUT);
/* Build the message in the mailbox */
reg = FSP_MBX1_HDATA_AREA;
fsp_wreg(fsp, reg, msg->word0); reg += 4;
fsp_wreg(fsp, reg, msg->word1); reg += 4;
wlen = (msg->dlen + 3) >> 2;
for (i = 0; i < wlen; i++) {
fsp_wreg(fsp, reg, msg->data.words[i]);
reg += 4;
}
/* Write the header */
fsp_wreg(fsp, FSP_MBX1_HHDR0_REG, (msg->dlen + 8) << 16);
/* Write the control register */
ctl = 4 << FSP_MBX_CTL_HCHOST_SHIFT;
ctl |= (msg->dlen + 8) << FSP_MBX_CTL_DCHOST_SHIFT;
ctl |= FSP_MBX_CTL_PTS | FSP_MBX_CTL_SPPEND;
prlog(PR_INSANE, " new ctl: %08x\n", ctl);
fsp_wreg(fsp, FSP_MBX1_HCTL_REG, ctl);
return true;
}
static void fsp_poke_queue(struct fsp_cmdclass *cmdclass)
{
struct fsp *fsp = fsp_get_active();
struct fsp_msg *msg;
if (!fsp)
return;
if (!fsp_check_can_send(fsp))
return;
/* From here to the point where fsp_post_msg() sets fsp->state
* to !idle we must not cause any re-entrancy (no debug or trace)
* in a code path that may hit fsp_post_msg() (it's ok to do so
* if we are going to bail out), as we are committed to calling
* fsp_post_msg() and so a re-entrancy could cause us to do a
* double-send into the mailbox.
*/
if (cmdclass->busy || list_empty(&cmdclass->msgq))
return;
msg = list_top(&cmdclass->msgq, struct fsp_msg, link);
assert(msg);
cmdclass->busy = true;
if (!fsp_post_msg(fsp, msg)) {
prerror("FSP #%d: Failed to send message\n", fsp->index);
cmdclass->busy = false;
return;
}
}
static void __fsp_fillmsg(struct fsp_msg *msg, u32 cmd_sub_mod,
u8 add_words, va_list list)
{
bool response = !!(cmd_sub_mod & 0x1000000);
u8 cmd = (cmd_sub_mod >> 16) & 0xff;
u8 sub = (cmd_sub_mod >> 8) & 0xff;
u8 mod = cmd_sub_mod & 0xff;
int i;
msg->word0 = cmd & 0xff;
msg->word1 = mod << 8 | sub;
msg->response = response;
msg->dlen = add_words << 2;
for (i = 0; i < add_words; i++)
msg->data.words[i] = va_arg(list, unsigned int);
va_end(list);
}
void fsp_fillmsg(struct fsp_msg *msg, u32 cmd_sub_mod, u8 add_words, ...)
{
va_list list;
va_start(list, add_words);
__fsp_fillmsg(msg, cmd_sub_mod, add_words, list);
va_end(list);
}
struct fsp_msg *fsp_mkmsg(u32 cmd_sub_mod, u8 add_words, ...)
{
struct fsp_msg *msg = fsp_allocmsg(!!(cmd_sub_mod & 0x1000000));
va_list list;
if (!msg) {
prerror("FSP: Failed to allocate struct fsp_msg\n");
return NULL;
}
va_start(list, add_words);
__fsp_fillmsg(msg, cmd_sub_mod, add_words, list);
va_end(list);
return msg;
}
/*