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phb4.c
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phb4.c
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/* Copyright 2013-2016 IBM Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
* implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* PHB4 support
*
*/
/*
*
* FIXME:
* More stuff for EEH support:
* - PBCQ error reporting interrupt
* - I2C-based power management (replacing SHPC)
* - Directly detect fenced PHB through one dedicated HW reg
*/
#undef NO_ASB
#undef LOG_CFG
#include <skiboot.h>
#include <io.h>
#include <timebase.h>
#include <pci.h>
#include <pci-cfg.h>
#include <pci-slot.h>
#include <vpd.h>
#include <interrupts.h>
#include <opal.h>
#include <cpu.h>
#include <device.h>
#include <ccan/str/str.h>
#include <ccan/array_size/array_size.h>
#include <xscom.h>
#include <affinity.h>
#include <phb4.h>
#include <phb4-regs.h>
#include <capp.h>
#include <fsp.h>
#include <chip.h>
#include <chiptod.h>
#include <xive.h>
#include <xscom-p9-regs.h>
#include <phys-map.h>
#include <nvram.h>
/* Enable this to disable error interrupts for debug purposes */
#define DISABLE_ERR_INTS
static void phb4_init_hw(struct phb4 *p, bool first_init);
#define PHBDBG(p, fmt, a...) prlog(PR_DEBUG, "PHB#%04x[%d:%d]: " fmt, \
(p)->phb.opal_id, (p)->chip_id, \
(p)->index, ## a)
#define PHBINF(p, fmt, a...) prlog(PR_INFO, "PHB#%04x[%d:%d]: " fmt, \
(p)->phb.opal_id, (p)->chip_id, \
(p)->index, ## a)
#define PHBERR(p, fmt, a...) prlog(PR_ERR, "PHB#%04x[%d:%d]: " fmt, \
(p)->phb.opal_id, (p)->chip_id, \
(p)->index, ## a)
#ifdef LOG_CFG
#define PHBLOGCFG(p, fmt, a...) PHBDBG(p, fmt, ## a)
#else
#define PHBLOGCFG(p, fmt, a...) do {} while (0)
#endif
/* Note: The "ASB" name is historical, practically this means access via
* the XSCOM backdoor
*/
static inline uint64_t phb4_read_reg_asb(struct phb4 *p, uint32_t offset)
{
#ifdef NO_ASB
return in_be64(p->regs + offset);
#else
int64_t rc;
uint64_t addr, val;
/* Address register: must use 4 bytes for built-in config space.
*
* This path isn't usable for outbound configuration space
*/
if ((offset & 0xfffffffc) == PHB_CONFIG_DATA) {
PHBERR(p, "XSCOM access to CONFIG_DATA unsupported\n");
return -1ull;
}
addr = XETU_HV_IND_ADDR_VALID | offset;
if (offset >= 0x1000 && offset < 0x1800)
addr |= XETU_HV_IND_ADDR_4B;
rc = xscom_write(p->chip_id, p->etu_xscom + XETU_HV_IND_ADDRESS, addr);
if (rc != 0) {
PHBERR(p, "XSCOM error addressing register 0x%x\n", offset);
return -1ull;
}
rc = xscom_read(p->chip_id, p->etu_xscom + XETU_HV_IND_DATA, &val);
if (rc != 0) {
PHBERR(p, "XSCOM error reading register 0x%x\n", offset);
return -1ull;
}
return val;
#endif
}
static inline void phb4_write_reg_asb(struct phb4 *p,
uint32_t offset, uint64_t val)
{
#ifdef NO_ASB
out_be64(p->regs + offset, val);
#else
int64_t rc;
uint64_t addr;
/* Address register: must use 4 bytes for built-in config space.
*
* This path isn't usable for outbound configuration space
*/
if ((offset & 0xfffffffc) == PHB_CONFIG_DATA) {
PHBERR(p, "XSCOM access to CONFIG_DATA unsupported\n");
return;
}
addr = XETU_HV_IND_ADDR_VALID | offset;
if (offset >= 0x1000 && offset < 0x1800)
addr |= XETU_HV_IND_ADDR_4B;
rc = xscom_write(p->chip_id, p->etu_xscom + XETU_HV_IND_ADDRESS, addr);
if (rc != 0) {
PHBERR(p, "XSCOM error addressing register 0x%x\n", offset);
return;
}
rc = xscom_write(p->chip_id, p->etu_xscom + XETU_HV_IND_DATA, val);
if (rc != 0) {
PHBERR(p, "XSCOM error writing register 0x%x\n", offset);
return;
}
#endif
}
/* Helper to select an IODA table entry */
static inline void phb4_ioda_sel(struct phb4 *p, uint32_t table,
uint32_t addr, bool autoinc)
{
out_be64(p->regs + PHB_IODA_ADDR,
(autoinc ? PHB_IODA_AD_AUTOINC : 0) |
SETFIELD(PHB_IODA_AD_TSEL, 0ul, table) |
SETFIELD(PHB_IODA_AD_TADR, 0ul, addr));
}
/* Check if AIB is fenced via PBCQ NFIR */
static bool phb4_fenced(struct phb4 *p)
{
uint64_t nfir;
xscom_read(p->chip_id, p->pe_stk_xscom + 0x0, &nfir);
if (nfir & PPC_BIT(16)) {
p->flags |= PHB4_AIB_FENCED;
p->state = PHB4_STATE_FENCED;
return true;
}
return false;
}
/*
* Configuration space access
*
* The PHB lock is assumed to be already held
*/
static int64_t phb4_pcicfg_check(struct phb4 *p, uint32_t bdfn,
uint32_t offset, uint32_t size,
uint8_t *pe)
{
uint32_t sm = size - 1;
if (offset > 0xfff || bdfn > 0xffff)
return OPAL_PARAMETER;
if (offset & sm)
return OPAL_PARAMETER;
/* The root bus only has a device at 0 and we get into an
* error state if we try to probe beyond that, so let's
* avoid that and just return an error to Linux
*/
if ((bdfn >> 8) == 0 && (bdfn & 0xff))
return OPAL_HARDWARE;
/* Check PHB state */
if (p->state == PHB4_STATE_BROKEN)
return OPAL_HARDWARE;
/* Fetch the PE# from cache */
*pe = p->rte_cache[bdfn];
return OPAL_SUCCESS;
}
static int64_t phb4_rc_read(struct phb4 *p, uint32_t offset, uint8_t sz,
void *data)
{
uint32_t reg = offset & ~3;
uint32_t oval;
/* Some registers are handled locally */
switch (reg) {
/* Bridge base/limit registers are cached here as HW
* doesn't implement them (it hard codes values that
* will confuse a proper PCI implementation).
*/
case PCI_CFG_MEM_BASE: /* Includes PCI_CFG_MEM_LIMIT */
oval = p->rc_cache[(reg - 0x20) >> 2] & 0xfff0fff0;
break;
case PCI_CFG_PREF_MEM_BASE: /* Includes PCI_CFG_PREF_MEM_LIMIT */
oval = p->rc_cache[(reg - 0x20) >> 2] & 0xfff0fff0;
oval |= 0x00010001;
break;
case PCI_CFG_IO_BASE_U16: /* Includes PCI_CFG_IO_LIMIT_U16 */
oval = 0;
break;
case PCI_CFG_PREF_MEM_BASE_U32:
case PCI_CFG_PREF_MEM_LIMIT_U32:
oval = p->rc_cache[(reg - 0x20) >> 2];
break;
default:
oval = 0xffffffff; /* default if offset too big */
if (reg < PHB_RC_CONFIG_SIZE)
/* XXX Add ASB support ? */
oval = in_le32(p->regs + PHB_RC_CONFIG_BASE + reg);
}
switch (sz) {
case 1:
offset &= 3;
*((uint8_t *)data) = (oval >> (offset << 3)) & 0xff;
break;
case 2:
offset &= 2;
*((uint16_t *)data) = (oval >> (offset << 3)) & 0xffff;
break;
case 4:
*((uint32_t *)data) = oval;
break;
default:
assert(false);
}
return OPAL_SUCCESS;
}
static int64_t phb4_rc_write(struct phb4 *p, uint32_t offset, uint8_t sz,
uint32_t val)
{
uint32_t reg = offset & ~3;
uint32_t old, mask, shift;
int64_t rc;
if (reg > PHB_RC_CONFIG_SIZE)
return OPAL_SUCCESS;
/* If size isn't 4-bytes, do a RMW cycle
*
* XXX TODO: Filter out registers that do write-1-to-clear !!!
*/
if (sz < 4) {
rc = phb4_rc_read(p, reg, 4, &old);
if (rc != OPAL_SUCCESS)
return rc;
if (sz == 1) {
shift = (offset & 3) << 3;
mask = 0xff << shift;
val = (old & ~mask) | ((val & 0xff) << shift);
} else {
shift = (offset & 2) << 3;
mask = 0xffff << shift;
val = (old & ~mask) | ((val & 0xffff) << shift);
}
}
/* Some registers are handled locally */
switch (reg) {
/* See comment in phb4_rc_read() */
case PCI_CFG_MEM_BASE: /* Includes PCI_CFG_MEM_LIMIT */
case PCI_CFG_PREF_MEM_BASE: /* Includes PCI_CFG_PREF_MEM_LIMIT */
case PCI_CFG_PREF_MEM_BASE_U32:
case PCI_CFG_PREF_MEM_LIMIT_U32:
p->rc_cache[(reg - 0x20) >> 2] = val;
break;
case PCI_CFG_IO_BASE_U16: /* Includes PCI_CFG_IO_LIMIT_U16 */
break;
default:
/* XXX Add ASB support ? */
/* Workaround PHB config space enable */
if ((p->rev == PHB4_REV_NIMBUS_DD10) && (reg == PCI_CFG_CMD))
val |= PCI_CFG_CMD_MEM_EN | PCI_CFG_CMD_BUS_MASTER_EN;
out_le32(p->regs + PHB_RC_CONFIG_BASE + reg, val);
}
return OPAL_SUCCESS;
}
static int64_t phb4_pcicfg_read(struct phb4 *p, uint32_t bdfn,
uint32_t offset, uint32_t size,
void *data)
{
uint64_t addr, val64;
int64_t rc;
uint8_t pe;
bool use_asb = false;
rc = phb4_pcicfg_check(p, bdfn, offset, size, &pe);
if (rc)
return rc;
if (p->flags & PHB4_AIB_FENCED) {
if (!(p->flags & PHB4_CFG_USE_ASB))
return OPAL_HARDWARE;
use_asb = true;
} else if ((p->flags & PHB4_CFG_BLOCKED) && bdfn != 0) {
return OPAL_HARDWARE;
}
/* Handle per-device filters */
rc = pci_handle_cfg_filters(&p->phb, bdfn, offset, size,
(uint32_t *)data, false);
if (rc != OPAL_PARTIAL)
return rc;
/* Handle root complex MMIO based config space */
if (bdfn == 0)
return phb4_rc_read(p, offset, size, data);
addr = PHB_CA_ENABLE;
addr = SETFIELD(PHB_CA_BDFN, addr, bdfn);
addr = SETFIELD(PHB_CA_REG, addr, offset & ~3u);
addr = SETFIELD(PHB_CA_PE, addr, pe);
if (use_asb) {
phb4_write_reg_asb(p, PHB_CONFIG_ADDRESS, addr);
sync();
val64 = bswap_64(phb4_read_reg_asb(p, PHB_CONFIG_DATA));
switch(size) {
case 1:
*((uint8_t *)data) = val64 >> (8 * (offset & 3));
break;
case 2:
*((uint16_t *)data) = val64 >> (8 * (offset & 2));
break;
case 4:
*((uint32_t *)data) = val64;
break;
default:
return OPAL_PARAMETER;
}
} else {
out_be64(p->regs + PHB_CONFIG_ADDRESS, addr);
switch(size) {
case 1:
*((uint8_t *)data) =
in_8(p->regs + PHB_CONFIG_DATA + (offset & 3));
PHBLOGCFG(p, "CFG8 Rd %02x=%02x\n",
offset, *((uint8_t *)data));
break;
case 2:
*((uint16_t *)data) =
in_le16(p->regs + PHB_CONFIG_DATA + (offset & 2));
PHBLOGCFG(p, "CFG16 Rd %02x=%04x\n",
offset, *((uint16_t *)data));
break;
case 4:
*((uint32_t *)data) = in_le32(p->regs + PHB_CONFIG_DATA);
PHBLOGCFG(p, "CFG32 Rd %02x=%08x\n",
offset, *((uint32_t *)data));
break;
default:
return OPAL_PARAMETER;
}
}
return OPAL_SUCCESS;
}
#define PHB4_PCI_CFG_READ(size, type) \
static int64_t phb4_pcicfg_read##size(struct phb *phb, uint32_t bdfn, \
uint32_t offset, type *data) \
{ \
struct phb4 *p = phb_to_phb4(phb); \
\
/* Initialize data in case of error */ \
*data = (type)0xffffffff; \
return phb4_pcicfg_read(p, bdfn, offset, sizeof(type), data); \
}
static int64_t phb4_pcicfg_write(struct phb4 *p, uint32_t bdfn,
uint32_t offset, uint32_t size,
uint32_t data)
{
uint64_t addr;
int64_t rc;
uint8_t pe;
bool use_asb = false;
rc = phb4_pcicfg_check(p, bdfn, offset, size, &pe);
if (rc)
return rc;
if (p->flags & PHB4_AIB_FENCED) {
if (!(p->flags & PHB4_CFG_USE_ASB))
return OPAL_HARDWARE;
use_asb = true;
} else if ((p->flags & PHB4_CFG_BLOCKED) && bdfn != 0) {
return OPAL_HARDWARE;
}
/* Handle per-device filters */
rc = pci_handle_cfg_filters(&p->phb, bdfn, offset, size,
(uint32_t *)&data, true);
if (rc != OPAL_PARTIAL)
return rc;
/* Handle root complex MMIO based config space */
if (bdfn == 0)
return phb4_rc_write(p, offset, size, data);
addr = PHB_CA_ENABLE;
addr = SETFIELD(PHB_CA_BDFN, addr, bdfn);
addr = SETFIELD(PHB_CA_REG, addr, offset & ~3u);
addr = SETFIELD(PHB_CA_PE, addr, pe);
if (use_asb) {
/* We don't support ASB config space writes */
return OPAL_UNSUPPORTED;
} else {
out_be64(p->regs + PHB_CONFIG_ADDRESS, addr);
switch(size) {
case 1:
out_8(p->regs + PHB_CONFIG_DATA + (offset & 3), data);
break;
case 2:
out_le16(p->regs + PHB_CONFIG_DATA + (offset & 2), data);
break;
case 4:
out_le32(p->regs + PHB_CONFIG_DATA, data);
break;
default:
return OPAL_PARAMETER;
}
}
PHBLOGCFG(p, "CFG%d Wr %02x=%08x\n", 8 * size, offset, data);
return OPAL_SUCCESS;
}
#define PHB4_PCI_CFG_WRITE(size, type) \
static int64_t phb4_pcicfg_write##size(struct phb *phb, uint32_t bdfn, \
uint32_t offset, type data) \
{ \
struct phb4 *p = phb_to_phb4(phb); \
\
return phb4_pcicfg_write(p, bdfn, offset, sizeof(type), data); \
}
PHB4_PCI_CFG_READ(8, u8)
PHB4_PCI_CFG_READ(16, u16)
PHB4_PCI_CFG_READ(32, u32)
PHB4_PCI_CFG_WRITE(8, u8)
PHB4_PCI_CFG_WRITE(16, u16)
PHB4_PCI_CFG_WRITE(32, u32)
static uint8_t phb4_choose_bus(struct phb *phb __unused,
struct pci_device *bridge __unused,
uint8_t candidate, uint8_t *max_bus __unused,
bool *use_max)
{
/* Use standard bus number selection */
*use_max = false;
return candidate;
}
static int64_t phb4_get_reserved_pe_number(struct phb *phb)
{
struct phb4 *p = phb_to_phb4(phb);
return PHB4_RESERVED_PE_NUM(p);
}
static void phb4_root_port_init(struct phb *phb __unused,
struct pci_device *dev __unused,
int ecap __unused,
int aercap __unused)
{
#if 0
uint16_t bdfn = dev->bdfn;
uint16_t val16;
uint32_t val32;
// FIXME: check recommended init values for phb4
/* Enable SERR and parity checking */
pci_cfg_read16(phb, bdfn, PCI_CFG_CMD, &val16);
val16 |= (PCI_CFG_CMD_SERR_EN | PCI_CFG_CMD_PERR_RESP);
pci_cfg_write16(phb, bdfn, PCI_CFG_CMD, val16);
/* Enable reporting various errors */
if (!ecap) return;
pci_cfg_read16(phb, bdfn, ecap + PCICAP_EXP_DEVCTL, &val16);
val16 |= (PCICAP_EXP_DEVCTL_CE_REPORT |
PCICAP_EXP_DEVCTL_NFE_REPORT |
PCICAP_EXP_DEVCTL_FE_REPORT |
PCICAP_EXP_DEVCTL_UR_REPORT);
pci_cfg_write16(phb, bdfn, ecap + PCICAP_EXP_DEVCTL, val16);
if (!aercap) return;
/* Mask various unrecoverable errors */
pci_cfg_read32(phb, bdfn, aercap + PCIECAP_AER_UE_MASK, &val32);
val32 |= (PCIECAP_AER_UE_MASK_POISON_TLP |
PCIECAP_AER_UE_MASK_COMPL_TIMEOUT |
PCIECAP_AER_UE_MASK_COMPL_ABORT |
PCIECAP_AER_UE_MASK_ECRC);
pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_UE_MASK, val32);
/* Report various unrecoverable errors as fatal errors */
pci_cfg_read32(phb, bdfn, aercap + PCIECAP_AER_UE_SEVERITY, &val32);
val32 |= (PCIECAP_AER_UE_SEVERITY_DLLP |
PCIECAP_AER_UE_SEVERITY_SURPRISE_DOWN |
PCIECAP_AER_UE_SEVERITY_FLOW_CTL_PROT |
PCIECAP_AER_UE_SEVERITY_UNEXP_COMPL |
PCIECAP_AER_UE_SEVERITY_RECV_OVFLOW |
PCIECAP_AER_UE_SEVERITY_MALFORMED_TLP);
pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_UE_SEVERITY, val32);
/* Mask various recoverable errors */
pci_cfg_read32(phb, bdfn, aercap + PCIECAP_AER_CE_MASK, &val32);
val32 |= PCIECAP_AER_CE_MASK_ADV_NONFATAL;
pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_CE_MASK, val32);
/* Enable ECRC check */
pci_cfg_read32(phb, bdfn, aercap + PCIECAP_AER_CAPCTL, &val32);
val32 |= (PCIECAP_AER_CAPCTL_ECRCG_EN |
PCIECAP_AER_CAPCTL_ECRCC_EN);
pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_CAPCTL, val32);
/* Enable all error reporting */
pci_cfg_read32(phb, bdfn, aercap + PCIECAP_AER_RERR_CMD, &val32);
val32 |= (PCIECAP_AER_RERR_CMD_FE |
PCIECAP_AER_RERR_CMD_NFE |
PCIECAP_AER_RERR_CMD_CE);
pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_RERR_CMD, val32);
#endif
}
static void phb4_switch_port_init(struct phb *phb,
struct pci_device *dev,
int ecap, int aercap)
{
uint16_t bdfn = dev->bdfn;
uint16_t val16;
uint32_t val32;
// FIXME: update AER settings for phb4
/* Enable SERR and parity checking and disable INTx */
pci_cfg_read16(phb, bdfn, PCI_CFG_CMD, &val16);
val16 |= (PCI_CFG_CMD_PERR_RESP |
PCI_CFG_CMD_SERR_EN |
PCI_CFG_CMD_INTx_DIS);
pci_cfg_write16(phb, bdfn, PCI_CFG_CMD, val16);
/* Disable partity error and enable system error */
pci_cfg_read16(phb, bdfn, PCI_CFG_BRCTL, &val16);
val16 &= ~PCI_CFG_BRCTL_PERR_RESP_EN;
val16 |= PCI_CFG_BRCTL_SERR_EN;
pci_cfg_write16(phb, bdfn, PCI_CFG_BRCTL, val16);
/* Enable reporting various errors */
if (!ecap) return;
pci_cfg_read16(phb, bdfn, ecap + PCICAP_EXP_DEVCTL, &val16);
val16 |= (PCICAP_EXP_DEVCTL_CE_REPORT |
PCICAP_EXP_DEVCTL_NFE_REPORT |
PCICAP_EXP_DEVCTL_FE_REPORT);
/* HW279570 - Disable reporting of correctable errors */
val16 &= ~PCICAP_EXP_DEVCTL_CE_REPORT;
pci_cfg_write16(phb, bdfn, ecap + PCICAP_EXP_DEVCTL, val16);
/* Unmask all unrecoverable errors */
if (!aercap) return;
pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_UE_MASK, 0x0);
/* Severity of unrecoverable errors */
if (dev->dev_type == PCIE_TYPE_SWITCH_UPPORT)
val32 = (PCIECAP_AER_UE_SEVERITY_DLLP |
PCIECAP_AER_UE_SEVERITY_SURPRISE_DOWN |
PCIECAP_AER_UE_SEVERITY_FLOW_CTL_PROT |
PCIECAP_AER_UE_SEVERITY_RECV_OVFLOW |
PCIECAP_AER_UE_SEVERITY_MALFORMED_TLP |
PCIECAP_AER_UE_SEVERITY_INTERNAL);
else
val32 = (PCIECAP_AER_UE_SEVERITY_FLOW_CTL_PROT |
PCIECAP_AER_UE_SEVERITY_INTERNAL);
pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_UE_SEVERITY, val32);
/*
* Mask various correctable errors
*/
val32 = PCIECAP_AER_CE_MASK_ADV_NONFATAL;
pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_CE_MASK, val32);
/* Enable ECRC generation and disable ECRC check */
pci_cfg_read32(phb, bdfn, aercap + PCIECAP_AER_CAPCTL, &val32);
val32 |= PCIECAP_AER_CAPCTL_ECRCG_EN;
val32 &= ~PCIECAP_AER_CAPCTL_ECRCC_EN;
pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_CAPCTL, val32);
}
static void phb4_endpoint_init(struct phb *phb,
struct pci_device *dev,
int ecap, int aercap)
{
uint16_t bdfn = dev->bdfn;
uint16_t val16;
uint32_t val32;
/* Enable SERR and parity checking */
pci_cfg_read16(phb, bdfn, PCI_CFG_CMD, &val16);
val16 |= (PCI_CFG_CMD_PERR_RESP |
PCI_CFG_CMD_SERR_EN);
pci_cfg_write16(phb, bdfn, PCI_CFG_CMD, val16);
/* Enable reporting various errors */
if (!ecap) return;
pci_cfg_read16(phb, bdfn, ecap + PCICAP_EXP_DEVCTL, &val16);
val16 &= ~PCICAP_EXP_DEVCTL_CE_REPORT;
val16 |= (PCICAP_EXP_DEVCTL_NFE_REPORT |
PCICAP_EXP_DEVCTL_FE_REPORT |
PCICAP_EXP_DEVCTL_UR_REPORT);
/* Enable ECRC generation and check */
pci_cfg_read32(phb, bdfn, aercap + PCIECAP_AER_CAPCTL, &val32);
val32 |= (PCIECAP_AER_CAPCTL_ECRCG_EN |
PCIECAP_AER_CAPCTL_ECRCC_EN);
pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_CAPCTL, val32);
}
static int64_t phb4_pcicfg_no_dstate(void *dev,
struct pci_cfg_reg_filter *pcrf,
uint32_t offset, uint32_t len,
uint32_t *data, bool write)
{
uint32_t loff = offset - pcrf->start;
/* Disable D-state change on children of the PHB. For now we
* simply block all writes to the PM control/status
*/
if (write && loff >= 4 && loff < 6)
return OPAL_SUCCESS;
return OPAL_PARTIAL;
}
static void phb4_check_device_quirks(struct phb *phb, struct pci_device *dev)
{
/* Some special adapter tweaks for devices directly under the PHB */
if (dev->primary_bus != 1)
return;
/* PM quirk */
if (!pci_has_cap(dev, PCI_CFG_CAP_ID_PM, false))
return;
pci_add_cfg_reg_filter(dev,
pci_cap(dev, PCI_CFG_CAP_ID_PM, false), 8,
PCI_REG_FLAG_WRITE,
phb4_pcicfg_no_dstate);
}
static int phb4_device_init(struct phb *phb, struct pci_device *dev,
void *data __unused)
{
int ecap, aercap;
/* Setup special device quirks */
phb4_check_device_quirks(phb, dev);
/* Common initialization for the device */
pci_device_init(phb, dev);
ecap = pci_cap(dev, PCI_CFG_CAP_ID_EXP, false);
aercap = pci_cap(dev, PCIECAP_ID_AER, true);
if (dev->dev_type == PCIE_TYPE_ROOT_PORT)
phb4_root_port_init(phb, dev, ecap, aercap);
else if (dev->dev_type == PCIE_TYPE_SWITCH_UPPORT ||
dev->dev_type == PCIE_TYPE_SWITCH_DNPORT)
phb4_switch_port_init(phb, dev, ecap, aercap);
else
phb4_endpoint_init(phb, dev, ecap, aercap);
return 0;
}
static int64_t phb4_pci_reinit(struct phb *phb, uint64_t scope, uint64_t data)
{
struct pci_device *pd;
uint16_t bdfn = data;
int ret;
if (scope != OPAL_REINIT_PCI_DEV)
return OPAL_PARAMETER;
pd = pci_find_dev(phb, bdfn);
if (!pd)
return OPAL_PARAMETER;
ret = phb4_device_init(phb, pd, NULL);
if (ret)
return OPAL_HARDWARE;
return OPAL_SUCCESS;
}
/* Clear IODA cache tables */
static void phb4_init_ioda_cache(struct phb4 *p)
{
uint32_t i;
uint64_t mbt0;
/*
* RTT and PELTV. RTE should be 0xFF's to indicate
* invalid PE# for the corresponding RID.
*
* Note: Instead we set all RTE entries to 0x00 to
* work around a problem where PE lookups might be
* done before Linux has established valid PE's
* (during PCI probing). We can revisit that once/if
* Linux has been fixed to always setup valid PEs.
*
* The value 0x00 corresponds to the default PE# Linux
* uses to check for config space freezes before it
* has assigned PE# to busses.
*
* WARNING: Additionally, we need to be careful, there's
* a HW issue, if we get an MSI on an RTT entry that is
* FF, things will go bad. We need to ensure we don't
* ever let a live FF RTT even temporarily when resetting
* for EEH etc... (HW278969).
*/
for (i = 0; i < ARRAY_SIZE(p->rte_cache); i++)
p->rte_cache[i] = PHB4_RESERVED_PE_NUM(p);
memset(p->peltv_cache, 0x0, sizeof(p->peltv_cache));
memset(p->tve_cache, 0x0, sizeof(p->tve_cache));
/* Since we configure the PHB4 with half the PE's, we need
* to give the illusion that we support only 128/256 segments
* half the segments.
*
* To achieve that, we configure *all* the M64 windows to use
* column 1 of the MDT, which is itself set so that segment 0 and 1
* map to PE0, 2 and 3 to PE1 etc...
*
* Column 0, 2 and 3 are left all 0, column 0 will be used for M32
* and configured by the OS.
*/
mbt0 = SETFIELD(IODA3_MBT0_MODE, 0ull, IODA3_MBT0_MODE_MDT);
mbt0 = SETFIELD(IODA3_MBT0_MDT_COLUMN, mbt0, 1);
for (i = 0; i < p->mbt_size; i++) {
p->mbt_cache[i][0] = mbt0;
p->mbt_cache[i][1] = 0;
}
for (i = 0; i < p->max_num_pes; i++)
p->mdt_cache[i] = SETFIELD(IODA3_MDT_PE_B, 0ull, i >> 1);
/* XXX Should we mask them ? */
memset(p->mist_cache, 0x0, sizeof(p->mist_cache));
/* Initialise M32 bar using MDT entry 0 */
p->mbt_cache[0][0] = IODA3_MBT0_TYPE_M32 |
SETFIELD(IODA3_MBT0_MODE, 0ull, IODA3_MBT0_MODE_MDT) |
SETFIELD(IODA3_MBT0_MDT_COLUMN, 0ull, 0) |
(p->mm1_base & IODA3_MBT0_BASE_ADDR);
p->mbt_cache[0][1] = IODA3_MBT1_ENABLE |
((~(M32_PCI_SIZE - 1)) & IODA3_MBT1_MASK);
}
static int64_t phb4_wait_bit(struct phb4 *p, uint32_t reg,
uint64_t mask, uint64_t want_val)
{
uint64_t val;
/* Wait for all pending TCE kills to complete
*
* XXX Add timeout...
*/
/* XXX SIMICS is nasty... */
if ((reg == PHB_TCE_KILL || reg == PHB_DMARD_SYNC) &&
chip_quirk(QUIRK_SIMICS))
return OPAL_SUCCESS;
for (;;) {
val = in_be64(p->regs + reg);
if (val == 0xffffffffffffffffull) {
/* XXX Fenced ? */
return OPAL_HARDWARE;
}
if ((val & mask) == want_val)
break;
}
return OPAL_SUCCESS;
}
static int64_t phb4_tce_kill(struct phb *phb, uint32_t kill_type,
uint64_t pe_number, uint32_t tce_size,
uint64_t dma_addr, uint32_t npages)
{
struct phb4 *p = phb_to_phb4(phb);
uint64_t val;
int64_t rc;
sync();
switch(kill_type) {
case OPAL_PCI_TCE_KILL_PAGES:
while (npages--) {
/* Wait for a slot in the HW kill queue */
rc = phb4_wait_bit(p, PHB_TCE_KILL,
PHB_TCE_KILL_ALL |
PHB_TCE_KILL_PE |
PHB_TCE_KILL_ONE, 0);
if (rc)
return rc;
val = SETFIELD(PHB_TCE_KILL_PENUM, dma_addr, pe_number);
/* Set appropriate page size */
switch(tce_size) {
case 0x1000:
if (dma_addr & 0xf000000000000fffull)
return OPAL_PARAMETER;
break;
case 0x10000:
if (dma_addr & 0xf00000000000ffffull)
return OPAL_PARAMETER;
val |= PHB_TCE_KILL_PSEL | PHB_TCE_KILL_64K;
break;
case 0x200000:
if (dma_addr & 0xf0000000001fffffull)
return OPAL_PARAMETER;
val |= PHB_TCE_KILL_PSEL | PHB_TCE_KILL_2M;
break;
case 0x40000000:
if (dma_addr & 0xf00000003fffffffull)
return OPAL_PARAMETER;
val |= PHB_TCE_KILL_PSEL | PHB_TCE_KILL_1G;
break;
default:
return OPAL_PARAMETER;
}
/* Perform kill */
out_be64(p->regs + PHB_TCE_KILL, PHB_TCE_KILL_ONE | val);
/* Next page */
dma_addr += tce_size;
}
break;
case OPAL_PCI_TCE_KILL_PE:
/* Wait for a slot in the HW kill queue */
rc = phb4_wait_bit(p, PHB_TCE_KILL,
PHB_TCE_KILL_ALL |
PHB_TCE_KILL_PE |
PHB_TCE_KILL_ONE, 0);
if (rc)
return rc;
/* Perform kill */
out_be64(p->regs + PHB_TCE_KILL, PHB_TCE_KILL_PE |
SETFIELD(PHB_TCE_KILL_PENUM, 0ull, pe_number));
break;
case OPAL_PCI_TCE_KILL_ALL:
/* Wait for a slot in the HW kill queue */
rc = phb4_wait_bit(p, PHB_TCE_KILL,
PHB_TCE_KILL_ALL |
PHB_TCE_KILL_PE |
PHB_TCE_KILL_ONE, 0);
if (rc)
return rc;
/* Perform kill */
out_be64(p->regs + PHB_TCE_KILL, PHB_TCE_KILL_ALL);
break;
default:
return OPAL_PARAMETER;
}
/* Start DMA sync process */
out_be64(p->regs + PHB_DMARD_SYNC, PHB_DMARD_SYNC_START);
/* Wait for kill to complete */
rc = phb4_wait_bit(p, PHB_Q_DMA_R, PHB_Q_DMA_R_TCE_KILL_STATUS, 0);
if (rc)
return rc;
/* Wait for DMA sync to complete */
return phb4_wait_bit(p, PHB_DMARD_SYNC,
PHB_DMARD_SYNC_COMPLETE,
PHB_DMARD_SYNC_COMPLETE);
}
/* phb4_ioda_reset - Reset the IODA tables
*
* @purge: If true, the cache is cleared and the cleared values
* are applied to HW. If false, the cached values are
* applied to HW
*
* This reset the IODA tables in the PHB. It is called at
* initialization time, on PHB reset, and can be called
* explicitly from OPAL
*/
static int64_t phb4_ioda_reset(struct phb *phb, bool purge)
{
struct phb4 *p = phb_to_phb4(phb);
uint32_t i;
uint64_t val;
if (purge) {
PHBDBG(p, "Purging all IODA tables...\n");
phb4_init_ioda_cache(p);
}
/* Init_29..30 - Errata workaround, clear PEST */
/* ... We do that further down as part of our normal IODA reset */
/* Init_31..32 - MIST */
phb4_ioda_sel(p, IODA3_TBL_MIST, 0, true);
val = in_be64(p->regs + PHB_IODA_ADDR);
val = SETFIELD(PHB_IODA_AD_MIST_PWV, val, 0xf);
out_be64(p->regs + PHB_IODA_ADDR, val);
for (i = 0; i < (p->num_irqs/4); i++)
out_be64(p->regs + PHB_IODA_DATA0, p->mist_cache[i]);
/* Init_33..34 - MRT */
phb4_ioda_sel(p, IODA3_TBL_MRT, 0, true);
for (i = 0; i < p->mrt_size; i++)
out_be64(p->regs + PHB_IODA_DATA0, 0);
/* Init_35..36 - TVT */
phb4_ioda_sel(p, IODA3_TBL_TVT, 0, true);
for (i = 0; i < p->tvt_size; i++)
out_be64(p->regs + PHB_IODA_DATA0, p->tve_cache[i]);
/* Init_37..38 - MBT */
phb4_ioda_sel(p, IODA3_TBL_MBT, 0, true);
for (i = 0; i < p->mbt_size; i++) {
out_be64(p->regs + PHB_IODA_DATA0, p->mbt_cache[i][0]);
out_be64(p->regs + PHB_IODA_DATA0, p->mbt_cache[i][1]);
}
/* Init_39..40 - MDT */
phb4_ioda_sel(p, IODA3_TBL_MDT, 0, true);
for (i = 0; i < p->max_num_pes; i++)
out_be64(p->regs + PHB_IODA_DATA0, p->mdt_cache[i]);
/* Clear RTT and PELTV */
if (p->tbl_rtt)
memcpy((void *)p->tbl_rtt, p->rte_cache, RTT_TABLE_SIZE);
if (p->tbl_peltv)
memcpy((void *)p->tbl_peltv, p->peltv_cache, p->tbl_peltv_size);
/* Clear PEST & PEEV */
for (i = 0; i < p->max_num_pes; i++) {
phb4_ioda_sel(p, IODA3_TBL_PESTA, i, false);
out_be64(p->regs + PHB_IODA_DATA0, 0);
phb4_ioda_sel(p, IODA3_TBL_PESTB, i, false);
out_be64(p->regs + PHB_IODA_DATA0, 0);
}
phb4_ioda_sel(p, IODA3_TBL_PEEV, 0, true);
for (i = 0; i < p->max_num_pes/64; i++)
out_be64(p->regs + PHB_IODA_DATA0, 0);
/* Invalidate RTE, TCE cache */
out_be64(p->regs + PHB_RTC_INVALIDATE, PHB_RTC_INVALIDATE_ALL);
return phb4_tce_kill(&p->phb, OPAL_PCI_TCE_KILL_ALL, 0, 0, 0, 0);
}
/*
* Clear anything we have in PAPR Error Injection registers. Though
* the spec says the PAPR error injection should be one-shot without
* the "sticky" bit. However, that's false according to the experiments
* I had. So we have to clear it at appropriate point in kernel to
* avoid endless frozen PE.
*/
static int64_t phb4_papr_errinjct_reset(struct phb *phb)
{
struct phb4 *p = phb_to_phb4(phb);
out_be64(p->regs + PHB_PAPR_ERR_INJ_CTL, 0x0ul);
out_be64(p->regs + PHB_PAPR_ERR_INJ_ADDR, 0x0ul);
out_be64(p->regs + PHB_PAPR_ERR_INJ_MASK, 0x0ul);
return OPAL_SUCCESS;
}