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pci.c
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pci.c
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/* Copyright 2013-2014 IBM Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
* implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <skiboot.h>
#include <cpu.h>
#include <pci.h>
#include <pci-cfg.h>
#include <pci-iov.h>
#include <pci-slot.h>
#include <pci-quirk.h>
#include <timebase.h>
#include <device.h>
#include <fsp.h>
#define MAX_PHB_ID 256
static struct phb *phbs[MAX_PHB_ID];
int last_phb_id = 0;
#define PCITRACE(_p, _bdfn, fmt, a...) \
prlog(PR_TRACE, "PHB#%04x:%02x:%02x.%x " fmt, \
(_p)->opal_id, \
((_bdfn) >> 8) & 0xff, \
((_bdfn) >> 3) & 0x1f, (_bdfn) & 0x7, ## a)
#define PCIDBG(_p, _bdfn, fmt, a...) \
prlog(PR_DEBUG, "PHB#%04x:%02x:%02x.%x " fmt, \
(_p)->opal_id, \
((_bdfn) >> 8) & 0xff, \
((_bdfn) >> 3) & 0x1f, (_bdfn) & 0x7, ## a)
#define PCINOTICE(_p, _bdfn, fmt, a...) \
prlog(PR_NOTICE, "PHB#%04x:%02x:%02x.%x " fmt, \
(_p)->opal_id, \
((_bdfn) >> 8) & 0xff, \
((_bdfn) >> 3) & 0x1f, (_bdfn) & 0x7, ## a)
#define PCIERR(_p, _bdfn, fmt, a...) \
prlog(PR_ERR, "PHB#%04x:%02x:%02x.%x " fmt, \
(_p)->opal_id, \
((_bdfn) >> 8) & 0xff, \
((_bdfn) >> 3) & 0x1f, (_bdfn) & 0x7, ## a)
/*
* Generic PCI utilities
*/
static int64_t __pci_find_cap(struct phb *phb, uint16_t bdfn,
uint8_t want, bool check_cap_indicator)
{
int64_t rc;
uint16_t stat, cap;
uint8_t pos, next;
rc = pci_cfg_read16(phb, bdfn, PCI_CFG_STAT, &stat);
if (rc)
return rc;
if (check_cap_indicator && !(stat & PCI_CFG_STAT_CAP))
return OPAL_UNSUPPORTED;
rc = pci_cfg_read8(phb, bdfn, PCI_CFG_CAP, &pos);
if (rc)
return rc;
pos &= 0xfc;
while(pos) {
rc = pci_cfg_read16(phb, bdfn, pos, &cap);
if (rc)
return rc;
if ((cap & 0xff) == want)
return pos;
next = (cap >> 8) & 0xfc;
if (next == pos) {
PCIERR(phb, bdfn, "pci_find_cap hit a loop !\n");
break;
}
pos = next;
}
return OPAL_UNSUPPORTED;
}
/* pci_find_cap - Find a PCI capability in a device config space
*
* This will return a config space offset (positive) or a negative
* error (OPAL error codes).
*
* OPAL_UNSUPPORTED is returned if the capability doesn't exist
*/
int64_t pci_find_cap(struct phb *phb, uint16_t bdfn, uint8_t want)
{
return __pci_find_cap(phb, bdfn, want, true);
}
/* pci_find_ecap - Find a PCIe extended capability in a device
* config space
*
* This will return a config space offset (positive) or a negative
* error (OPAL error code). Additionally, if the "version" argument
* is non-NULL, the capability version will be returned there.
*
* OPAL_UNSUPPORTED is returned if the capability doesn't exist
*/
int64_t pci_find_ecap(struct phb *phb, uint16_t bdfn, uint16_t want,
uint8_t *version)
{
int64_t rc;
uint32_t cap;
uint16_t off, prev = 0;
for (off = 0x100; off && off < 0x1000; off = (cap >> 20) & 0xffc ) {
if (off == prev) {
PCIERR(phb, bdfn, "pci_find_ecap hit a loop !\n");
break;
}
prev = off;
rc = pci_cfg_read32(phb, bdfn, off, &cap);
if (rc)
return rc;
if ((cap & 0xffff) == want) {
if (version)
*version = (cap >> 16) & 0xf;
return off;
}
}
return OPAL_UNSUPPORTED;
}
static void pci_init_pcie_cap(struct phb *phb, struct pci_device *pd)
{
int64_t ecap = 0;
uint16_t reg;
uint32_t val;
/* On the upstream port of PLX bridge 8724 (rev ba), PCI_STATUS
* register doesn't have capability indicator though it support
* various PCI capabilities. So we need ignore that bit when
* looking for PCI capabilities on the upstream port, which is
* limited to one that seats directly under root port.
*/
if (pd->vdid == 0x872410b5 && pd->parent && !pd->parent->parent) {
uint8_t rev;
pci_cfg_read8(phb, pd->bdfn, PCI_CFG_REV_ID, &rev);
if (rev == 0xba)
ecap = __pci_find_cap(phb, pd->bdfn,
PCI_CFG_CAP_ID_EXP, false);
else
ecap = pci_find_cap(phb, pd->bdfn, PCI_CFG_CAP_ID_EXP);
} else {
ecap = pci_find_cap(phb, pd->bdfn, PCI_CFG_CAP_ID_EXP);
}
if (ecap <= 0) {
pd->dev_type = PCIE_TYPE_LEGACY;
return;
}
pci_set_cap(pd, PCI_CFG_CAP_ID_EXP, ecap, NULL, false);
/*
* XXX We observe a problem on some PLX switches where one
* of the downstream ports appears as an upstream port, we
* fix that up here otherwise, other code will misbehave
*/
pci_cfg_read16(phb, pd->bdfn, ecap + PCICAP_EXP_CAPABILITY_REG, ®);
pd->dev_type = GETFIELD(PCICAP_EXP_CAP_TYPE, reg);
if (pd->parent && pd->parent->dev_type == PCIE_TYPE_SWITCH_UPPORT &&
pd->vdid == 0x874810b5 && pd->dev_type == PCIE_TYPE_SWITCH_UPPORT) {
PCIDBG(phb, pd->bdfn, "Fixing up bad PLX downstream port !\n");
pd->dev_type = PCIE_TYPE_SWITCH_DNPORT;
}
/* XXX Handle ARI */
if (pd->dev_type == PCIE_TYPE_SWITCH_DNPORT ||
pd->dev_type == PCIE_TYPE_ROOT_PORT)
pd->scan_map = 0x1;
/* Read MPS capability, whose maximal size is 4096 */
pci_cfg_read32(phb, pd->bdfn, ecap + PCICAP_EXP_DEVCAP, &val);
pd->mps = (128 << GETFIELD(PCICAP_EXP_DEVCAP_MPSS, val));
if (pd->mps > 4096)
pd->mps = 4096;
}
static void pci_init_aer_cap(struct phb *phb, struct pci_device *pd)
{
int64_t pos;
if (!pci_has_cap(pd, PCI_CFG_CAP_ID_EXP, false))
return;
pos = pci_find_ecap(phb, pd->bdfn, PCIECAP_ID_AER, NULL);
if (pos > 0)
pci_set_cap(pd, PCIECAP_ID_AER, pos, NULL, true);
}
static void pci_init_pm_cap(struct phb *phb, struct pci_device *pd)
{
int64_t pos;
pos = pci_find_cap(phb, pd->bdfn, PCI_CFG_CAP_ID_PM);
if (pos > 0)
pci_set_cap(pd, PCI_CFG_CAP_ID_PM, pos, NULL, false);
}
void pci_init_capabilities(struct phb *phb, struct pci_device *pd)
{
pci_init_pcie_cap(phb, pd);
pci_init_aer_cap(phb, pd);
pci_init_iov_cap(phb, pd);
pci_init_pm_cap(phb, pd);
}
static struct pci_device *pci_scan_one(struct phb *phb, struct pci_device *parent,
uint16_t bdfn)
{
struct pci_device *pd = NULL;
uint32_t retries, vdid;
int64_t rc;
uint8_t htype;
bool had_crs = false;
for (retries = 0; retries < 40; retries++) {
rc = pci_cfg_read32(phb, bdfn, PCI_CFG_VENDOR_ID, &vdid);
if (rc)
return NULL;
if (vdid == 0xffffffff || vdid == 0x00000000)
return NULL;
if (vdid != 0xffff0001)
break;
had_crs = true;
time_wait_ms(100);
}
if (vdid == 0xffff0001) {
PCIERR(phb, bdfn, "CRS timeout !\n");
return NULL;
}
if (had_crs)
PCIDBG(phb, bdfn, "Probe success after %d CRS\n", retries);
/* Perform a dummy write to the device in order for it to
* capture it's own bus number, so any subsequent error
* messages will be properly tagged
*/
pci_cfg_write32(phb, bdfn, PCI_CFG_VENDOR_ID, vdid);
pd = zalloc(sizeof(struct pci_device));
if (!pd) {
PCIERR(phb, bdfn,"Failed to allocate structure pci_device !\n");
goto fail;
}
pd->phb = phb;
pd->bdfn = bdfn;
pd->vdid = vdid;
pci_cfg_read32(phb, bdfn, PCI_CFG_SUBSYS_VENDOR_ID, &pd->sub_vdid);
pci_cfg_read32(phb, bdfn, PCI_CFG_REV_ID, &pd->class);
pd->class >>= 8;
pd->parent = parent;
list_head_init(&pd->pcrf);
list_head_init(&pd->children);
rc = pci_cfg_read8(phb, bdfn, PCI_CFG_HDR_TYPE, &htype);
if (rc) {
PCIERR(phb, bdfn, "Failed to read header type !\n");
goto fail;
}
pd->is_multifunction = !!(htype & 0x80);
pd->is_bridge = (htype & 0x7f) != 0;
pd->scan_map = 0xffffffff; /* Default */
pd->primary_bus = (bdfn >> 8);
pci_init_capabilities(phb, pd);
/* If it's a bridge, sanitize the bus numbers to avoid forwarding
*
* This will help when walking down those bridges later on
*/
if (pd->is_bridge) {
pci_cfg_write8(phb, bdfn, PCI_CFG_PRIMARY_BUS, pd->primary_bus);
pci_cfg_write8(phb, bdfn, PCI_CFG_SECONDARY_BUS, 0);
pci_cfg_write8(phb, bdfn, PCI_CFG_SUBORDINATE_BUS, 0);
}
/* XXX Need to do some basic setups, such as MPSS, MRS,
* RCB, etc...
*/
PCIDBG(phb, bdfn, "Found VID:%04x DEV:%04x TYP:%d MF%s BR%s EX%s\n",
vdid & 0xffff, vdid >> 16, pd->dev_type,
pd->is_multifunction ? "+" : "-",
pd->is_bridge ? "+" : "-",
pci_has_cap(pd, PCI_CFG_CAP_ID_EXP, false) ? "+" : "-");
/* Try to get PCI slot behind the device */
if (platform.pci_get_slot_info)
platform.pci_get_slot_info(phb, pd);
/* Put it to the child device of list of PHB or parent */
if (!parent)
list_add_tail(&phb->devices, &pd->link);
else
list_add_tail(&parent->children, &pd->link);
/*
* Call PHB hook
*/
if (phb->ops->device_init)
phb->ops->device_init(phb, pd, NULL);
return pd;
fail:
if (pd)
free(pd);
return NULL;
}
/* pci_check_clear_freeze - Probing empty slot will result in an EEH
* freeze. Currently we have a single PE mapping
* everything (default state of our backend) so
* we just check and clear the state of PE#0
*
* NOTE: We currently only handle simple PE freeze, not PHB fencing
* (or rather our backend does)
*/
static void pci_check_clear_freeze(struct phb *phb)
{
uint8_t freeze_state;
uint16_t pci_error_type, sev;
int64_t pe_number, rc;
/* Retrieve the reserved PE number */
pe_number = OPAL_PARAMETER;
if (phb->ops->get_reserved_pe_number)
pe_number = phb->ops->get_reserved_pe_number(phb);
if (pe_number < 0)
return;
/* Retrieve the frozen state */
rc = phb->ops->eeh_freeze_status(phb, pe_number, &freeze_state,
&pci_error_type, &sev, NULL);
if (rc)
return;
if (freeze_state == OPAL_EEH_STOPPED_NOT_FROZEN)
return;
/* We can't handle anything worse than an ER here */
if (sev > OPAL_EEH_SEV_NO_ERROR &&
sev < OPAL_EEH_SEV_PE_ER) {
PCIERR(phb, 0, "Fatal probe in %s error !\n", __func__);
return;
}
phb->ops->eeh_freeze_clear(phb, pe_number,
OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
}
/*
* Turn off slot's power supply if there are nothing connected for
* 2 purposes: power saving obviously and initialize the slot to
* to initial power-off state for hotplug.
*
* The power should be turned on if the downstream link of the slot
* isn't up.
*/
static void pci_slot_set_power_state(struct phb *phb,
struct pci_device *pd,
uint8_t state)
{
struct pci_slot *slot;
uint8_t cur_state;
int32_t wait = 100;
int64_t rc;
if (!pd || !pd->slot)
return;
slot = pd->slot;
if (!slot->pluggable ||
!slot->ops.get_power_state ||
!slot->ops.set_power_state)
return;
if (state == PCI_SLOT_POWER_OFF) {
/* Bail if there're something connected */
if (!list_empty(&pd->children))
return;
pci_slot_add_flags(slot, PCI_SLOT_FLAG_BOOTUP);
rc = slot->ops.get_power_state(slot, &cur_state);
if (rc != OPAL_SUCCESS) {
PCINOTICE(phb, pd->bdfn, "Error %lld getting slot power state\n", rc);
cur_state = PCI_SLOT_POWER_OFF;
}
pci_slot_remove_flags(slot, PCI_SLOT_FLAG_BOOTUP);
if (cur_state == PCI_SLOT_POWER_OFF)
return;
}
pci_slot_add_flags(slot,
(PCI_SLOT_FLAG_BOOTUP | PCI_SLOT_FLAG_ENFORCE));
rc = slot->ops.set_power_state(slot, state);
if (rc == OPAL_SUCCESS)
goto success;
if (rc != OPAL_ASYNC_COMPLETION) {
PCINOTICE(phb, pd->bdfn, "Error %lld powering %s slot\n",
rc, state == PCI_SLOT_POWER_ON ? "on" : "off");
goto error;
}
/* Wait until the operation is completed */
do {
if (slot->state == PCI_SLOT_STATE_SPOWER_DONE)
break;
check_timers(false);
time_wait_ms(10);
} while (--wait >= 0);
if (wait < 0) {
PCINOTICE(phb, pd->bdfn, "Timeout powering %s slot\n",
state == PCI_SLOT_POWER_ON ? "on" : "off");
goto error;
}
success:
PCIDBG(phb, pd->bdfn, "Powering %s hotpluggable slot\n",
state == PCI_SLOT_POWER_ON ? "on" : "off");
error:
pci_slot_remove_flags(slot,
(PCI_SLOT_FLAG_BOOTUP | PCI_SLOT_FLAG_ENFORCE));
pci_slot_set_state(slot, PCI_SLOT_STATE_NORMAL);
}
static bool pci_bridge_power_on(struct phb *phb, struct pci_device *pd)
{
int32_t ecap;
uint16_t pcie_cap, slot_sts, slot_ctl, link_ctl;
uint32_t slot_cap;
int64_t rc;
/*
* If there is a PCI slot associated with the bridge, to use
* the PCI slot's facality to power it on.
*/
if (pd->slot) {
struct pci_slot *slot = pd->slot;
uint8_t presence;
/*
* We assume the presence state is OPAL_PCI_SLOT_PRESENT
* by default. In this way, we won't miss anything when
* the operation isn't supported or hitting error upon
* retrieving it.
*/
if (slot->ops.get_presence_state) {
rc = slot->ops.get_presence_state(slot, &presence);
if (rc == OPAL_SUCCESS &&
presence == OPAL_PCI_SLOT_EMPTY)
return false;
}
/* To power it on */
pci_slot_set_power_state(phb, pd, PCI_SLOT_POWER_ON);
return true;
}
if (!pci_has_cap(pd, PCI_CFG_CAP_ID_EXP, false))
return true;
/* Check if slot is supported */
ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false);
pci_cfg_read16(phb, pd->bdfn,
ecap + PCICAP_EXP_CAPABILITY_REG, &pcie_cap);
if (!(pcie_cap & PCICAP_EXP_CAP_SLOT))
return true;
/* Check presence */
pci_cfg_read16(phb, pd->bdfn,
ecap + PCICAP_EXP_SLOTSTAT, &slot_sts);
if (!(slot_sts & PCICAP_EXP_SLOTSTAT_PDETECTST))
return false;
/* Ensure that power control is supported */
pci_cfg_read32(phb, pd->bdfn,
ecap + PCICAP_EXP_SLOTCAP, &slot_cap);
if (!(slot_cap & PCICAP_EXP_SLOTCAP_PWCTRL))
return true;
/* Read the slot control register, check if the slot is off */
pci_cfg_read16(phb, pd->bdfn, ecap + PCICAP_EXP_SLOTCTL, &slot_ctl);
PCITRACE(phb, pd->bdfn, " SLOT_CTL=%04x\n", slot_ctl);
if (slot_ctl & PCICAP_EXP_SLOTCTL_PWRCTLR) {
PCIDBG(phb, pd->bdfn, "Bridge power is off, turning on ...\n");
slot_ctl &= ~PCICAP_EXP_SLOTCTL_PWRCTLR;
slot_ctl |= SETFIELD(PCICAP_EXP_SLOTCTL_PWRI, 0, PCIE_INDIC_ON);
pci_cfg_write16(phb, pd->bdfn,
ecap + PCICAP_EXP_SLOTCTL, slot_ctl);
/* Wait a couple of seconds */
time_wait_ms(2000);
}
/* Enable link */
pci_cfg_read16(phb, pd->bdfn, ecap + PCICAP_EXP_LCTL, &link_ctl);
PCITRACE(phb, pd->bdfn, " LINK_CTL=%04x\n", link_ctl);
link_ctl &= ~PCICAP_EXP_LCTL_LINK_DIS;
pci_cfg_write16(phb, pd->bdfn, ecap + PCICAP_EXP_LCTL, link_ctl);
return true;
}
static bool pci_bridge_wait_link(struct phb *phb,
struct pci_device *pd,
bool was_reset)
{
int32_t ecap = 0;
uint32_t link_cap = 0, retries = 100;
uint16_t link_sts;
if (pci_has_cap(pd, PCI_CFG_CAP_ID_EXP, false)) {
ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false);
pci_cfg_read32(phb, pd->bdfn, ecap + PCICAP_EXP_LCAP, &link_cap);
}
/*
* If link state reporting isn't supported, wait 10 seconds
* if the downstream link was ever resetted.
*/
if (!(link_cap & PCICAP_EXP_LCAP_DL_ACT_REP)) {
if (was_reset)
time_wait_ms(1000);
return true;
}
/*
* Link state reporting is supported, wait for the link to
* come up until timeout.
*/
PCIDBG(phb, pd->bdfn, "waiting for link... \n");
while (retries--) {
pci_cfg_read16(phb, pd->bdfn,
ecap + PCICAP_EXP_LSTAT, &link_sts);
if (link_sts & PCICAP_EXP_LSTAT_DLLL_ACT)
break;
time_wait_ms(100);
}
if (!(link_sts & PCICAP_EXP_LSTAT_DLLL_ACT)) {
PCIERR(phb, pd->bdfn, "Timeout waitingfor downstream link\n");
return false;
}
/* Need another 100ms before touching the config space */
time_wait_ms(100);
PCIDBG(phb, pd->bdfn, "link is up\n");
return true;
}
/* pci_enable_bridge - Called before scanning a bridge
*
* Ensures error flags are clean, disable master abort, and
* check if the subordinate bus isn't reset, the slot is enabled
* on PCIe, etc...
*/
static bool pci_enable_bridge(struct phb *phb, struct pci_device *pd)
{
uint16_t bctl;
bool was_reset = false;
/* Disable master aborts, clear errors */
pci_cfg_read16(phb, pd->bdfn, PCI_CFG_BRCTL, &bctl);
bctl &= ~PCI_CFG_BRCTL_MABORT_REPORT;
pci_cfg_write16(phb, pd->bdfn, PCI_CFG_BRCTL, bctl);
/* PCI-E bridge, check the slot state. We don't do that on the
* root complex as this is handled separately and not all our
* RCs implement the standard register set.
*/
if ((pd->dev_type == PCIE_TYPE_ROOT_PORT && pd->primary_bus > 0) ||
pd->dev_type == PCIE_TYPE_SWITCH_DNPORT) {
if (pci_has_cap(pd, PCI_CFG_CAP_ID_EXP, false)) {
int32_t ecap;
uint32_t link_cap = 0;
uint16_t link_sts = 0;
ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false);
pci_cfg_read32(phb, pd->bdfn,
ecap + PCICAP_EXP_LCAP, &link_cap);
/*
* No need to touch the power supply if the PCIe link has
* been up. Further more, the slot presence bit is lost while
* the PCIe link is up on the specific PCI topology. In that
* case, we need ignore the slot presence bit and go ahead for
* probing. Otherwise, the NVMe adapter won't be probed.
*
* PHB3 root port, PLX switch 8748 (10b5:8748), PLX swich 9733
* (10b5:9733), PMC 8546 swtich (11f8:8546), NVMe adapter
* (1c58:0023).
*/
ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false);
pci_cfg_read32(phb, pd->bdfn,
ecap + PCICAP_EXP_LCAP, &link_cap);
pci_cfg_read16(phb, pd->bdfn,
ecap + PCICAP_EXP_LSTAT, &link_sts);
if ((link_cap & PCICAP_EXP_LCAP_DL_ACT_REP) &&
(link_sts & PCICAP_EXP_LSTAT_DLLL_ACT))
return true;
}
/* Power on the downstream slot or link */
if (!pci_bridge_power_on(phb, pd))
return false;
}
/* Clear secondary reset */
if (bctl & PCI_CFG_BRCTL_SECONDARY_RESET) {
PCIDBG(phb, pd->bdfn,
"Bridge secondary reset is on, clearing it ...\n");
bctl &= ~PCI_CFG_BRCTL_SECONDARY_RESET;
pci_cfg_write16(phb, pd->bdfn, PCI_CFG_BRCTL, bctl);
time_wait_ms(1000);
was_reset = true;
}
/* PCI-E bridge, wait for link */
if (pd->dev_type == PCIE_TYPE_ROOT_PORT ||
pd->dev_type == PCIE_TYPE_SWITCH_DNPORT) {
if (!pci_bridge_wait_link(phb, pd, was_reset))
return false;
}
/* Clear error status */
pci_cfg_write16(phb, pd->bdfn, PCI_CFG_STAT, 0xffff);
return true;
}
/* Clear up bridge resources */
static void pci_cleanup_bridge(struct phb *phb, struct pci_device *pd)
{
uint16_t cmd;
pci_cfg_write16(phb, pd->bdfn, PCI_CFG_IO_BASE_U16, 0xffff);
pci_cfg_write8(phb, pd->bdfn, PCI_CFG_IO_BASE, 0xf0);
pci_cfg_write16(phb, pd->bdfn, PCI_CFG_IO_LIMIT_U16, 0);
pci_cfg_write8(phb, pd->bdfn, PCI_CFG_IO_LIMIT, 0);
pci_cfg_write16(phb, pd->bdfn, PCI_CFG_MEM_BASE, 0xfff0);
pci_cfg_write16(phb, pd->bdfn, PCI_CFG_MEM_LIMIT, 0);
pci_cfg_write32(phb, pd->bdfn, PCI_CFG_PREF_MEM_BASE_U32, 0xffffffff);
pci_cfg_write16(phb, pd->bdfn, PCI_CFG_PREF_MEM_BASE, 0xfff0);
pci_cfg_write32(phb, pd->bdfn, PCI_CFG_PREF_MEM_LIMIT_U32, 0);
pci_cfg_write16(phb, pd->bdfn, PCI_CFG_PREF_MEM_LIMIT, 0);
/* Note: This is a bit fishy but since we have closed all the
* bridge windows above, it shouldn't be a problem. Basically
* we enable Memory, IO and Bus Master on the bridge because
* some versions of Linux will fail to do it themselves.
*/
pci_cfg_read16(phb, pd->bdfn, PCI_CFG_CMD, &cmd);
cmd |= PCI_CFG_CMD_IO_EN | PCI_CFG_CMD_MEM_EN;
cmd |= PCI_CFG_CMD_BUS_MASTER_EN;
pci_cfg_write16(phb, pd->bdfn, PCI_CFG_CMD, cmd);
}
/* Remove all subordinate PCI devices leading from the indicated
* PCI bus. It's used to remove all PCI devices behind one PCI
* slot at unplugging time
*/
void pci_remove_bus(struct phb *phb, struct list_head *list)
{
struct pci_device *pd, *tmp;
list_for_each_safe(list, pd, tmp, link) {
pci_remove_bus(phb, &pd->children);
if (phb->ops->device_remove)
phb->ops->device_remove(phb, pd);
/* Release device node and PCI slot */
if (pd->dn)
dt_free(pd->dn);
if (pd->slot)
free(pd->slot);
/* Remove from parent list and release itself */
list_del(&pd->link);
free(pd);
}
}
/* Perform a recursive scan of the bus at bus_number populating
* the list passed as an argument. This also performs the bus
* numbering, so it returns the largest bus number that was
* assigned.
*
* Note: Eventually this might want to access some VPD information
* in order to know what slots to scan and what not etc..
*
* XXX NOTE: We might want to enable ARI along the way...
*
* XXX NOTE: We might also want to setup the PCIe MPS/MRSS properly
* here as Linux may or may not do it
*/
uint8_t pci_scan_bus(struct phb *phb, uint8_t bus, uint8_t max_bus,
struct list_head *list, struct pci_device *parent,
bool scan_downstream)
{
struct pci_device *pd = NULL, *rc = NULL;
uint8_t dev, fn, next_bus, max_sub, save_max;
uint32_t scan_map;
bool use_max;
/* Decide what to scan */
scan_map = parent ? parent->scan_map : phb->scan_map;
/* Do scan */
for (dev = 0; dev < 32; dev++) {
if (!(scan_map & (1ul << dev)))
continue;
/* Scan the device */
pd = pci_scan_one(phb, parent, (bus << 8) | (dev << 3));
pci_check_clear_freeze(phb);
if (!pd)
continue;
/* Record RC when its downstream link is down */
if (!scan_downstream && dev == 0 && !rc)
rc = pd;
/* XXX Handle ARI */
if (!pd->is_multifunction)
continue;
for (fn = 1; fn < 8; fn++) {
pd = pci_scan_one(phb, parent,
((uint16_t)bus << 8) | (dev << 3) | fn);
pci_check_clear_freeze(phb);
}
}
/* Reserve all possible buses if RC's downstream link is down
* if PCI hotplug is supported.
*/
if (rc && rc->slot && rc->slot->pluggable) {
next_bus = phb->ops->choose_bus(phb, rc, bus + 1,
&max_bus, &use_max);
rc->secondary_bus = next_bus;
rc->subordinate_bus = max_bus;
pci_cfg_write8(phb, rc->bdfn, PCI_CFG_SECONDARY_BUS,
rc->secondary_bus);
pci_cfg_write8(phb, rc->bdfn, PCI_CFG_SUBORDINATE_BUS,
rc->subordinate_bus);
}
/*
* We only scan downstream if instructed to do so by the
* caller. Typically we avoid the scan when we know the
* link is down already, which happens for the top level
* root complex, and avoids a long secondary timeout
*/
if (!scan_downstream) {
list_for_each(list, pd, link)
pci_slot_set_power_state(phb, pd, PCI_SLOT_POWER_OFF);
return bus;
}
next_bus = bus + 1;
max_sub = bus;
save_max = max_bus;
/* Scan down bridges */
list_for_each(list, pd, link) {
bool do_scan;
if (!pd->is_bridge)
continue;
/* We need to figure out a new bus number to start from.
*
* This can be tricky due to our HW constraints which differ
* from bridge to bridge so we are going to let the phb
* driver decide what to do. This can return us a maximum
* bus number to assign as well
*
* This function will:
*
* - Return the bus number to use as secondary for the
* bridge or 0 for a failure
*
* - "max_bus" will be adjusted to represent the max
* subordinate that can be associated with the downstream
* device
*
* - "use_max" will be set to true if the returned max_bus
* *must* be used as the subordinate bus number of that
* bridge (when we need to give aligned powers of two's
* on P7IOC). If is is set to false, we just adjust the
* subordinate bus number based on what we probed.
*
*/
max_bus = save_max;
next_bus = phb->ops->choose_bus(phb, pd, next_bus,
&max_bus, &use_max);
/* Configure the bridge with the returned values */
if (next_bus <= bus) {
PCIERR(phb, pd->bdfn, "Out of bus numbers !\n");
max_bus = next_bus = 0; /* Failure case */
}
pd->secondary_bus = next_bus;
pd->subordinate_bus = max_bus;
pci_cfg_write8(phb, pd->bdfn, PCI_CFG_SECONDARY_BUS, next_bus);
pci_cfg_write8(phb, pd->bdfn, PCI_CFG_SUBORDINATE_BUS, max_bus);
if (!next_bus)
break;
PCIDBG(phb, pd->bdfn, "Bus %02x..%02x %s scanning...\n",
next_bus, max_bus, use_max ? "[use max]" : "");
/* Clear up bridge resources */
pci_cleanup_bridge(phb, pd);
/* Configure the bridge. This will enable power to the slot
* if it's currently disabled, lift reset, etc...
*
* Return false if we know there's nothing behind the bridge
*/
do_scan = pci_enable_bridge(phb, pd);
/* Perform recursive scan */
if (do_scan) {
max_sub = pci_scan_bus(phb, next_bus, max_bus,
&pd->children, pd, true);
} else if (!use_max) {
/* Empty bridge. We leave room for hotplug
* slots if the downstream port is pluggable.
*/
if (pd->slot && !pd->slot->pluggable)
max_sub = next_bus;
else {
max_sub = next_bus + 4;
if (max_sub > max_bus)
max_sub = max_bus;
}
}
/* Update the max subordinate as described previously */
if (use_max)
max_sub = max_bus;
pd->subordinate_bus = max_sub;
pci_cfg_write8(phb, pd->bdfn, PCI_CFG_SUBORDINATE_BUS, max_sub);
next_bus = max_sub + 1;
pci_slot_set_power_state(phb, pd, PCI_SLOT_POWER_OFF);
}
return max_sub;
}
static int pci_get_mps(struct phb *phb,
struct pci_device *pd, void *userdata)
{
uint32_t *mps = (uint32_t *)userdata;
/* Only check PCI device that had MPS capacity */
if (phb && pd && pd->mps && *mps > pd->mps)
*mps = pd->mps;
return 0;
}
static int pci_configure_mps(struct phb *phb,
struct pci_device *pd,
void *userdata __unused)
{
uint32_t ecap, aercap, mps;
uint16_t val;
assert(phb);
assert(pd);
/* If the MPS isn't acceptable one, bail immediately */
mps = phb->mps;
if (mps < 128 || mps > 4096)
return 1;
/* Retrieve PCIe and AER capability */
ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false);
aercap = pci_cap(pd, PCIECAP_ID_AER, true);
/* PCIe device always has MPS capacity */
if (pd->mps) {
mps = ilog2(mps) - 7;
pci_cfg_read16(phb, pd->bdfn, ecap + PCICAP_EXP_DEVCTL, &val);
val = SETFIELD(PCICAP_EXP_DEVCTL_MPS, val, mps);
pci_cfg_write16(phb, pd->bdfn, ecap + PCICAP_EXP_DEVCTL, val);
}
/* Changing MPS on upstream PCI bridge might cause some error
* bits in PCIe and AER capability. To clear them to avoid
* confusion.
*/
if (aercap) {
pci_cfg_write32(phb, pd->bdfn, aercap + PCIECAP_AER_UE_STATUS,
0xffffffff);
pci_cfg_write32(phb, pd->bdfn, aercap + PCIECAP_AER_CE_STATUS,
0xffffffff);
}
if (ecap)
pci_cfg_write16(phb, pd->bdfn, ecap + PCICAP_EXP_DEVSTAT, 0xf);
return 0;
}
static void pci_disable_completion_timeout(struct phb *phb, struct pci_device *pd)
{
uint32_t ecap;
uint32_t val;
/* PCIE capability required */
if (!pci_has_cap(pd, PCI_CFG_CAP_ID_EXP, false))
return;
/* Check if it has capability to disable completion timeout */
ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false);
pci_cfg_read32(phb, pd->bdfn, ecap + PCIECAP_EXP_DCAP2, &val);
if (!(val & PCICAP_EXP_DCAP2_CMPTOUT_DIS))
return;
/* Disable completion timeout without more check */
pci_cfg_read32(phb, pd->bdfn, ecap + PCICAP_EXP_DCTL2, &val);
val |= PCICAP_EXP_DCTL2_CMPTOUT_DIS;
pci_cfg_write32(phb, pd->bdfn, ecap + PCICAP_EXP_DCTL2, val);
}
void pci_device_init(struct phb *phb, struct pci_device *pd)
{
pci_configure_mps(phb, pd, NULL);
pci_disable_completion_timeout(phb, pd);
}
static void pci_reset_phb(void *data)
{
struct phb *phb = data;
struct pci_slot *slot = phb->slot;
int64_t rc;
if (!slot || !slot->ops.freset) {
PCINOTICE(phb, 0, "Cannot issue fundamental reset\n");
return;
}
pci_slot_add_flags(slot, PCI_SLOT_FLAG_BOOTUP);
rc = slot->ops.freset(slot);
while (rc > 0) {
time_wait(rc);
rc = slot->ops.run_sm(slot);
}
pci_slot_remove_flags(slot, PCI_SLOT_FLAG_BOOTUP);
if (rc < 0)
PCIERR(phb, 0, "Error %lld fundamental resetting\n", rc);
}
static void pci_scan_phb(void *data)
{
struct phb *phb = data;
struct pci_slot *slot = phb->slot;
uint8_t link;
uint32_t mps = 0xffffffff;
int64_t rc;
if (!slot || !slot->ops.get_link_state) {
PCIERR(phb, 0, "Cannot query link status\n");
link = 0;
} else {
rc = slot->ops.get_link_state(slot, &link);
if (rc != OPAL_SUCCESS) {
PCIERR(phb, 0, "Error %lld querying link status\n",
rc);
link = 0;
}
}
if (!link)
PCIDBG(phb, 0, "Link down\n");
else