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phb3.c
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phb3.c
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/* Copyright 2013-2014 IBM Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
* implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <skiboot.h>
#include <io.h>
#include <timebase.h>
#include <pci-cfg.h>
#include <pci.h>
#include <pci-slot.h>
#include <vpd.h>
#include <interrupts.h>
#include <opal.h>
#include <cpu.h>
#include <device.h>
#include <ccan/str/str.h>
#include <ccan/array_size/array_size.h>
#include <xscom.h>
#include <affinity.h>
#include <phb3.h>
#include <phb3-regs.h>
#include <capp.h>
#include <fsp.h>
#include <chip.h>
#include <chiptod.h>
/* Enable this to disable error interrupts for debug purposes */
#undef DISABLE_ERR_INTS
static void phb3_init_hw(struct phb3 *p, bool first_init);
#define PHBDBG(p, fmt, a...) prlog(PR_DEBUG, "PHB#%04x: " fmt, \
(p)->phb.opal_id, ## a)
#define PHBINF(p, fmt, a...) prlog(PR_INFO, "PHB#%04x: " fmt, \
(p)->phb.opal_id, ## a)
#define PHBERR(p, fmt, a...) prlog(PR_ERR, "PHB#%04x: " fmt, \
(p)->phb.opal_id, ## a)
#define PE_CAPP_EN 0x9013c03
#define PE_REG_OFFSET(p) \
((PHB3_IS_NAPLES(p) && (p)->index) ? 0x40 : 0x0)
/* Helper to select an IODA table entry */
static inline void phb3_ioda_sel(struct phb3 *p, uint32_t table,
uint32_t addr, bool autoinc)
{
out_be64(p->regs + PHB_IODA_ADDR,
(autoinc ? PHB_IODA_AD_AUTOINC : 0) |
SETFIELD(PHB_IODA_AD_TSEL, 0ul, table) |
SETFIELD(PHB_IODA_AD_TADR, 0ul, addr));
}
/* Check if AIB is fenced via PBCQ NFIR */
static bool phb3_fenced(struct phb3 *p)
{
uint64_t nfir;
/* We still probably has crazy xscom */
xscom_read(p->chip_id, p->pe_xscom + 0x0, &nfir);
if (nfir & PPC_BIT(16)) {
p->flags |= PHB3_AIB_FENCED;
p->state = PHB3_STATE_FENCED;
return true;
}
return false;
}
static int64_t phb3_pcicfg_rc_pref_window(void *dev __unused,
struct pci_cfg_reg_filter *pcrf,
uint32_t offset, uint32_t len,
uint32_t *data, bool write)
{
uint8_t *pdata;
uint32_t i;
/* Cache whatever we received */
if (write) {
pdata = &pcrf->data[offset - pcrf->start];
for (i = 0; i < len; i++, pdata++)
*pdata = (uint8_t)(*data >> (8 * i));
return OPAL_SUCCESS;
}
/* Return whatever we cached */
*data = 0;
pdata = &pcrf->data[offset - pcrf->start + len - 1];
for (i = len; i > 0; i--, pdata--) {
*data = (*data) << 8;
if (offset + i == PCI_CFG_PREF_MEM_BASE) {
*data |= ((*pdata & 0xf0) | 0x1);
continue;
}
*data |= *pdata;
}
return OPAL_SUCCESS;
}
/*
* Configuration space access
*
* The PHB lock is assumed to be already held
*/
static int64_t phb3_pcicfg_check(struct phb3 *p, uint32_t bdfn,
uint32_t offset, uint32_t size,
uint8_t *pe)
{
uint32_t sm = size - 1;
if (offset > 0xfff || bdfn > 0xffff)
return OPAL_PARAMETER;
if (offset & sm)
return OPAL_PARAMETER;
/* The root bus only has a device at 0 and we get into an
* error state if we try to probe beyond that, so let's
* avoid that and just return an error to Linux
*/
if ((bdfn >> 8) == 0 && (bdfn & 0xff))
return OPAL_HARDWARE;
/* Check PHB state */
if (p->state == PHB3_STATE_BROKEN)
return OPAL_HARDWARE;
/* Fetch the PE# from cache */
*pe = p->rte_cache[bdfn];
return OPAL_SUCCESS;
}
static void phb3_link_update(struct phb *phb, uint16_t data)
{
struct phb3 *p = phb_to_phb3(phb);
uint32_t new_spd, new_wid;
uint32_t old_spd, old_wid;
uint16_t old_data;
uint64_t lreg;
int i;
/* Read the old speed and width */
pci_cfg_read16(phb, 0, 0x5a, &old_data);
/* Decode the register values */
new_spd = data & PCICAP_EXP_LSTAT_SPEED;
new_wid = (data & PCICAP_EXP_LSTAT_WIDTH) >> 4;
old_spd = old_data & PCICAP_EXP_LSTAT_SPEED;
old_wid = (old_data & PCICAP_EXP_LSTAT_WIDTH) >> 4;
/* Apply maximums */
if (new_wid > 16)
new_wid = 16;
if (new_wid < 1)
new_wid = 1;
if (new_spd > 3)
new_spd = 3;
if (new_spd < 1)
new_spd = 1;
PHBINF(p, "Link change request: speed %d->%d, width %d->%d\n",
old_spd, new_spd, old_wid, new_wid);
/* Check if width needs to be changed */
if (old_wid != new_wid) {
PHBINF(p, "Changing width...\n");
lreg = in_be64(p->regs + PHB_PCIE_LINK_MANAGEMENT);
lreg = SETFIELD(PHB_PCIE_LM_TGT_LINK_WIDTH, lreg, new_wid);
lreg |= PHB_PCIE_LM_CHG_LINK_WIDTH;
out_be64(p->regs + PHB_PCIE_LINK_MANAGEMENT, lreg);
for (i=0; i<10;i++) {
lreg = in_be64(p->regs + PHB_PCIE_LINK_MANAGEMENT);
if (lreg & PHB_PCIE_LM_DL_WCHG_PENDING)
break;
time_wait_ms_nopoll(1);
}
if (!(lreg & PHB_PCIE_LM_DL_WCHG_PENDING))
PHBINF(p, "Timeout waiting for speed change start\n");
for (i=0; i<100;i++) {
lreg = in_be64(p->regs + PHB_PCIE_LINK_MANAGEMENT);
if (!(lreg & PHB_PCIE_LM_DL_WCHG_PENDING))
break;
time_wait_ms_nopoll(1);
}
if (lreg & PHB_PCIE_LM_DL_WCHG_PENDING)
PHBINF(p, "Timeout waiting for speed change end\n");
}
/* Check if speed needs to be changed */
if (old_spd != new_spd) {
PHBINF(p, "Changing speed...\n");
lreg = in_be64(p->regs + PHB_PCIE_LINK_MANAGEMENT);
if (lreg & PPC_BIT(19)) {
uint16_t lctl2;
PHBINF(p, " Bit19 set ! working around...\n");
pci_cfg_read16(phb, 0, 0x78, &lctl2);
PHBINF(p, " LCTL2=%04x\n", lctl2);
lctl2 &= ~PCICAP_EXP_LCTL2_HWAUTSPDIS;
pci_cfg_write16(phb, 0, 0x78, lctl2);
}
lreg = in_be64(p->regs + PHB_PCIE_LINK_MANAGEMENT);
lreg = SETFIELD(PHB_PCIE_LM_TGT_SPEED, lreg, new_spd);
lreg |= PHB_PCIE_LM_CHG_SPEED;
out_be64(p->regs + PHB_PCIE_LINK_MANAGEMENT, lreg);
}
}
static void phb3_pcicfg_filter(struct phb *phb, uint32_t bdfn,
uint32_t offset, uint32_t len,
uint32_t *data, bool write)
{
struct pci_device *pd;
struct pci_cfg_reg_filter *pcrf;
uint32_t flags;
/* Hack for link speed changes. We intercept attempts at writing
* the link control/status register
*/
if (bdfn == 0 && write && len == 4 && offset == 0x58) {
phb3_link_update(phb, (*data) >> 16);
return;
}
if (bdfn == 0 && write && len == 2 && offset == 0x5a) {
phb3_link_update(phb, *(uint16_t *)data);
return;
}
if (!pci_device_has_cfg_reg_filters(phb, bdfn))
return;
pd = pci_find_dev(phb, bdfn);
pcrf = pd ? pci_find_cfg_reg_filter(pd, offset, len) : NULL;
if (!pcrf || !pcrf->func)
return;
flags = write ? PCI_REG_FLAG_WRITE : PCI_REG_FLAG_READ;
if ((pcrf->flags & flags) != flags)
return;
pcrf->func(pd, pcrf, offset, len, data, write);
}
#define PHB3_PCI_CFG_READ(size, type) \
static int64_t phb3_pcicfg_read##size(struct phb *phb, uint32_t bdfn, \
uint32_t offset, type *data) \
{ \
struct phb3 *p = phb_to_phb3(phb); \
uint64_t addr, val64; \
int64_t rc; \
uint8_t pe; \
bool use_asb = false; \
\
/* Initialize data in case of error */ \
*data = (type)0xffffffff; \
\
rc = phb3_pcicfg_check(p, bdfn, offset, sizeof(type), &pe); \
if (rc) \
return rc; \
\
if (p->flags & PHB3_AIB_FENCED) { \
if (!(p->flags & PHB3_CFG_USE_ASB)) \
return OPAL_HARDWARE; \
use_asb = true; \
} else if ((p->flags & PHB3_CFG_BLOCKED) && bdfn != 0) { \
return OPAL_HARDWARE; \
} \
\
addr = PHB_CA_ENABLE; \
addr = SETFIELD(PHB_CA_BDFN, addr, bdfn); \
addr = SETFIELD(PHB_CA_REG, addr, offset); \
addr = SETFIELD(PHB_CA_PE, addr, pe); \
if (use_asb) { \
phb3_write_reg_asb(p, PHB_CONFIG_ADDRESS, addr); \
sync(); \
val64 = bswap_64(phb3_read_reg_asb(p, PHB_CONFIG_DATA)); \
*data = (type)(val64 >> (8 * (offset & (4 - sizeof(type))))); \
} else { \
out_be64(p->regs + PHB_CONFIG_ADDRESS, addr); \
*data = in_le##size(p->regs + PHB_CONFIG_DATA + \
(offset & (4 - sizeof(type)))); \
} \
\
phb3_pcicfg_filter(phb, bdfn, offset, sizeof(type), \
(uint32_t *)data, false); \
\
return OPAL_SUCCESS; \
}
#define PHB3_PCI_CFG_WRITE(size, type) \
static int64_t phb3_pcicfg_write##size(struct phb *phb, uint32_t bdfn, \
uint32_t offset, type data) \
{ \
struct phb3 *p = phb_to_phb3(phb); \
uint64_t addr, val64 = 0; \
int64_t rc; \
uint8_t pe; \
bool use_asb = false; \
\
rc = phb3_pcicfg_check(p, bdfn, offset, sizeof(type), &pe); \
if (rc) \
return rc; \
\
if (p->flags & PHB3_AIB_FENCED) { \
if (!(p->flags & PHB3_CFG_USE_ASB)) \
return OPAL_HARDWARE; \
use_asb = true; \
} else if ((p->flags & PHB3_CFG_BLOCKED) && bdfn != 0) { \
return OPAL_HARDWARE; \
} \
\
addr = PHB_CA_ENABLE; \
addr = SETFIELD(PHB_CA_BDFN, addr, bdfn); \
addr = SETFIELD(PHB_CA_REG, addr, offset); \
addr = SETFIELD(PHB_CA_PE, addr, pe); \
if (use_asb) { \
val64 = data; \
val64 = bswap_64(val64 << 8 * (offset & (4 - sizeof(type)))); \
phb3_write_reg_asb(p, PHB_CONFIG_ADDRESS, addr); \
sync(); \
phb3_write_reg_asb(p, PHB_CONFIG_DATA, val64); \
} else { \
out_be64(p->regs + PHB_CONFIG_ADDRESS, addr); \
out_le##size(p->regs + PHB_CONFIG_DATA + \
(offset & (4 - sizeof(type))), data); \
} \
\
phb3_pcicfg_filter(phb, bdfn, offset, sizeof(type), \
(uint32_t *)&data, true); \
\
return OPAL_SUCCESS; \
}
PHB3_PCI_CFG_READ(8, u8)
PHB3_PCI_CFG_READ(16, u16)
PHB3_PCI_CFG_READ(32, u32)
PHB3_PCI_CFG_WRITE(8, u8)
PHB3_PCI_CFG_WRITE(16, u16)
PHB3_PCI_CFG_WRITE(32, u32)
static uint8_t phb3_choose_bus(struct phb *phb __unused,
struct pci_device *bridge __unused,
uint8_t candidate, uint8_t *max_bus __unused,
bool *use_max)
{
/* Use standard bus number selection */
*use_max = false;
return candidate;
}
static int64_t phb3_get_reserved_pe_number(struct phb *phb __unused)
{
return PHB3_RESERVED_PE_NUM;
}
static inline void phb3_enable_ecrc(struct phb *phb, bool enable)
{
struct phb3 *p = phb_to_phb3(phb);
uint32_t ctl;
if (p->aercap <= 0)
return;
pci_cfg_read32(phb, 0, p->aercap + PCIECAP_AER_CAPCTL, &ctl);
if (enable) {
ctl |= (PCIECAP_AER_CAPCTL_ECRCG_EN |
PCIECAP_AER_CAPCTL_ECRCC_EN);
} else {
ctl &= ~(PCIECAP_AER_CAPCTL_ECRCG_EN |
PCIECAP_AER_CAPCTL_ECRCC_EN);
}
pci_cfg_write32(phb, 0, p->aercap + PCIECAP_AER_CAPCTL, ctl);
}
static void phb3_root_port_init(struct phb *phb, struct pci_device *dev,
int ecap, int aercap)
{
struct phb3 *p = phb_to_phb3(phb);
uint16_t bdfn = dev->bdfn;
uint16_t val16;
uint32_t val32;
/* Use PHB's callback so that the UTL events will be masked
* or unmasked when the link is down or up.
*/
if (dev->slot && dev->slot->ops.prepare_link_change &&
phb->slot && phb->slot->ops.prepare_link_change)
dev->slot->ops.prepare_link_change =
phb->slot->ops.prepare_link_change;
/* Mask UTL link down event if root slot supports surprise
* hotplug as the event should be handled by hotplug driver
* instead of EEH subsystem.
*/
if (dev->slot && dev->slot->surprise_pluggable)
out_be64(p->regs + UTL_PCIE_PORT_IRQ_EN, 0xad42800000000000);
/* Enable SERR and parity checking */
pci_cfg_read16(phb, bdfn, PCI_CFG_CMD, &val16);
val16 |= (PCI_CFG_CMD_SERR_EN | PCI_CFG_CMD_PERR_RESP);
pci_cfg_write16(phb, bdfn, PCI_CFG_CMD, val16);
/* Enable reporting various errors */
if (!ecap) return;
pci_cfg_read16(phb, bdfn, ecap + PCICAP_EXP_DEVCTL, &val16);
val16 |= (PCICAP_EXP_DEVCTL_CE_REPORT |
PCICAP_EXP_DEVCTL_NFE_REPORT |
PCICAP_EXP_DEVCTL_FE_REPORT |
PCICAP_EXP_DEVCTL_UR_REPORT);
pci_cfg_write16(phb, bdfn, ecap + PCICAP_EXP_DEVCTL, val16);
if (!aercap) return;
/* Mask various unrecoverable errors. The link surprise down
* event should be masked when its PCI slot support surprise
* hotplug. The link surprise down event should be handled by
* PCI hotplug driver instead of EEH subsystem.
*/
pci_cfg_read32(phb, bdfn, aercap + PCIECAP_AER_UE_MASK, &val32);
val32 |= (PCIECAP_AER_UE_MASK_POISON_TLP |
PCIECAP_AER_UE_MASK_COMPL_TIMEOUT |
PCIECAP_AER_UE_MASK_COMPL_ABORT |
PCIECAP_AER_UE_MASK_ECRC);
if (dev->slot && dev->slot->surprise_pluggable)
val32 |= PCIECAP_AER_UE_MASK_SURPRISE_DOWN;
pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_UE_MASK, val32);
/* Report various unrecoverable errors as fatal errors */
pci_cfg_read32(phb, bdfn, aercap + PCIECAP_AER_UE_SEVERITY, &val32);
val32 |= (PCIECAP_AER_UE_SEVERITY_DLLP |
PCIECAP_AER_UE_SEVERITY_SURPRISE_DOWN |
PCIECAP_AER_UE_SEVERITY_FLOW_CTL_PROT |
PCIECAP_AER_UE_SEVERITY_UNEXP_COMPL |
PCIECAP_AER_UE_SEVERITY_RECV_OVFLOW |
PCIECAP_AER_UE_SEVERITY_MALFORMED_TLP);
pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_UE_SEVERITY, val32);
/* Mask various recoverable errors */
pci_cfg_read32(phb, bdfn, aercap + PCIECAP_AER_CE_MASK, &val32);
val32 |= PCIECAP_AER_CE_MASK_ADV_NONFATAL;
pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_CE_MASK, val32);
/* Enable ECRC check */
phb3_enable_ecrc(phb, true);
/* Enable all error reporting */
pci_cfg_read32(phb, bdfn, aercap + PCIECAP_AER_RERR_CMD, &val32);
val32 |= (PCIECAP_AER_RERR_CMD_FE |
PCIECAP_AER_RERR_CMD_NFE |
PCIECAP_AER_RERR_CMD_CE);
pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_RERR_CMD, val32);
}
static void phb3_switch_port_init(struct phb *phb,
struct pci_device *dev,
int ecap, int aercap)
{
struct phb3 *p = phb_to_phb3(phb);
uint16_t bdfn = dev->bdfn;
uint16_t val16;
uint32_t val32;
/* Enable SERR and parity checking and disable INTx */
pci_cfg_read16(phb, bdfn, PCI_CFG_CMD, &val16);
val16 |= (PCI_CFG_CMD_PERR_RESP |
PCI_CFG_CMD_SERR_EN |
PCI_CFG_CMD_INTx_DIS);
pci_cfg_write16(phb, bdfn, PCI_CFG_CMD, val16);
/* Disable partity error and enable system error */
pci_cfg_read16(phb, bdfn, PCI_CFG_BRCTL, &val16);
val16 &= ~PCI_CFG_BRCTL_PERR_RESP_EN;
val16 |= PCI_CFG_BRCTL_SERR_EN;
pci_cfg_write16(phb, bdfn, PCI_CFG_BRCTL, val16);
/* Enable reporting various errors */
if (!ecap) return;
pci_cfg_read16(phb, bdfn, ecap + PCICAP_EXP_DEVCTL, &val16);
val16 |= (PCICAP_EXP_DEVCTL_CE_REPORT |
PCICAP_EXP_DEVCTL_NFE_REPORT |
PCICAP_EXP_DEVCTL_FE_REPORT);
/* HW279570 - Disable reporting of correctable errors */
val16 &= ~PCICAP_EXP_DEVCTL_CE_REPORT;
pci_cfg_write16(phb, bdfn, ecap + PCICAP_EXP_DEVCTL, val16);
/* Unmask all unrecoverable errors for upstream port. For
* downstream port, the surprise link down is masked because
* it should be handled by hotplug driver instead of EEH
* subsystem.
*/
if (!aercap) return;
if (dev->dev_type == PCIE_TYPE_SWITCH_DNPORT &&
dev->slot && dev->slot->surprise_pluggable)
pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_UE_MASK,
PCIECAP_AER_UE_MASK_SURPRISE_DOWN);
else
pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_UE_MASK, 0x0);
/* Severity of unrecoverable errors */
if (dev->dev_type == PCIE_TYPE_SWITCH_UPPORT)
val32 = (PCIECAP_AER_UE_SEVERITY_DLLP |
PCIECAP_AER_UE_SEVERITY_SURPRISE_DOWN |
PCIECAP_AER_UE_SEVERITY_FLOW_CTL_PROT |
PCIECAP_AER_UE_SEVERITY_RECV_OVFLOW |
PCIECAP_AER_UE_SEVERITY_MALFORMED_TLP |
PCIECAP_AER_UE_SEVERITY_INTERNAL);
else
val32 = (PCIECAP_AER_UE_SEVERITY_FLOW_CTL_PROT |
PCIECAP_AER_UE_SEVERITY_INTERNAL);
pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_UE_SEVERITY, val32);
/*
* Mask various correctable errors
*
* On Murano and Venice DD1.0 we disable emission of corrected
* error messages to the PHB completely to workaround errata
* HW257476 causing the loss of tags.
*/
if (p->rev < PHB3_REV_MURANO_DD20)
val32 = 0xffffffff;
else
val32 = PCIECAP_AER_CE_MASK_ADV_NONFATAL;
pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_CE_MASK, val32);
/* Enable ECRC generation and disable ECRC check */
pci_cfg_read32(phb, bdfn, aercap + PCIECAP_AER_CAPCTL, &val32);
val32 |= PCIECAP_AER_CAPCTL_ECRCG_EN;
val32 &= ~PCIECAP_AER_CAPCTL_ECRCC_EN;
pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_CAPCTL, val32);
}
static void phb3_endpoint_init(struct phb *phb,
struct pci_device *dev,
int ecap, int aercap)
{
struct phb3 *p = phb_to_phb3(phb);
uint16_t bdfn = dev->bdfn;
uint16_t val16;
uint32_t val32;
/* Enable SERR and parity checking */
pci_cfg_read16(phb, bdfn, PCI_CFG_CMD, &val16);
val16 |= (PCI_CFG_CMD_PERR_RESP |
PCI_CFG_CMD_SERR_EN);
pci_cfg_write16(phb, bdfn, PCI_CFG_CMD, val16);
/* Enable reporting various errors */
if (!ecap) return;
pci_cfg_read16(phb, bdfn, ecap + PCICAP_EXP_DEVCTL, &val16);
val16 &= ~PCICAP_EXP_DEVCTL_CE_REPORT;
val16 |= (PCICAP_EXP_DEVCTL_NFE_REPORT |
PCICAP_EXP_DEVCTL_FE_REPORT |
PCICAP_EXP_DEVCTL_UR_REPORT);
/* HW279570 - Disable reporting of correctable errors */
val16 &= ~PCICAP_EXP_DEVCTL_CE_REPORT;
pci_cfg_write16(phb, bdfn, ecap + PCICAP_EXP_DEVCTL, val16);
/*
* On Murano and Venice DD1.0 we disable emission of corrected
* error messages to the PHB completely to workaround errata
* HW257476 causing the loss of tags.
*/
if (p->rev < PHB3_REV_MURANO_DD20)
pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_CE_MASK,
0xffffffff);
/* Enable ECRC generation and check */
pci_cfg_read32(phb, bdfn, aercap + PCIECAP_AER_CAPCTL, &val32);
val32 |= (PCIECAP_AER_CAPCTL_ECRCG_EN |
PCIECAP_AER_CAPCTL_ECRCC_EN);
pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_CAPCTL, val32);
}
static void phb3_check_device_quirks(struct phb *phb, struct pci_device *dev)
{
struct phb3 *p = phb_to_phb3(phb);
u32 vdid;
u16 vendor, device;
if (dev->primary_bus != 0 &&
dev->primary_bus != 1)
return;
pci_cfg_read32(phb, dev->bdfn, 0, &vdid);
vendor = vdid & 0xffff;
device = vdid >> 16;
if (dev->primary_bus == 1) {
u64 modectl;
/* For these adapters, if they are directly under the PHB, we
* adjust some settings for performances
*/
xscom_read(p->chip_id, p->pe_xscom + 0x0b, &modectl);
if (vendor == 0x15b3 && /* Mellanox */
(device == 0x1003 || /* Travis3-EN (CX3) */
device == 0x1011 || /* HydePark (ConnectIB) */
device == 0x1013)) { /* GlacierPark (CX4) */
/* Set disable_wr_scope_group bit */
modectl |= PPC_BIT(14);
} else {
/* Clear disable_wr_scope_group bit */
modectl &= ~PPC_BIT(14);
}
xscom_write(p->chip_id, p->pe_xscom + 0x0b, modectl);
} else if (dev->primary_bus == 0) {
if (vendor == 0x1014 && /* IBM */
device == 0x03dc) { /* P8/P8E/P8NVL Root port */
uint32_t pref_hi, tmp;
pci_cfg_read32(phb, dev->bdfn,
PCI_CFG_PREF_MEM_BASE_U32, &pref_hi);
pci_cfg_write32(phb, dev->bdfn,
PCI_CFG_PREF_MEM_BASE_U32, ~pref_hi);
pci_cfg_read32(phb, dev->bdfn,
PCI_CFG_PREF_MEM_BASE_U32, &tmp);
pci_cfg_write32(phb, dev->bdfn,
PCI_CFG_PREF_MEM_BASE_U32, pref_hi);
if (tmp == pref_hi)
pci_add_cfg_reg_filter(dev,
PCI_CFG_PREF_MEM_BASE_U32, 12,
PCI_REG_FLAG_READ | PCI_REG_FLAG_WRITE,
phb3_pcicfg_rc_pref_window);
}
}
}
static inline int phb3_should_disable_ecrc(struct pci_device *pd)
{
/*
* When we have PMC PCIe switch, we need disable ECRC on root port.
* Otherwise, the adapters behind the switch downstream ports might
* not probed successfully.
*/
if (pd->vdid == 0x854611f8)
return true;
return false;
}
static int phb3_device_init(struct phb *phb,
struct pci_device *dev,
void *data)
{
struct phb3 *p = phb_to_phb3(phb);
int ecap, aercap;
/* Some special adapter tweaks for devices directly under the PHB */
phb3_check_device_quirks(phb, dev);
/* Common initialization for the device */
pci_device_init(phb, dev);
ecap = pci_cap(dev, PCI_CFG_CAP_ID_EXP, false);
aercap = pci_cap(dev, PCIECAP_ID_AER, true);
if (dev->dev_type == PCIE_TYPE_ROOT_PORT)
phb3_root_port_init(phb, dev, ecap, aercap);
else if (dev->dev_type == PCIE_TYPE_SWITCH_UPPORT ||
dev->dev_type == PCIE_TYPE_SWITCH_DNPORT)
phb3_switch_port_init(phb, dev, ecap, aercap);
else
phb3_endpoint_init(phb, dev, ecap, aercap);
/*
* Check if we need disable ECRC functionality on root port. It
* only happens when PCI topology changes, meaning it's skipped
* when reinitializing PCI device after EEH reset.
*/
if (!data && phb3_should_disable_ecrc(dev)) {
if (p->no_ecrc_devs++ == 0)
phb3_enable_ecrc(phb, false);
}
return 0;
}
static void phb3_device_remove(struct phb *phb, struct pci_device *pd)
{
struct phb3 *p = phb_to_phb3(phb);
if (!phb3_should_disable_ecrc(pd) || p->no_ecrc_devs == 0)
return;
if (--p->no_ecrc_devs == 0)
phb3_enable_ecrc(phb, true);
}
static int64_t phb3_pci_reinit(struct phb *phb, uint64_t scope, uint64_t data)
{
struct pci_device *pd;
uint16_t bdfn = data;
int ret;
if (scope != OPAL_REINIT_PCI_DEV)
return OPAL_PARAMETER;
pd = pci_find_dev(phb, bdfn);
if (!pd)
return OPAL_PARAMETER;
ret = phb3_device_init(phb, pd, pd);
if (ret)
return OPAL_HARDWARE;
return OPAL_SUCCESS;
}
/* Clear IODA cache tables */
static void phb3_init_ioda_cache(struct phb3 *p)
{
uint32_t i;
uint64_t *data64;
/*
* RTT and PELTV. RTE should be 0xFF's to indicate
* invalid PE# for the corresponding RID.
*
* Note: Instead we set all RTE entries to 0x00 to
* work around a problem where PE lookups might be
* done before Linux has established valid PE's
* (during PCI probing). We can revisit that once/if
* Linux has been fixed to always setup valid PEs.
*
* The value 0x00 corresponds to the default PE# Linux
* uses to check for config space freezes before it
* has assigned PE# to busses.
*
* WARNING: Additionally, we need to be careful, there's
* a HW issue, if we get an MSI on an RTT entry that is
* FF, things will go bad. We need to ensure we don't
* ever let a live FF RTT even temporarily when resetting
* for EEH etc... (HW278969).
*/
for (i = 0; i < ARRAY_SIZE(p->rte_cache); i++)
p->rte_cache[i] = PHB3_RESERVED_PE_NUM;
memset(p->peltv_cache, 0x0, sizeof(p->peltv_cache));
/* Disable all LSI */
for (i = 0; i < ARRAY_SIZE(p->lxive_cache); i++) {
data64 = &p->lxive_cache[i];
*data64 = SETFIELD(IODA2_LXIVT_PRIORITY, 0ul, 0xff);
*data64 = SETFIELD(IODA2_LXIVT_SERVER, *data64, 0x0);
}
/* Diable all MSI */
for (i = 0; i < ARRAY_SIZE(p->ive_cache); i++) {
data64 = &p->ive_cache[i];
*data64 = SETFIELD(IODA2_IVT_PRIORITY, 0ul, 0xff);
*data64 = SETFIELD(IODA2_IVT_SERVER, *data64, 0x0);
}
/* Clear TVT */
memset(p->tve_cache, 0x0, sizeof(p->tve_cache));
/* Clear M32 domain */
memset(p->m32d_cache, 0x0, sizeof(p->m32d_cache));
/* Clear M64 domain */
memset(p->m64b_cache, 0x0, sizeof(p->m64b_cache));
}
/* phb3_ioda_reset - Reset the IODA tables
*
* @purge: If true, the cache is cleared and the cleared values
* are applied to HW. If false, the cached values are
* applied to HW
*
* This reset the IODA tables in the PHB. It is called at
* initialization time, on PHB reset, and can be called
* explicitly from OPAL
*/
static int64_t phb3_ioda_reset(struct phb *phb, bool purge)
{
struct phb3 *p = phb_to_phb3(phb);
uint64_t server, prio;
uint64_t *pdata64, data64;
uint32_t i;
if (purge) {
prlog(PR_DEBUG, "PHB%x: Purging all IODA tables...\n",
p->phb.opal_id);
phb3_init_ioda_cache(p);
}
/* Init_27..28 - LIXVT */
phb3_ioda_sel(p, IODA2_TBL_LXIVT, 0, true);
for (i = 0; i < ARRAY_SIZE(p->lxive_cache); i++) {
data64 = p->lxive_cache[i];
server = GETFIELD(IODA2_LXIVT_SERVER, data64);
prio = GETFIELD(IODA2_LXIVT_PRIORITY, data64);
data64 = SETFIELD(IODA2_LXIVT_SERVER, data64, server);
data64 = SETFIELD(IODA2_LXIVT_PRIORITY, data64, prio);
out_be64(p->regs + PHB_IODA_DATA0, data64);
}
/* Init_29..30 - MRT */
phb3_ioda_sel(p, IODA2_TBL_MRT, 0, true);
for (i = 0; i < 8; i++)
out_be64(p->regs + PHB_IODA_DATA0, 0);
/* Init_31..32 - TVT */
phb3_ioda_sel(p, IODA2_TBL_TVT, 0, true);
for (i = 0; i < ARRAY_SIZE(p->tve_cache); i++)
out_be64(p->regs + PHB_IODA_DATA0, p->tve_cache[i]);
/* Init_33..34 - M64BT */
phb3_ioda_sel(p, IODA2_TBL_M64BT, 0, true);
for (i = 0; i < ARRAY_SIZE(p->m64b_cache); i++)
out_be64(p->regs + PHB_IODA_DATA0, p->m64b_cache[i]);
/* Init_35..36 - M32DT */
phb3_ioda_sel(p, IODA2_TBL_M32DT, 0, true);
for (i = 0; i < ARRAY_SIZE(p->m32d_cache); i++)
out_be64(p->regs + PHB_IODA_DATA0, p->m32d_cache[i]);
/* Load RTE, PELTV */
if (p->tbl_rtt)
memcpy((void *)p->tbl_rtt, p->rte_cache, RTT_TABLE_SIZE);
if (p->tbl_peltv)
memcpy((void *)p->tbl_peltv, p->peltv_cache, PELTV_TABLE_SIZE);
/* Load IVT */
if (p->tbl_ivt) {
pdata64 = (uint64_t *)p->tbl_ivt;
for (i = 0; i < IVT_TABLE_ENTRIES; i++)
pdata64[i * IVT_TABLE_STRIDE] = p->ive_cache[i];
}
/* Invalidate RTE, IVE, TCE cache */
out_be64(p->regs + PHB_RTC_INVALIDATE, PHB_RTC_INVALIDATE_ALL);
out_be64(p->regs + PHB_IVC_INVALIDATE, PHB_IVC_INVALIDATE_ALL);
out_be64(p->regs + PHB_TCE_KILL, PHB_TCE_KILL_ALL);
/* Clear RBA */
if (p->rev >= PHB3_REV_MURANO_DD20) {
phb3_ioda_sel(p, IODA2_TBL_RBA, 0, true);
for (i = 0; i < 32; i++)
out_be64(p->regs + PHB_IODA_DATA0, 0x0ul);
}
/* Clear PEST & PEEV */
for (i = 0; i < PHB3_MAX_PE_NUM; i++) {
uint64_t pesta, pestb;
phb3_ioda_sel(p, IODA2_TBL_PESTA, i, false);
pesta = in_be64(p->regs + PHB_IODA_DATA0);
out_be64(p->regs + PHB_IODA_DATA0, 0);
phb3_ioda_sel(p, IODA2_TBL_PESTB, i, false);
pestb = in_be64(p->regs + PHB_IODA_DATA0);
out_be64(p->regs + PHB_IODA_DATA0, 0);
if ((pesta & IODA2_PESTA_MMIO_FROZEN) ||
(pestb & IODA2_PESTB_DMA_STOPPED))
PHBDBG(p, "Frozen PE#%x (%s - %s)\n",
i, (pesta & IODA2_PESTA_MMIO_FROZEN) ? "DMA" : "",
(pestb & IODA2_PESTB_DMA_STOPPED) ? "MMIO" : "");
}
phb3_ioda_sel(p, IODA2_TBL_PEEV, 0, true);
for (i = 0; i < 4; i++)
out_be64(p->regs + PHB_IODA_DATA0, 0);
return OPAL_SUCCESS;
}
/*
* Clear anything we have in PAPR Error Injection registers. Though
* the spec says the PAPR error injection should be one-shot without
* the "sticky" bit. However, that's false according to the experiments
* I had. So we have to clear it at appropriate point in kernel to
* avoid endless frozen PE.
*/
static int64_t phb3_papr_errinjct_reset(struct phb *phb)
{
struct phb3 *p = phb_to_phb3(phb);
out_be64(p->regs + PHB_PAPR_ERR_INJ_CTL, 0x0ul);
out_be64(p->regs + PHB_PAPR_ERR_INJ_ADDR, 0x0ul);
out_be64(p->regs + PHB_PAPR_ERR_INJ_MASK, 0x0ul);
return OPAL_SUCCESS;
}
static int64_t phb3_set_phb_mem_window(struct phb *phb,
uint16_t window_type,
uint16_t window_num,
uint64_t addr,
uint64_t __unused pci_addr,
uint64_t size)
{
struct phb3 *p = phb_to_phb3(phb);
uint64_t data64;
/*
* By design, PHB3 doesn't support IODT any more.
* Besides, we can't enable M32 BAR as well. So
* the function is used to do M64 mapping and each
* BAR is supposed to be shared by all PEs.
*/
switch (window_type) {
case OPAL_IO_WINDOW_TYPE:
case OPAL_M32_WINDOW_TYPE:
return OPAL_UNSUPPORTED;
case OPAL_M64_WINDOW_TYPE:
if (window_num >= 16)
return OPAL_PARAMETER;
data64 = p->m64b_cache[window_num];
if (data64 & IODA2_M64BT_SINGLE_PE) {
if ((addr & 0x1FFFFFFul) ||
(size & 0x1FFFFFFul))
return OPAL_PARAMETER;
} else {
if ((addr & 0xFFFFFul) ||
(size & 0xFFFFFul))
return OPAL_PARAMETER;
}
/* size should be 2^N */
if (!size || size & (size-1))
return OPAL_PARAMETER;
/* address should be size aligned */
if (addr & (size - 1))
return OPAL_PARAMETER;
break;
default:
return OPAL_PARAMETER;
}
if (data64 & IODA2_M64BT_SINGLE_PE) {
data64 = SETFIELD(IODA2_M64BT_SINGLE_BASE, data64,
addr >> 25);
data64 = SETFIELD(IODA2_M64BT_SINGLE_MASK, data64,
0x20000000 - (size >> 25));
} else {
data64 = SETFIELD(IODA2_M64BT_BASE, data64,
addr >> 20);
data64 = SETFIELD(IODA2_M64BT_MASK, data64,
0x40000000 - (size >> 20));
}
p->m64b_cache[window_num] = data64;
return OPAL_SUCCESS;
}
/*
* For one specific M64 BAR, it can be shared by all PEs,
* or owned by single PE exclusively.
*/
static int64_t phb3_phb_mmio_enable(struct phb *phb,
uint16_t window_type,
uint16_t window_num,
uint16_t enable)
{
struct phb3 *p = phb_to_phb3(phb);
uint64_t data64, base, mask;
/*
* By design, PHB3 doesn't support IODT any more.
* Besides, we can't enable M32 BAR as well. So
* the function is used to do M64 mapping and each
* BAR is supposed to be shared by all PEs.
*/
switch (window_type) {
case OPAL_IO_WINDOW_TYPE:
case OPAL_M32_WINDOW_TYPE:
return OPAL_UNSUPPORTED;
case OPAL_M64_WINDOW_TYPE:
if (window_num >= 16 ||
enable > OPAL_ENABLE_M64_NON_SPLIT)
return OPAL_PARAMETER;
break;
default:
return OPAL_PARAMETER;
}
/*
* We need check the base/mask while enabling
* the M64 BAR. Otherwise, invalid base/mask
* might cause fenced AIB unintentionally
*/
data64 = p->m64b_cache[window_num];
switch (enable) {
case OPAL_DISABLE_M64:
data64 &= ~IODA2_M64BT_SINGLE_PE;
data64 &= ~IODA2_M64BT_ENABLE;
break;
case OPAL_ENABLE_M64_SPLIT:
if (data64 & IODA2_M64BT_SINGLE_PE)