-
Notifications
You must be signed in to change notification settings - Fork 134
/
xive.c
2281 lines (1952 loc) · 60.8 KB
/
xive.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/* Copyright 2016 IBM Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
* implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <skiboot.h>
#include <xscom.h>
#include <chip.h>
#include <io.h>
#include <xive.h>
#include <xscom-p9-regs.h>
#include <interrupts.h>
#include <timebase.h>
/* Use Block group mode to move chip_id into block .... */
#define USE_BLOCK_GROUP_MODE
/* Indirect mode */
#define USE_INDIRECT
/* Always notify from EQ to VP (no EOI on EQs). Will speed up
* EOIs at the expense of potentially higher powerbus traffic.
*/
#define EQ_ALWAYS_NOTIFY
/* Indirect VSDs are little endian (SIMICS bug ?) */
#undef INDIRECT_IS_LE
/* Verbose debug */
#undef XIVE_VERBOSE_DEBUG
/* Note on interrupt numbering:
*
* The way we represent HW interrupt numbers globaly in the system
* and in the device-tree is documented in include/interrupts.h
*
* Basically, the EAS/IVT index is the global interrupt number
*/
/*
*
* VSDs, blocks, set translation etc...
*
* This stuff confused me to no end so here's an attempt at explaining
* my understanding of it and how I use it in OPAL & Linux
*
* For the following data structures, the XIVE use a mechanism called
* Virtualization Structure Tables (VST) to manage the memory layout
* and access: ESBs (Event State Buffers, aka IPI sources), EAS/IVT
* (Event assignment structures), END/EQs (Notification descriptors
* aka event queues) and NVT/VPD (Notification Virtual Targets).
*
* These structures divide those tables into 16 "blocks". Each XIVE
* instance has a definition for all 16 blocks that can either represent
* an actual table in memory or a remote XIVE MMIO port to access a
* block that is owned by that remote XIVE.
*
* Our SW design will consist of allocating one block per chip (and thus
* per XIVE instance) for now, thus giving us up to 16 supported chips in
* the system. We may have to revisit that if we ever support systems with
* more than 16 chips but that isn't on our radar at the moment or if we
* want to do like pHyp on some machines and dedicate 2 blocks per chip
* for some structures.
*
* Thus we need to be careful that we never expose to Linux the concept
* of block and block boundaries, but instead we provide full number ranges
* so that consecutive blocks can be supported.
*
* We will pre-allocate some of the tables in order to support a "fallback"
* mode operations where an old-style XICS is emulated via OPAL calls. This
* is achieved by having a default of one VP per physical thread associated
* with one EQ and one IPI. There is also enought EATs to cover all the PHBs.
*
* Similarily, for MMIO access, the BARs support what is called "set
* translation" which allows tyhe BAR to be devided into a certain
* number of sets. The VC BAR (ESBs, ENDs, ...) supports 64 sets and
* the PC BAT supports 16. Each "set" can be routed to a specific
* block and offset within a block.
*
* For now, we will not use much of that functionality. We will use a
* fixed split between ESB and ENDs for the VC BAR as defined by the
* constants below and we will allocate all the PC BARs set to the
* local block of that chip
*/
/* BAR default values (should be initialized by HostBoot but for
* now we do it). Based on the memory map document by Dave Larson
*
* Fixed IC and TM BARs first.
*/
/* Use 64K for everything by default */
#define IC_PAGE_SIZE 0x10000
#define TM_PAGE_SIZE 0x10000
#define IPI_ESB_SHIFT (16 + 1)
#define IC_BAR_DEFAULT 0x30203100000ull
#define IC_BAR_SIZE (8 * IC_PAGE_SIZE)
#define TM_BAR_DEFAULT 0x30203180000ull
#define TM_BAR_SIZE (4 * TM_PAGE_SIZE)
/* VC BAR contains set translations for the ESBs and the EQs.
*
* It's divided in 64 sets, each of which can be either ESB pages or EQ pages.
* The table configuring this is the EDT
*
* Additionally, the ESB pages come in pair of Linux_Trig_Mode isn't enabled
* (which we won't enable for now as it assumes write-only permission which
* the MMU doesn't support).
*
* To get started we just hard wire the following setup:
*
* VC_BAR size is 512G. We split it into 384G of ESBs (48 sets) and 128G
* of ENDs (16 sets) for the time being. IE. Each set is thus 8GB
*/
#define VC_BAR_DEFAULT 0x10000000000ull
#define VC_BAR_SIZE 0x08000000000ull
#define VC_ESB_SETS 48
#define VC_END_SETS 16
#define VC_MAX_SETS 64
/* PC BAR contains the virtual processors
*
* The table configuring the set translation (16 sets) is the VDT
*/
#define PC_BAR_DEFAULT 0x18000000000ull
#define PC_BAR_SIZE 0x01000000000ull
#define PC_MAX_SETS 16
/* XXX This is the currently top limit of number of ESB/SBE entries
* and EAS/IVT entries pre-allocated per chip. This should probably
* turn into a device-tree property or NVRAM setting, or maybe
* calculated from the amount of system RAM...
*
* This is currently set to 1M
*
* This is independent of the sizing of the MMIO space.
*
* WARNING: Due to how XICS emulation works, we cannot support more
* interrupts per chip at this stage as the full interrupt number
* (block + index) has to fit in a 24-bit number.
*
* That gives us a pre-allocated space of 256KB per chip for the state
* bits and 8M per chip for the EAS/IVT.
*
* Note: The HW interrupts from PCIe and similar other entities that
* use their own state bit array will have to share that IVT space,
* so we could potentially make the IVT size twice as big, but for now
* we will simply share it and ensure we don't hand out IPIs that
* overlap the HW interrupts.
*/
#define MAX_INT_ENTRIES (1 * 1024 * 1024)
/* Corresponding direct table sizes */
#define SBE_SIZE (MAX_INT_ENTRIES / 4)
#define IVT_SIZE (MAX_INT_ENTRIES * 8)
/* Max number of EQs. We allocate an indirect table big enough so
* that when fully populated we can have that many EQs.
*
* The max number of EQs we support in our MMIO space is 128G/128K
* ie. 1M. Since one EQ is 8 words (32 bytes), a 64K page can hold
* 2K EQs. We need 512 pointers, ie, 4K of memory for the indirect
* table.
*
* XXX Adjust that based on BAR value ?
*/
#ifdef USE_INDIRECT
#define MAX_EQ_COUNT (1 * 1024 * 1024)
#define EQ_PER_PAGE (0x10000 / 32) // Use sizeof ?
#define IND_EQ_TABLE_SIZE ((MAX_EQ_COUNT / EQ_PER_PAGE) * 8)
#else
#define MAX_EQ_COUNT (4 * 1024)
#define EQT_SIZE (MAX_EQ_COUNT * 32)
#endif
/* Max number of VPs. We allocate an indirect table big enough so
* that when fully populated we can have that many VPs.
*
* The max number of VPs we support in our MMIO space is 64G/64K
* ie. 1M. Since one VP is 16 words (64 bytes), a 64K page can hold
* 1K EQ. We need 1024 pointers, ie, 8K of memory for the indirect
* table.
*
* HOWEVER: A block supports only up to 512K VPs (19 bits of target
* in the EQ). Since we currently only support 1 block per chip,
* we will allocate half of the above. We might add support for
* 2 blocks per chip later if necessary.
*
* XXX Adjust that based on BAR value ?
*/
#ifdef USE_INDIRECT
#define MAX_VP_COUNT (512 * 1024)
#define VP_PER_PAGE (0x10000 / 64) // Use sizeof ?
#define IND_VP_TABLE_SIZE ((MAX_VP_COUNT / VP_PER_PAGE) * 8)
#else
#define MAX_VP_COUNT (4 * 1024)
#define VPT_SIZE (MAX_VP_COUNT * 64)
#endif
#ifdef USE_BLOCK_GROUP_MODE
/* Initial number of VPs (XXX Make it a variable ?). Round things
* up to a max of 32 cores per chip
*/
#define INITIAL_VP_BASE 0x80
#define INITIAL_VP_COUNT 0x80
#else
/* Initial number of VPs on block 0 only */
#define INITIAL_BLK0_VP_BASE 0x800
#define INITIAL_BLK0_VP_COUNT (2 * 1024)
#endif
/* Each source controller has one of these. There's one embedded
* in the XIVE struct for IPIs
*/
struct xive_src {
struct irq_source is;
const struct irq_source_ops *orig_ops;
struct xive *xive;
void *esb_mmio;
uint32_t esb_base;
uint32_t esb_shift;
uint32_t flags;
};
struct xive {
uint32_t chip_id;
struct dt_node *x_node;
struct dt_node *m_node;
uint64_t xscom_base;
/* MMIO regions */
void *ic_base;
uint64_t ic_size;
uint32_t ic_shift;
void *tm_base;
uint64_t tm_size;
uint32_t tm_shift;
void *pc_base;
uint64_t pc_size;
void *vc_base;
uint64_t vc_size;
void *esb_mmio;
void *eq_mmio;
/* Set on XSCOM register access error */
bool last_reg_error;
/* Per-XIVE mutex */
struct lock lock;
/* Pre-allocated tables.
*
* We setup all the VDS for actual tables (ie, by opposition to
* forwarding ports) as either direct pre-allocated or indirect
* and partially populated.
*
* Currently, the ESB/SBE and the EAS/IVT tables are direct and
* fully pre-allocated based on MAX_INT_ENTRIES.
*
* The other tables are indirect, we thus pre-allocate the indirect
* table (ie, pages of pointers) and populate enough of the pages
* for our basic setup using 64K pages.
*
* The size of the indirect tables are driven by MAX_VP_COUNT and
* MAX_EQ_COUNT. The number of pre-allocated ones are driven by
* INITIAL_VP_COUNT (number of EQ depends on number of VP) in block
* mode, otherwise we only preallocate INITIAL_BLK0_VP_COUNT on
* block 0.
*/
/* Direct SBE and IVT tables */
void *sbe_base;
void *ivt_base;
#ifdef USE_INDIRECT
/* Indirect END/EQ table. NULL entries are unallocated, count is
* the numbre of pointers (ie, sub page placeholders). base_count
* is the number of sub-pages that have been pre-allocated (and
* thus whose memory is owned by OPAL).
*/
uint64_t *eq_ind_base;
uint32_t eq_ind_count;
uint32_t eq_alloc_count;
#else
void *eq_base;
#endif
#ifdef USE_INDIRECT
/* Indirect NVT/VP table. NULL entries are unallocated, count is
* the numbre of pointers (ie, sub page placeholders).
*/
uint64_t *vp_ind_base;
uint64_t vp_ind_count;
#else
void *vp_base;
#endif
/* To ease a possible change to supporting more than one block of
* interrupts per chip, we store here the "base" global number
* and max number of interrupts for this chip. The global number
* encompass the block number and index.
*/
uint32_t int_base;
uint32_t int_max;
/* Due to the overlap between IPIs and HW sources in the IVT table,
* we keep some kind of top-down allocator. It is used for HW sources
* to "allocate" interrupt entries and will limit what can be handed
* out as IPIs. Of course this assumes we "allocate" all HW sources
* before we start handing out IPIs.
*
* Note: The numbers here are global interrupt numbers so that we can
* potentially handle more than one block per chip in the future.
*/
uint32_t int_hw_bot; /* Bottom of HW allocation */
uint32_t int_ipi_top; /* Highest IPI handed out so far + 1 */
/* Embedded source IPIs */
struct xive_src ipis;
};
/* Conversion between GIRQ and block/index.
*
* ------------------------------------
* |00000000|BLOC| INDEX|
* ------------------------------------
* 8 4 20
*
* The global interrupt number is thus limited to 24 bits which is
* necessary for our XICS emulation since the top 8 bits are
* reserved for the CPPR value.
*
*/
#define GIRQ_TO_BLK(__g) (((__g) >> 20) & 0xf)
#define GIRQ_TO_IDX(__g) ((__g) & 0x000fffff)
#define BLKIDX_TO_GIRQ(__b,__i) (((uint32_t)(__b)) << 20 | (__i))
/* VP IDs are just the concatenation of the BLK and index as found
* in an EQ target field for example
*/
/* For now, it's one chip per block for both VC and PC */
#define PC_BLK_TO_CHIP(__b) (__b)
#define VC_BLK_TO_CHIP(__b) (__b)
#define GIRQ_TO_CHIP(__isn) (VC_BLK_TO_CHIP(GIRQ_TO_BLK(__isn)))
/* Routing of physical processors to VPs */
#ifdef USE_BLOCK_GROUP_MODE
#define PIR2VP_IDX(__pir) (0x80 | P9_PIR2LOCALCPU(__pir))
#define PIR2VP_BLK(__pir) (P9_PIR2GCID(__pir))
#define VP2PIR(__blk, __idx) (P9_PIRFROMLOCALCPU(VC_BLK_TO_CHIP(__blk), (__idx) & 0x7f))
#else
#define PIR2VP_IDX(__pir) (0x800 | (P9_PIR2GCID(__pir) << 7) | P9_PIR2LOCALCPU(__pir))
#define PIR2VP_BLK(__pir) (0)
#define VP2PIR(__blk, __idx) (P9_PIRFROMLOCALCPU(((__idx) >> 7) & 0xf, (__idx) & 0x7f))
#endif
#define xive_regw(__x, __r, __v) \
__xive_regw(__x, __r, X_##__r, __v, #__r)
#define xive_regr(__x, __r) \
__xive_regr(__x, __r, X_##__r, #__r)
#define xive_regwx(__x, __r, __v) \
__xive_regw(__x, 0, X_##__r, __v, #__r)
#define xive_regrx(__x, __r) \
__xive_regr(__x, 0, X_##__r, #__r)
#ifdef XIVE_VERBOSE_DEBUG
#define xive_vdbg(__x,__fmt,...) prlog(PR_DEBUG,"XIVE[ IC %02x ] " __fmt, (__x)->chip_id, ##__VA_ARGS__)
#define xive_cpu_vdbg(__c,__fmt,...) prlog(PR_DEBUG,"XIVE[CPU %04x] " __fmt, (__c)->pir, ##__VA_ARGS__)
#else
#define xive_vdbg(x,fmt,...) do { } while(0)
#define xive_cpu_vdbg(x,fmt,...) do { } while(0)
#endif
#define xive_dbg(__x,__fmt,...) prlog(PR_DEBUG,"XIVE[ IC %02x ] " __fmt, (__x)->chip_id, ##__VA_ARGS__)
#define xive_cpu_dbg(__c,__fmt,...) prlog(PR_DEBUG,"XIVE[CPU %04x] " __fmt, (__c)->pir, ##__VA_ARGS__)
#define xive_warn(__x,__fmt,...) prlog(PR_WARNING,"XIVE[ IC %02x ] " __fmt, (__x)->chip_id, ##__VA_ARGS__)
#define xive_cpu_warn(__c,__fmt,...) prlog(PR_WARNING,"XIVE[CPU %04x] " __fmt, (__c)->pir, ##__VA_ARGS__)
#define xive_err(__x,__fmt,...) prlog(PR_ERR,"XIVE[ IC %02x ] " __fmt, (__x)->chip_id, ##__VA_ARGS__)
#define xive_cpu_err(__c,__fmt,...) prlog(PR_ERR,"XIVE[CPU %04x] " __fmt, (__c)->pir, ##__VA_ARGS__)
static void __xive_regw(struct xive *x, uint32_t m_reg, uint32_t x_reg, uint64_t v,
const char *rname)
{
bool use_xscom = (m_reg == 0) || !x->ic_base;
int64_t rc;
x->last_reg_error = false;
if (use_xscom) {
assert(x_reg != 0);
rc = xscom_write(x->chip_id, x->xscom_base + x_reg, v);
if (rc) {
if (!rname)
rname = "???";
xive_err(x, "Error writing register %s\n", rname);
/* Anything else we can do here ? */
x->last_reg_error = true;
}
} else {
out_be64(x->ic_base + m_reg, v);
}
}
static uint64_t __xive_regr(struct xive *x, uint32_t m_reg, uint32_t x_reg,
const char *rname)
{
bool use_xscom = (m_reg == 0) || !x->ic_base;
int64_t rc;
uint64_t val;
x->last_reg_error = false;
if (use_xscom) {
rc = xscom_read(x->chip_id, x->xscom_base + x_reg, &val);
if (rc) {
if (!rname)
rname = "???";
xive_err(x, "Error reading register %s\n", rname);
/* Anything else we can do here ? */
x->last_reg_error = true;
return -1ull;
}
} else {
val = in_be64(x->ic_base + m_reg);
}
return val;
}
/* Locate a controller from an IRQ number */
static struct xive *xive_from_isn(uint32_t isn)
{
uint32_t chip_id = GIRQ_TO_CHIP(isn);
struct proc_chip *c = get_chip(chip_id);
if (!c)
return NULL;
return c->xive;
}
/*
static struct xive *xive_from_pc_blk(uint32_t blk)
{
uint32_t chip_id = PC_BLK_TO_CHIP(blk);
struct proc_chip *c = get_chip(chip_id);
if (!c)
return NULL;
return c->xive;
}
*/
static struct xive *xive_from_vc_blk(uint32_t blk)
{
uint32_t chip_id = VC_BLK_TO_CHIP(blk);
struct proc_chip *c = get_chip(chip_id);
if (!c)
return NULL;
return c->xive;
}
static struct xive_ive *xive_get_ive(struct xive *x, unsigned int isn)
{
struct xive_ive *ivt;
uint32_t idx = GIRQ_TO_IDX(isn);
/* Check the block matches */
if (isn < x->int_base || isn >= x->int_max) {
xive_err(x, "xive_get_ive, ISN 0x%x not on chip\n", idx);
return NULL;
}
assert (idx < MAX_INT_ENTRIES);
/* If we support >1 block per chip, this should still work as
* we are likely to make the table contiguous anyway
*/
ivt = x->ivt_base;
assert(ivt);
return ivt + idx;
}
static struct xive_eq *xive_get_eq(struct xive *x, unsigned int idx)
{
struct xive_eq *p;
#ifdef USE_INDIRECT
if (idx >= (x->eq_ind_count * EQ_PER_PAGE))
return NULL;
#ifdef INDIRECT_IS_LE
p = (struct xive_eq *)(le64_to_cpu(x->eq_ind_base[idx / EQ_PER_PAGE]) &
VSD_ADDRESS_MASK);
#else
p = (struct xive_eq *)(x->eq_ind_base[idx / EQ_PER_PAGE] &
VSD_ADDRESS_MASK);
#endif
if (!p)
return NULL;
return &p[idx % EQ_PER_PAGE];
#else
if (idx >= MAX_EQ_COUNT)
return NULL;
if (!x->eq_base)
return NULL;
p = x->eq_base;
return p + idx;
#endif
}
static struct xive_vp *xive_get_vp(struct xive *x, unsigned int idx)
{
struct xive_vp *p;
#ifdef USE_INDIRECT
assert(idx < (x->vp_ind_count * VP_PER_PAGE));
#ifdef INDIRECT_IS_LE
p = (struct xive_vp *)(le64_to_cpu(x->vp_ind_base[idx / VP_PER_PAGE]) &
VSD_ADDRESS_MASK);
#else
p = (struct xive_vp *)(x->vp_ind_base[idx / VP_PER_PAGE] &
VSD_ADDRESS_MASK);
#endif
assert(p);
return &p[idx % VP_PER_PAGE];
#else
assert(idx < MAX_VP_COUNT);
p = x->vp_base;
return p + idx;
#endif
}
static void xive_init_vp(struct xive *x __unused, struct xive_vp *vp __unused)
{
/* XXX TODO: Look at the special cache line stuff */
vp->w0 = VP_W0_VALID;
}
static void xive_init_eq(struct xive *x __unused, uint32_t vp_idx,
struct xive_eq *eq, void *backing_page)
{
eq->w1 = EQ_W1_GENERATION;
eq->w3 = ((uint64_t)backing_page) & 0xffffffff;
eq->w2 = (((uint64_t)backing_page)) >> 32 & 0x0fffffff;
// IS this right ? Are we limited to 2K VPs per block ? */
eq->w6 = SETFIELD(EQ_W6_NVT_BLOCK, 0ul, x->chip_id) |
SETFIELD(EQ_W6_NVT_INDEX, 0ul, vp_idx);
eq->w7 = SETFIELD(EQ_W7_F0_PRIORITY, 0ul, 0x07);
eieio();
eq->w0 = EQ_W0_VALID | EQ_W0_ENQUEUE |
SETFIELD(EQ_W0_QSIZE, 0ul, EQ_QSIZE_64K);
#ifdef EQ_ALWAYS_NOTIFY
eq->w0 |= EQ_W0_UCOND_NOTIFY;
#endif
}
static uint32_t *xive_get_eq_buf(struct xive *x, uint32_t eq_blk __unused,
uint32_t eq_idx)
{
struct xive_eq *eq = xive_get_eq(x, eq_idx);
uint64_t addr;
assert(eq);
assert(eq->w0 & EQ_W0_VALID);
addr = (((uint64_t)eq->w2) & 0x0fffffff) << 32 | eq->w3;
return (uint32_t *)addr;
}
#if 0 /* Not used yet. This will be used to kill the cache
* of indirect VSDs
*/
static int64_t xive_vc_ind_cache_kill(struct xive *x, uint64_t type,
uint64_t block, uint64_t idx)
{
uint64_t val;
xive_regw(x, VC_AT_MACRO_KILL_MASK,
SETFIELD(VC_KILL_BLOCK_ID, 0ull, -1ull) |
SETFIELD(VC_KILL_OFFSET, 0ull, -1ull));
xive_regw(x, VC_AT_MACRO_KILL, VC_KILL_VALID |
SETFIELD(VC_KILL_TYPE, 0ull, type) |
SETFIELD(VC_KILL_BLOCK_ID, 0ull, block) |
SETFIELD(VC_KILL_OFFSET, 0ull, idx));
/* XXX SIMICS problem ? */
if (chip_quirk(QUIRK_SIMICS))
return 0;
/* XXX Add timeout */
for (;;) {
val = xive_regr(x, VC_AT_MACRO_KILL);
if (!(val & VC_KILL_VALID))
break;
}
return 0;
}
#endif
enum xive_cache_type {
xive_cache_ivc,
xive_cache_sbc,
xive_cache_eqc,
xive_cache_vpc,
};
static int64_t __xive_cache_scrub(struct xive *x, enum xive_cache_type ctype,
uint64_t block, uint64_t idx,
bool want_inval, bool want_disable)
{
uint64_t sreg, sregx, mreg, mregx;
uint64_t mval, sval;
switch (ctype) {
case xive_cache_ivc:
sreg = VC_IVC_SCRUB_TRIG;
sregx = X_VC_IVC_SCRUB_TRIG;
mreg = VC_IVC_SCRUB_MASK;
mregx = X_VC_IVC_SCRUB_MASK;
break;
case xive_cache_sbc:
sreg = VC_SBC_SCRUB_TRIG;
sregx = X_VC_SBC_SCRUB_TRIG;
mreg = VC_SBC_SCRUB_MASK;
mregx = X_VC_SBC_SCRUB_MASK;
break;
case xive_cache_eqc:
sreg = VC_EQC_SCRUB_TRIG;
sregx = X_VC_EQC_SCRUB_TRIG;
mreg = VC_EQC_SCRUB_MASK;
mregx = X_VC_EQC_SCRUB_MASK;
break;
case xive_cache_vpc:
sreg = PC_VPC_SCRUB_TRIG;
sregx = X_PC_VPC_SCRUB_TRIG;
mreg = PC_VPC_SCRUB_MASK;
mregx = X_PC_VPC_SCRUB_MASK;
break;
}
if (ctype == xive_cache_vpc) {
mval = PC_SCRUB_BLOCK_ID | PC_SCRUB_OFFSET;
sval = SETFIELD(PC_SCRUB_BLOCK_ID, idx, block) |
PC_SCRUB_VALID;
} else {
mval = VC_SCRUB_BLOCK_ID | VC_SCRUB_OFFSET;
sval = SETFIELD(VC_SCRUB_BLOCK_ID, idx, block) |
VC_SCRUB_VALID;
}
if (want_inval)
sval |= PC_SCRUB_WANT_INVAL;
if (want_disable)
sval |= PC_SCRUB_WANT_DISABLE;
__xive_regw(x, mreg, mregx, mval, NULL);
__xive_regw(x, sreg, sregx, sval, NULL);
/* XXX Add timeout !!! */
for (;;) {
sval = __xive_regr(x, sreg, sregx, NULL);
if (!(sval & VC_SCRUB_VALID))
break;
time_wait_us(1);
}
return 0;
}
static int64_t xive_ivc_scrub(struct xive *x, uint64_t block, uint64_t idx)
{
return __xive_cache_scrub(x, xive_cache_ivc, block, idx, false, false);
}
static bool xive_set_vsd(struct xive *x, uint32_t tbl, uint32_t idx, uint64_t v)
{
/* Set VC version */
xive_regw(x, VC_VSD_TABLE_ADDR,
SETFIELD(VST_TABLE_SELECT, 0ull, tbl) |
SETFIELD(VST_TABLE_OFFSET, 0ull, idx));
if (x->last_reg_error)
return false;
xive_regw(x, VC_VSD_TABLE_DATA, v);
if (x->last_reg_error)
return false;
/* Except for IRQ table, also set PC version */
if (tbl == VST_TSEL_IRQ)
return true;
xive_regw(x, PC_VSD_TABLE_ADDR,
SETFIELD(VST_TABLE_SELECT, 0ull, tbl) |
SETFIELD(VST_TABLE_OFFSET, 0ull, idx));
if (x->last_reg_error)
return false;
xive_regw(x, PC_VSD_TABLE_DATA, v);
if (x->last_reg_error)
return false;
return true;
}
static bool xive_set_local_tables(struct xive *x)
{
uint64_t base;
/* These have to be power of 2 sized */
assert(is_pow2(SBE_SIZE));
assert(is_pow2(IVT_SIZE));
/* All tables set as exclusive */
base = SETFIELD(VSD_MODE, 0ull, VSD_MODE_EXCLUSIVE);
/* Set IVT as direct mode */
if (!xive_set_vsd(x, VST_TSEL_IVT, x->chip_id, base |
(((uint64_t)x->ivt_base) & VSD_ADDRESS_MASK) |
SETFIELD(VSD_TSIZE, 0ull, ilog2(IVT_SIZE) - 12)))
return false;
/* Set SBE as direct mode */
if (!xive_set_vsd(x, VST_TSEL_SBE, x->chip_id, base |
(((uint64_t)x->sbe_base) & VSD_ADDRESS_MASK) |
SETFIELD(VSD_TSIZE, 0ull, ilog2(SBE_SIZE) - 12)))
return false;
#ifdef USE_INDIRECT
/* Set EQDT as indirect mode with 64K subpages */
if (!xive_set_vsd(x, VST_TSEL_EQDT, x->chip_id, base |
(((uint64_t)x->eq_ind_base) & VSD_ADDRESS_MASK) |
VSD_INDIRECT | SETFIELD(VSD_TSIZE, 0ull, 4)))
return false;
/* Set VPDT as indirect mode with 64K subpages */
if (!xive_set_vsd(x, VST_TSEL_VPDT, x->chip_id, base |
(((uint64_t)x->vp_ind_base) & VSD_ADDRESS_MASK) |
VSD_INDIRECT | SETFIELD(VSD_TSIZE, 0ull, 4)))
return false;
#else
/* Set EQDT as direct mode */
if (!xive_set_vsd(x, VST_TSEL_EQDT, x->chip_id, base |
(((uint64_t)x->eq_base) & VSD_ADDRESS_MASK) |
SETFIELD(VSD_TSIZE, 0ull, ilog2(EQT_SIZE) - 12)))
return false;
/* Set VPDT as direct mode */
if (!xive_set_vsd(x, VST_TSEL_VPDT, x->chip_id, base |
(((uint64_t)x->vp_base) & VSD_ADDRESS_MASK) |
SETFIELD(VSD_TSIZE, 0ull, ilog2(VPT_SIZE) - 12)))
return false;
#endif
return true;
}
static bool xive_read_bars(struct xive *x)
{
uint64_t bar, msk;
/* Read IC BAR */
bar = xive_regrx(x, CQ_IC_BAR);
if (bar & CQ_IC_BAR_64K)
x->ic_shift = 16;
else
x->ic_shift = 12;
x->ic_size = 8ul << x->ic_shift;
x->ic_base = (void *)(bar & 0x00ffffffffffffffull);
/* Read TM BAR */
bar = xive_regrx(x, CQ_TM1_BAR);
assert(bar & CQ_TM_BAR_VALID);
if (bar & CQ_TM_BAR_64K)
x->tm_shift = 16;
else
x->tm_shift = 12;
x->tm_size = 4ul << x->tm_shift;
x->tm_base = (void *)(bar & 0x00ffffffffffffffull);
/* Read PC BAR */
bar = xive_regr(x, CQ_PC_BAR);
msk = xive_regr(x, CQ_PC_BARM) | 0xffffffc000000000ul;
assert(bar & CQ_PC_BAR_VALID);
x->pc_size = (~msk) + 1;
x->pc_base = (void *)(bar & 0x00ffffffffffffffull);
/* Read VC BAR */
bar = xive_regr(x, CQ_VC_BAR);
msk = xive_regr(x, CQ_VC_BARM) | 0xfffff80000000000ul;
assert(bar & CQ_VC_BAR_VALID);
x->vc_size = (~msk) + 1;
x->vc_base = (void *)(bar & 0x00ffffffffffffffull);
return true;
}
static bool xive_configure_bars(struct xive *x)
{
uint64_t mmio_base, chip_base, val;
/* Calculate MMIO base offset for that chip */
mmio_base = 0x006000000000000ull;
chip_base = mmio_base | (0x40000000000ull * (uint64_t)x->chip_id);
/* IC BAR */
x->ic_base = (void *)(chip_base | IC_BAR_DEFAULT);
x->ic_size = IC_BAR_SIZE;
val = (uint64_t)x->ic_base | CQ_IC_BAR_VALID;
if (IC_PAGE_SIZE == 0x10000) {
val |= CQ_IC_BAR_64K;
x->ic_shift = 16;
} else
x->ic_shift = 12;
xive_regwx(x, CQ_IC_BAR, val);
if (x->last_reg_error)
return false;
/* TM BAR, only configure TM1. Note that this has the same address
* for each chip !!!
*/
x->tm_base = (void *)(mmio_base | TM_BAR_DEFAULT);
x->tm_size = TM_BAR_SIZE;
val = (uint64_t)x->tm_base | CQ_TM_BAR_VALID;
if (TM_PAGE_SIZE == 0x10000) {
x->tm_shift = 16;
val |= CQ_TM_BAR_64K;
} else
x->tm_shift = 12;
xive_regwx(x, CQ_TM1_BAR, val);
if (x->last_reg_error)
return false;
xive_regwx(x, CQ_TM2_BAR, 0);
if (x->last_reg_error)
return false;
/* PC BAR. Clear first, write mask, then write value */
x->pc_base = (void *)(chip_base | PC_BAR_DEFAULT);
x->pc_size = PC_BAR_SIZE;
xive_regwx(x, CQ_PC_BAR, 0);
if (x->last_reg_error)
return false;
val = ~(PC_BAR_SIZE - 1) & CQ_PC_BARM_MASK;
xive_regwx(x, CQ_PC_BARM, val);
if (x->last_reg_error)
return false;
val = (uint64_t)x->pc_base | CQ_PC_BAR_VALID;
xive_regwx(x, CQ_PC_BAR, val);
if (x->last_reg_error)
return false;
/* VC BAR. Clear first, write mask, then write value */
x->vc_base = (void *)(chip_base | VC_BAR_DEFAULT);
x->vc_size = VC_BAR_SIZE;
xive_regwx(x, CQ_VC_BAR, 0);
if (x->last_reg_error)
return false;
val = ~(VC_BAR_SIZE - 1) & CQ_VC_BARM_MASK;
xive_regwx(x, CQ_VC_BARM, val);
if (x->last_reg_error)
return false;
val = (uint64_t)x->vc_base | CQ_VC_BAR_VALID;
xive_regwx(x, CQ_VC_BAR, val);
if (x->last_reg_error)
return false;
return true;
}
static void xive_dump_mmio(struct xive *x)
{
prlog(PR_DEBUG, " CQ_CFG_PB_GEN = %016llx\n",
in_be64(x->ic_base + CQ_CFG_PB_GEN));
prlog(PR_DEBUG, " CQ_MSGSND = %016llx\n",
in_be64(x->ic_base + CQ_MSGSND));
}
static bool xive_check_update_bars(struct xive *x)
{
uint64_t val;
bool force_assign;
/* Check if IC BAR is enabled */
val = xive_regrx(x, CQ_IC_BAR);
if (x->last_reg_error)
return false;
/* Check if device-tree tells us to force-assign the BARs */
force_assign = dt_has_node_property(x->x_node,
"force-assign-bars", NULL);
if ((val & CQ_IC_BAR_VALID) && !force_assign) {
xive_dbg(x, "IC BAR valid, using existing values\n");
if (!xive_read_bars(x))
return false;
} else {
xive_warn(x, "IC BAR invalid, reconfiguring\n");
if (!xive_configure_bars(x))
return false;
}
/* Calculate some MMIO bases in the VC BAR */
x->esb_mmio = x->vc_base;
x->eq_mmio = x->vc_base + (x->vc_size / VC_MAX_SETS) * VC_ESB_SETS;
/* Print things out */
xive_dbg(x, "IC: %14p [0x%012llx/%d]\n", x->ic_base, x->ic_size,
x->ic_shift);
xive_dbg(x, "TM: %14p [0x%012llx/%d]\n", x->tm_base, x->tm_size,
x->tm_shift);
xive_dbg(x, "PC: %14p [0x%012llx]\n", x->pc_base, x->pc_size);
xive_dbg(x, "VC: %14p [0x%012llx]\n", x->vc_base, x->vc_size);
return true;
}
static bool xive_config_init(struct xive *x)
{
uint64_t val __unused;
/* Configure PC and VC page sizes and disable Linux trigger mode */
xive_regwx(x, CQ_PBI_CTL, CQ_PBI_PC_64K | CQ_PBI_VC_64K);
if (x->last_reg_error)
return false;
/*** The rest can use MMIO ***/
#ifdef USE_INDIRECT
/* Enable indirect mode in VC config */
val = xive_regr(x, VC_GLOBAL_CONFIG);
val |= VC_GCONF_INDIRECT;
xive_regw(x, VC_GLOBAL_CONFIG, val);
/* Enable indirect mode in PC config */
val = xive_regr(x, PC_GLOBAL_CONFIG);
val |= PC_GCONF_INDIRECT;
xive_regw(x, PC_GLOBAL_CONFIG, val);
#endif
#ifdef USE_BLOCK_GROUP_MODE
val = xive_regr(x, PC_TCTXT_CFG);
val |= PC_TCTXT_CFG_BLKGRP_EN | PC_TCTXT_CFG_HARD_CHIPID_BLK;
xive_regw(x, PC_TCTXT_CFG, val);
#endif
return true;
}
static bool xive_setup_set_xlate(struct xive *x)
{
unsigned int i;
/* Configure EDT for ESBs (aka IPIs) */
xive_regw(x, CQ_TAR, CQ_TAR_TBL_AUTOINC | CQ_TAR_TSEL_EDT);
if (x->last_reg_error)
return false;
for (i = 0; i < VC_ESB_SETS; i++) {
xive_regw(x, CQ_TDR,
/* IPI type */
(1ull << 62) |
/* block is chip_ID */
(((uint64_t)x->chip_id) << 48) |
/* offset */
(((uint64_t)i) << 32));
if (x->last_reg_error)
return false;
}
/* Configure EDT for ENDs (aka EQs) */
for (i = 0; i < VC_END_SETS; i++) {
xive_regw(x, CQ_TDR,
/* EQ type */
(2ull << 62) |
/* block is chip_ID */
(((uint64_t)x->chip_id) << 48) |
/* offset */
(((uint64_t)i) << 32));
if (x->last_reg_error)
return false;
}
/* Configure VDT */
xive_regw(x, CQ_TAR, CQ_TAR_TBL_AUTOINC | CQ_TAR_TSEL_VDT);
if (x->last_reg_error)
return false;
for (i = 0; i < PC_MAX_SETS; i++) {
xive_regw(x, CQ_TDR,
/* Valid bit */