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xive.c
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xive.c
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/* Copyright 2016 IBM Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
* implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <skiboot.h>
#include <xscom.h>
#include <chip.h>
#include <io.h>
#include <xive.h>
#include <xscom-p9-regs.h>
#include <interrupts.h>
#include <timebase.h>
#include <bitmap.h>
#include <buddy.h>
/* Use Block group mode to move chip_id into block .... */
#define USE_BLOCK_GROUP_MODE
/* Indirect mode */
#define USE_INDIRECT
/* Always notify from EQ to VP (no EOI on EQs). Will speed up
* EOIs at the expense of potentially higher powerbus traffic.
*/
#define EQ_ALWAYS_NOTIFY
/* Verbose debug */
#undef XIVE_VERBOSE_DEBUG
/*
*
* VSDs, blocks, set translation etc...
*
* This stuff confused me to no end so here's an attempt at explaining
* my understanding of it and how I use it in OPAL & Linux
*
* For the following data structures, the XIVE use a mechanism called
* Virtualization Structure Tables (VST) to manage the memory layout
* and access: ESBs (Event State Buffers, aka IPI sources), EAS/IVT
* (Event assignment structures), END/EQs (Notification descriptors
* aka event queues) and NVT/VPD (Notification Virtual Targets).
*
* These structures divide those tables into 16 "blocks". Each XIVE
* instance has a definition for all 16 blocks that can either represent
* an actual table in memory or a remote XIVE MMIO port to access a
* block that is owned by that remote XIVE.
*
* Our SW design will consist of allocating one block per chip (and thus
* per XIVE instance) for now, thus giving us up to 16 supported chips in
* the system. We may have to revisit that if we ever support systems with
* more than 16 chips but that isn't on our radar at the moment or if we
* want to do like pHyp on some machines and dedicate 2 blocks per chip
* for some structures.
*
* Thus we need to be careful that we never expose to Linux the concept
* of block and block boundaries, but instead we provide full number ranges
* so that consecutive blocks can be supported.
*
* We will pre-allocate some of the tables in order to support a "fallback"
* mode operations where an old-style XICS is emulated via OPAL calls. This
* is achieved by having a default of one VP per physical thread associated
* with one EQ and one IPI. There is also enought EATs to cover all the PHBs.
*
* Similarily, for MMIO access, the BARs support what is called "set
* translation" which allows tyhe BAR to be devided into a certain
* number of sets. The VC BAR (ESBs, ENDs, ...) supports 64 sets and
* the PC BAT supports 16. Each "set" can be routed to a specific
* block and offset within a block.
*
* For now, we will not use much of that functionality. We will use a
* fixed split between ESB and ENDs for the VC BAR as defined by the
* constants below and we will allocate all the PC BARs set to the
* local block of that chip
*/
/* BAR default values (should be initialized by HostBoot but for
* now we do it). Based on the memory map document by Dave Larson
*
* Fixed IC and TM BARs first.
*/
/* Use 64K for everything by default */
#define IC_PAGE_SIZE 0x10000
#define TM_PAGE_SIZE 0x10000
#define IPI_ESB_SHIFT (16 + 1)
#define IC_BAR_DEFAULT 0x30203100000ull
#define IC_BAR_SIZE (8 * IC_PAGE_SIZE)
#define TM_BAR_DEFAULT 0x30203180000ull
#define TM_BAR_SIZE (4 * TM_PAGE_SIZE)
/* VC BAR contains set translations for the ESBs and the EQs.
*
* It's divided in 64 sets, each of which can be either ESB pages or EQ pages.
* The table configuring this is the EDT
*
* Additionally, the ESB pages come in pair of Linux_Trig_Mode isn't enabled
* (which we won't enable for now as it assumes write-only permission which
* the MMU doesn't support).
*
* To get started we just hard wire the following setup:
*
* VC_BAR size is 512G. We split it into 384G of ESBs (48 sets) and 128G
* of ENDs (16 sets) for the time being. IE. Each set is thus 8GB
*/
#define VC_BAR_DEFAULT 0x10000000000ull
#define VC_BAR_SIZE 0x08000000000ull
#define VC_ESB_SETS 48
#define VC_END_SETS 16
#define VC_MAX_SETS 64
/* PC BAR contains the virtual processors
*
* The table configuring the set translation (16 sets) is the VDT
*/
#define PC_BAR_DEFAULT 0x18000000000ull
#define PC_BAR_SIZE 0x01000000000ull
#define PC_MAX_SETS 16
/* XXX This is the currently top limit of number of ESB/SBE entries
* and EAS/IVT entries pre-allocated per chip. This should probably
* turn into a device-tree property or NVRAM setting, or maybe
* calculated from the amount of system RAM...
*
* This is currently set to 1M
*
* This is independent of the sizing of the MMIO space.
*
* WARNING: Due to how XICS emulation works, we cannot support more
* interrupts per chip at this stage as the full interrupt number
* (block + index) has to fit in a 24-bit number.
*
* That gives us a pre-allocated space of 256KB per chip for the state
* bits and 8M per chip for the EAS/IVT.
*
* Note: The HW interrupts from PCIe and similar other entities that
* use their own state bit array will have to share that IVT space,
* so we could potentially make the IVT size twice as big, but for now
* we will simply share it and ensure we don't hand out IPIs that
* overlap the HW interrupts.
*/
#define MAX_INT_ENTRIES (1 * 1024 * 1024)
/* Corresponding direct table sizes */
#define SBE_SIZE (MAX_INT_ENTRIES / 4)
#define IVT_SIZE (MAX_INT_ENTRIES * 8)
/* Max number of EQs. We allocate an indirect table big enough so
* that when fully populated we can have that many EQs.
*
* The max number of EQs we support in our MMIO space is 128G/128K
* ie. 1M. Since one EQ is 8 words (32 bytes), a 64K page can hold
* 2K EQs. We need 512 pointers, ie, 4K of memory for the indirect
* table.
*
* XXX Adjust that based on BAR value ?
*/
#ifdef USE_INDIRECT
#define MAX_EQ_COUNT (1 * 1024 * 1024)
#define EQ_PER_PAGE (0x10000 / 32) // Use sizeof ?
#define IND_EQ_TABLE_SIZE ((MAX_EQ_COUNT / EQ_PER_PAGE) * 8)
#else
#define MAX_EQ_COUNT (4 * 1024)
#define EQT_SIZE (MAX_EQ_COUNT * 32)
#endif
/* Number of priorities (and thus EQDs) we allocate for each VP */
#define NUM_INT_PRIORITIES 8
/* Priority used for the one queue in XICS emulation */
#define XIVE_EMULATION_PRIO 7
/* Max number of VPs. We allocate an indirect table big enough so
* that when fully populated we can have that many VPs.
*
* The max number of VPs we support in our MMIO space is 64G/64K
* ie. 1M. Since one VP is 16 words (64 bytes), a 64K page can hold
* 1K EQ. We need 1024 pointers, ie, 8K of memory for the indirect
* table.
*
* HOWEVER: A block supports only up to 512K VPs (19 bits of target
* in the EQ). Since we currently only support 1 block per chip,
* we will allocate half of the above. We might add support for
* 2 blocks per chip later if necessary.
*
* XXX Adjust that based on BAR value ?
*/
#ifdef USE_INDIRECT
#define MAX_VP_ORDER 19 /* 512k */
#define MAX_VP_COUNT (1ul << MAX_VP_ORDER)
#define VP_PER_PAGE (0x10000 / 64) // Use sizeof ?
#define IND_VP_TABLE_SIZE ((MAX_VP_COUNT / VP_PER_PAGE) * 8)
#else
#define MAX_VP_ORDER 12 /* 4k */
#define MAX_VP_COUNT (1ul << MAX_VP_ORDER)
#define VPT_SIZE (MAX_VP_COUNT * 64)
#endif
#ifdef USE_BLOCK_GROUP_MODE
/* Initial number of VPs (XXX Make it a variable ?). Round things
* up to a max of 32 cores per chip
*/
#define INITIAL_VP_BASE 0x80
#define INITIAL_VP_COUNT 0x80
#else
/* Initial number of VPs on block 0 only */
#define INITIAL_BLK0_VP_BASE 0x800
#define INITIAL_BLK0_VP_COUNT 0x800
#endif
/* The xive operation mode indicates the active "API" and corresponds
* to the "mode" parameter of the opal_xive_reset() call
*/
static enum {
XIVE_MODE_EMU = OPAL_XIVE_MODE_EMU,
XIVE_MODE_EXPL = OPAL_XIVE_MODE_EXPL,
} xive_mode;
/* Each source controller has one of these. There's one embedded
* in the XIVE struct for IPIs
*/
struct xive_src {
struct irq_source is;
const struct irq_source_ops *orig_ops;
struct xive *xive;
void *esb_mmio;
uint32_t esb_base;
uint32_t esb_shift;
uint32_t flags;
};
struct xive_cpu_state {
struct xive *xive;
void *tm_ring1;
/* Base HW VP and associated queues */
uint32_t vp_blk;
uint32_t vp_idx;
uint32_t eq_blk;
uint32_t eq_idx; /* Base eq index of a block of 8 */
void *eq_page;
/* Pre-allocated IPI */
uint32_t ipi_irq;
/* Use for XICS emulation */
struct lock lock;
uint8_t cppr;
uint8_t mfrr;
uint8_t pending;
uint8_t prev_cppr;
uint32_t *eqbuf;
uint32_t eqptr;
uint32_t eqmsk;
uint8_t eqgen;
void *eqmmio;
};
struct xive {
uint32_t chip_id;
uint32_t block_id;
struct dt_node *x_node;
uint64_t xscom_base;
/* MMIO regions */
void *ic_base;
uint64_t ic_size;
uint32_t ic_shift;
void *tm_base;
uint64_t tm_size;
uint32_t tm_shift;
void *pc_base;
uint64_t pc_size;
void *vc_base;
uint64_t vc_size;
void *esb_mmio;
void *eq_mmio;
/* Set on XSCOM register access error */
bool last_reg_error;
/* Per-XIVE mutex */
struct lock lock;
/* Pre-allocated tables.
*
* We setup all the VDS for actual tables (ie, by opposition to
* forwarding ports) as either direct pre-allocated or indirect
* and partially populated.
*
* Currently, the ESB/SBE and the EAS/IVT tables are direct and
* fully pre-allocated based on MAX_INT_ENTRIES.
*
* The other tables are indirect, we thus pre-allocate the indirect
* table (ie, pages of pointers) and populate enough of the pages
* for our basic setup using 64K pages.
*
* The size of the indirect tables are driven by MAX_VP_COUNT and
* MAX_EQ_COUNT. The number of pre-allocated ones are driven by
* INITIAL_VP_COUNT (number of EQ depends on number of VP) in block
* mode, otherwise we only preallocate INITIAL_BLK0_VP_COUNT on
* block 0.
*/
/* Direct SBE and IVT tables */
void *sbe_base;
void *ivt_base;
#ifdef USE_INDIRECT
/* Indirect END/EQ table. NULL entries are unallocated, count is
* the numbre of pointers (ie, sub page placeholders).
*/
uint64_t *eq_ind_base;
uint32_t eq_ind_count;
#else
void *eq_base;
#endif
/* EQ allocation bitmap. Each bit represent 8 EQs */
bitmap_t *eq_map;
#ifdef USE_INDIRECT
/* Indirect NVT/VP table. NULL entries are unallocated, count is
* the numbre of pointers (ie, sub page placeholders).
*/
uint64_t *vp_ind_base;
uint64_t vp_ind_count;
#else
void *vp_base;
#endif
#ifndef USE_BLOCK_GROUP_MODE
/* VP allocation buddy when not using block group mode */
struct buddy *vp_buddy;
#endif
#ifdef USE_INDIRECT
/* Pool of donated pages for provisioning indirect EQ and VP pages */
struct list_head donated_pages;
#endif
/* To ease a possible change to supporting more than one block of
* interrupts per chip, we store here the "base" global number
* and max number of interrupts for this chip. The global number
* encompass the block number and index.
*/
uint32_t int_base;
uint32_t int_max;
/* Due to the overlap between IPIs and HW sources in the IVT table,
* we keep some kind of top-down allocator. It is used for HW sources
* to "allocate" interrupt entries and will limit what can be handed
* out as IPIs. Of course this assumes we "allocate" all HW sources
* before we start handing out IPIs.
*
* Note: The numbers here are global interrupt numbers so that we can
* potentially handle more than one block per chip in the future.
*/
uint32_t int_hw_bot; /* Bottom of HW allocation */
uint32_t int_ipi_top; /* Highest IPI handed out so far + 1 */
/* The IPI allocation bitmap */
bitmap_t *ipi_alloc_map;
/* We keep track of which interrupts were ever enabled to
* speed up xive_reset
*/
bitmap_t *int_enabled_map;
/* Embedded source IPIs */
struct xive_src ipis;
};
/* Global DT node */
static struct dt_node *xive_dt_node;
/* Block <-> Chip conversions.
*
* As chipIDs may not be within the range of 16 block IDs supported by XIVE,
* we have a 2 way conversion scheme.
*
* From block to chip, use the global table below.
*
* From chip to block, a field in struct proc_chip contains the first block
* of that chip. For now we only support one block per chip but that might
* change in the future
*/
#define XIVE_INVALID_CHIP 0xffffffff
#define XIVE_MAX_CHIPS 16
static uint32_t xive_block_to_chip[XIVE_MAX_CHIPS];
static uint32_t xive_block_count;
/* Conversion between GIRQ and block/index.
*
* ------------------------------------
* |0000000E|BLOC| INDEX|
* ------------------------------------
* 8 4 20
*
* the E bit indicates that this is an escalation interrupt, in
* that case, the BLOC/INDEX represents the EQ containig the
* corresponding escalation descriptor.
*
* Global interrupt numbers for non-escalation interrupts are thus
* limited to 24 bits which is necessary for our XICS emulation since
* the top 8 bits are reserved for the CPPR value.
*
*/
#define GIRQ_TO_BLK(__g) (((__g) >> 20) & 0xf)
#define GIRQ_TO_IDX(__g) ((__g) & 0x000fffff)
#define BLKIDX_TO_GIRQ(__b,__i) (((uint32_t)(__b)) << 20 | (__i))
#define GIRQ_IS_ESCALATION(__g) ((__g) & 0x01000000)
#define MAKE_ESCALATION_GIRQ(__g)((__g) | 0x01000000)
/* Block/IRQ to chip# conversions */
#define PC_BLK_TO_CHIP(__b) (xive_block_to_chip[__b])
#define VC_BLK_TO_CHIP(__b) (xive_block_to_chip[__b])
#define GIRQ_TO_CHIP(__isn) (VC_BLK_TO_CHIP(GIRQ_TO_BLK(__isn)))
/* Routing of physical processors to VPs */
#ifdef USE_BLOCK_GROUP_MODE
#define PIR2VP_IDX(__pir) (0x80 | P9_PIR2LOCALCPU(__pir))
#define PIR2VP_BLK(__pir) (P9_PIR2GCID(__pir))
#define VP2PIR(__blk, __idx) (P9_PIRFROMLOCALCPU(VC_BLK_TO_CHIP(__blk), (__idx) & 0x7f))
#else
#define PIR2VP_IDX(__pir) (0x800 | (P9_PIR2GCID(__pir) << 7) | P9_PIR2LOCALCPU(__pir))
#define PIR2VP_BLK(__pir) (0)
#define VP2PIR(__blk, __idx) (P9_PIRFROMLOCALCPU(((__idx) >> 7) & 0xf, (__idx) & 0x7f))
#endif
/* Decoding of OPAL API VP IDs. The VP IDs are encoded as follow
*
* Block group mode:
*
* -----------------------------------
* |GVEOOOOO| INDEX|
* -----------------------------------
* || |
* || Order
* |Virtual
* Group
*
* G (Group) : Set to 1 for a group VP (not currently supported)
* V (Virtual) : Set to 1 for an allocated VP (vs. a physical processor ID)
* E (Error) : Should never be 1, used internally for errors
* O (Order) : Allocation order of the VP block
*
* The conversion is thus done as follow (groups aren't implemented yet)
*
* If V=0, O must be 0 and 24-bit INDEX value is the PIR
* If V=1, the order O group is allocated such that if N is the number of
* chip bits considered for allocation (*)
* then the INDEX is constructed as follow (bit numbers such as 0=LSB)
* - bottom O-N bits is the index within the "VP block"
* - next N bits is the XIVE blockID of the VP
* - the remaining bits is the per-chip "base"
* so the conversion consists of "extracting" the block ID and moving
* down the upper bits by N bits.
*
* In non-block-group mode, the difference is that the blockID is
* on the left of the index (the entire VP block is in a single
* block ID)
*/
#ifdef USE_BLOCK_GROUP_MODE
/* VP allocation */
static uint32_t xive_chips_alloc_bits = 0;
struct buddy *xive_vp_buddy;
struct lock xive_buddy_lock = LOCK_UNLOCKED;
/* VP# decoding/encoding */
static bool xive_decode_vp(uint32_t vp, uint32_t *blk, uint32_t *idx,
uint8_t *order, bool *group)
{
uint32_t o = (vp >> 24) & 0x1f;
uint32_t n = xive_chips_alloc_bits;
uint32_t index = vp & 0x00ffffff;
uint32_t imask = (1 << (o - n)) - 1;
/* Groups not supported yet */
if ((vp >> 31) & 1)
return false;
if (group)
*group = false;
/* PIR case */
if (((vp >> 30) & 1) == 0) {
if (blk)
*blk = PIR2VP_BLK(index);
if (idx)
*idx = PIR2VP_IDX(index);
return true;
}
/* Ensure o > n, we have *at least* 2 VPs per block */
if (o <= n)
return false;
/* Combine the index base and index */
if (idx)
*idx = ((index >> n) & ~imask) | (index & imask);
/* Extract block ID */
if (blk)
*blk = (index >> (o - n)) & ((1 << n) - 1);
/* Return order as well if asked for */
if (order)
*order = o;
return true;
}
static uint32_t xive_encode_vp(uint32_t blk, uint32_t idx, uint32_t order)
{
uint32_t vp = 0x40000000 | (order << 24);
uint32_t n = xive_chips_alloc_bits;
uint32_t imask = (1 << (order - n)) - 1;
vp |= (idx & ~imask) << n;
vp |= blk << (order - n);
vp |= idx & imask;
return vp;
}
#else /* USE_BLOCK_GROUP_MODE */
/* VP# decoding/encoding */
static bool xive_decode_vp(uint32_t vp, uint32_t *blk, uint32_t *idx,
uint8_t *order, bool *group)
{
uint32_t o = (vp >> 24) & 0x1f;
uint32_t index = vp & 0x00ffffff;
uint32_t imask = (1 << o) - 1;
/* Groups not supported yet */
if ((vp >> 31) & 1)
return false;
if (group)
*group = false;
/* PIR case */
if (((vp >> 30) & 1) == 0) {
if (blk)
*blk = PIR2VP_BLK(index);
if (idx)
*idx = PIR2VP_IDX(index);
return true;
}
/* Ensure o > 0, we have *at least* 2 VPs per block */
if (o == 0)
return false;
/* Extract index */
if (idx)
*idx = index & imask;
/* Extract block ID */
if (blk)
*blk = index >> o;
/* Return order as well if asked for */
if (order)
*order = o;
return true;
}
static uint32_t xive_encode_vp(uint32_t blk, uint32_t idx, uint32_t order)
{
return 0x40000000 | (order << 24) | (blk << order) | idx;
}
#endif /* !USE_BLOCK_GROUP_MODE */
#define xive_regw(__x, __r, __v) \
__xive_regw(__x, __r, X_##__r, __v, #__r)
#define xive_regr(__x, __r) \
__xive_regr(__x, __r, X_##__r, #__r)
#define xive_regwx(__x, __r, __v) \
__xive_regw(__x, 0, X_##__r, __v, #__r)
#define xive_regrx(__x, __r) \
__xive_regr(__x, 0, X_##__r, #__r)
#ifdef XIVE_VERBOSE_DEBUG
#define xive_vdbg(__x,__fmt,...) prlog(PR_DEBUG,"XIVE[ IC %02x ] " __fmt, (__x)->chip_id, ##__VA_ARGS__)
#define xive_cpu_vdbg(__c,__fmt,...) prlog(PR_DEBUG,"XIVE[CPU %04x] " __fmt, (__c)->pir, ##__VA_ARGS__)
#else
#define xive_vdbg(x,fmt,...) do { } while(0)
#define xive_cpu_vdbg(x,fmt,...) do { } while(0)
#endif
#define xive_dbg(__x,__fmt,...) prlog(PR_DEBUG,"XIVE[ IC %02x ] " __fmt, (__x)->chip_id, ##__VA_ARGS__)
#define xive_cpu_dbg(__c,__fmt,...) prlog(PR_DEBUG,"XIVE[CPU %04x] " __fmt, (__c)->pir, ##__VA_ARGS__)
#define xive_warn(__x,__fmt,...) prlog(PR_WARNING,"XIVE[ IC %02x ] " __fmt, (__x)->chip_id, ##__VA_ARGS__)
#define xive_cpu_warn(__c,__fmt,...) prlog(PR_WARNING,"XIVE[CPU %04x] " __fmt, (__c)->pir, ##__VA_ARGS__)
#define xive_err(__x,__fmt,...) prlog(PR_ERR,"XIVE[ IC %02x ] " __fmt, (__x)->chip_id, ##__VA_ARGS__)
#define xive_cpu_err(__c,__fmt,...) prlog(PR_ERR,"XIVE[CPU %04x] " __fmt, (__c)->pir, ##__VA_ARGS__)
static void __xive_regw(struct xive *x, uint32_t m_reg, uint32_t x_reg, uint64_t v,
const char *rname)
{
bool use_xscom = (m_reg == 0) || !x->ic_base;
int64_t rc;
x->last_reg_error = false;
if (use_xscom) {
assert(x_reg != 0);
rc = xscom_write(x->chip_id, x->xscom_base + x_reg, v);
if (rc) {
if (!rname)
rname = "???";
xive_err(x, "Error writing register %s\n", rname);
/* Anything else we can do here ? */
x->last_reg_error = true;
}
} else {
out_be64(x->ic_base + m_reg, v);
}
}
static uint64_t __xive_regr(struct xive *x, uint32_t m_reg, uint32_t x_reg,
const char *rname)
{
bool use_xscom = (m_reg == 0) || !x->ic_base;
int64_t rc;
uint64_t val;
x->last_reg_error = false;
if (use_xscom) {
rc = xscom_read(x->chip_id, x->xscom_base + x_reg, &val);
if (rc) {
if (!rname)
rname = "???";
xive_err(x, "Error reading register %s\n", rname);
/* Anything else we can do here ? */
x->last_reg_error = true;
return -1ull;
}
} else {
val = in_be64(x->ic_base + m_reg);
}
return val;
}
/* Locate a controller from an IRQ number */
static struct xive *xive_from_isn(uint32_t isn)
{
uint32_t chip_id = GIRQ_TO_CHIP(isn);
struct proc_chip *c = get_chip(chip_id);
if (!c)
return NULL;
return c->xive;
}
static struct xive *xive_from_pc_blk(uint32_t blk)
{
uint32_t chip_id = PC_BLK_TO_CHIP(blk);
struct proc_chip *c = get_chip(chip_id);
if (!c)
return NULL;
return c->xive;
}
static struct xive *xive_from_vc_blk(uint32_t blk)
{
uint32_t chip_id = VC_BLK_TO_CHIP(blk);
struct proc_chip *c = get_chip(chip_id);
if (!c)
return NULL;
return c->xive;
}
static struct xive_eq *xive_get_eq(struct xive *x, unsigned int idx)
{
struct xive_eq *p;
#ifdef USE_INDIRECT
if (idx >= (x->eq_ind_count * EQ_PER_PAGE))
return NULL;
p = (struct xive_eq *)(x->eq_ind_base[idx / EQ_PER_PAGE] &
VSD_ADDRESS_MASK);
if (!p)
return NULL;
return &p[idx % EQ_PER_PAGE];
#else
if (idx >= MAX_EQ_COUNT)
return NULL;
if (!x->eq_base)
return NULL;
p = x->eq_base;
return p + idx;
#endif
}
static struct xive_ive *xive_get_ive(struct xive *x, unsigned int isn)
{
struct xive_ive *ivt;
uint32_t idx = GIRQ_TO_IDX(isn);
if (GIRQ_IS_ESCALATION(isn)) {
/* Allright, an escalation IVE is buried inside an EQ, let's
* try to find it
*/
struct xive_eq *eq;
if (x->chip_id != VC_BLK_TO_CHIP(GIRQ_TO_BLK(isn))) {
xive_err(x, "xive_get_ive, ESC ISN 0x%x not on right chip\n", isn);
return NULL;
}
eq = xive_get_eq(x, idx);
if (!eq) {
xive_err(x, "xive_get_ive, ESC ISN 0x%x EQ not found\n", isn);
return NULL;
}
return (struct xive_ive *)(char *)&eq->w4;
} else {
/* Check the block matches */
if (isn < x->int_base || isn >= x->int_max) {
xive_err(x, "xive_get_ive, ISN 0x%x not on right chip\n", isn);
return NULL;
}
assert (idx < MAX_INT_ENTRIES);
/* If we support >1 block per chip, this should still work as
* we are likely to make the table contiguous anyway
*/
ivt = x->ivt_base;
assert(ivt);
return ivt + idx;
}
}
static struct xive_vp *xive_get_vp(struct xive *x, unsigned int idx)
{
struct xive_vp *p;
#ifdef USE_INDIRECT
assert(idx < (x->vp_ind_count * VP_PER_PAGE));
p = (struct xive_vp *)(x->vp_ind_base[idx / VP_PER_PAGE] &
VSD_ADDRESS_MASK);
if (!p)
return NULL;
return &p[idx % VP_PER_PAGE];
#else
assert(idx < MAX_VP_COUNT);
p = x->vp_base;
return p + idx;
#endif
}
static void xive_init_default_vp(struct xive_vp *vp,
uint32_t eq_blk, uint32_t eq_idx)
{
/* Stash the EQ base in the pressure relief interrupt field
* and set the ACK# to 0xff to disable pressure relief interrupts
*/
vp->w1 = (eq_blk << 28) | eq_idx;
vp->w5 = 0xff000000;
lwsync();
vp->w0 = VP_W0_VALID;
}
static void xive_init_default_eq(uint32_t vp_blk, uint32_t vp_idx,
struct xive_eq *eq, void *backing_page,
uint8_t prio)
{
eq->w1 = EQ_W1_GENERATION;
eq->w3 = ((uint64_t)backing_page) & 0xffffffff;
eq->w2 = (((uint64_t)backing_page)) >> 32 & 0x0fffffff;
eq->w6 = SETFIELD(EQ_W6_NVT_BLOCK, 0ul, vp_blk) |
SETFIELD(EQ_W6_NVT_INDEX, 0ul, vp_idx);
eq->w7 = SETFIELD(EQ_W7_F0_PRIORITY, 0ul, prio);
eieio();
eq->w0 = EQ_W0_VALID | EQ_W0_ENQUEUE |
SETFIELD(EQ_W0_QSIZE, 0ul, EQ_QSIZE_64K) |
EQ_W0_FIRMWARE;
#ifdef EQ_ALWAYS_NOTIFY
eq->w0 |= EQ_W0_UCOND_NOTIFY;
#endif
}
static uint32_t *xive_get_eq_buf(uint32_t eq_blk, uint32_t eq_idx)
{
struct xive *x = xive_from_vc_blk(eq_blk);
struct xive_eq *eq = xive_get_eq(x, eq_idx);
uint64_t addr;
assert(eq);
assert(eq->w0 & EQ_W0_VALID);
addr = (((uint64_t)eq->w2) & 0x0fffffff) << 32 | eq->w3;
return (uint32_t *)addr;
}
#ifdef USE_INDIRECT
static void *xive_get_donated_page(struct xive *x __unused)
{
return (void *)list_pop_(&x->donated_pages, 0);
}
#endif
#define XIVE_ALLOC_IS_ERR(_idx) ((_idx) >= 0xfffffff0)
#define XIVE_ALLOC_NO_SPACE 0xffffffff /* No possible space */
#define XIVE_ALLOC_NO_IND 0xfffffffe /* Indirect need provisioning */
#define XIVE_ALLOC_NO_MEM 0xfffffffd /* Local allocation failed */
static uint32_t xive_alloc_eq_set(struct xive *x, bool alloc_indirect __unused)
{
uint32_t ind_idx __unused;
int idx;
xive_vdbg(x, "Allocating EQ set...\n");
assert(x->eq_map);
/* Allocate from the EQ bitmap. Each bit is 8 EQs */
idx = bitmap_find_zero_bit(*x->eq_map, 0, MAX_EQ_COUNT >> 3);
if (idx < 0) {
xive_dbg(x, "Allocation from EQ bitmap failed !\n");
return XIVE_ALLOC_NO_SPACE;
}
bitmap_set_bit(*x->eq_map, idx);
idx <<= 3;
xive_vdbg(x, "Got EQs 0x%x..0x%x\n", idx, idx + 7);
#ifdef USE_INDIRECT
/* Calculate the indirect page where the EQs reside */
ind_idx = idx / EQ_PER_PAGE;
/* Is there an indirect page ? If not, check if we can provision it */
if (!x->eq_ind_base[ind_idx]) {
/* Default flags */
uint64_t vsd_flags = SETFIELD(VSD_TSIZE, 0ull, 4) |
SETFIELD(VSD_MODE, 0ull, VSD_MODE_EXCLUSIVE);
void *page;
/* If alloc_indirect is set, allocate the memory from OPAL own,
* otherwise try to provision from the donated pool
*/
if (alloc_indirect) {
/* Allocate/provision indirect page during boot only */
xive_dbg(x, "Indirect empty, provisioning from local pool\n");
page = local_alloc(x->chip_id, 0x10000, 0x10000);
if (!page) {
xive_dbg(x, "provisioning failed !\n");
return XIVE_ALLOC_NO_MEM;
}
vsd_flags |= VSD_FIRMWARE;
} else {
xive_dbg(x, "Indirect empty, provisioning from donated pages\n");
page = xive_get_donated_page(x);
if (!page) {
xive_dbg(x, "none available !\n");
return XIVE_ALLOC_NO_IND;
}
}
memset(page, 0, 0x10000);
x->eq_ind_base[ind_idx] = vsd_flags | (((uint64_t)page) & VSD_ADDRESS_MASK);
/* Any cache scrub needed ? */
}
#endif /* USE_INDIRECT */
return idx;
}
static void xive_free_eq_set(struct xive *x, uint32_t eqs)
{
uint32_t idx;
xive_vdbg(x, "Freeing EQ set...\n");
assert((eqs & 7) == 0);
assert(x->eq_map);
idx = eqs >> 3;
bitmap_clr_bit(*x->eq_map, idx);
}
#ifdef USE_INDIRECT
static bool xive_provision_vp_ind(struct xive *x, uint32_t vp_idx, uint32_t order)
{
uint32_t pbase, pend, i;
pbase = vp_idx / VP_PER_PAGE;
pend = (vp_idx + (1 << order)) / VP_PER_PAGE;
for (i = pbase; i <= pend; i++) {
void *page;
/* Already provisioned ? */
if (x->vp_ind_base[i])
continue;
/* Try to grab a donated page */
page = xive_get_donated_page(x);
if (!page)
return false;
/* Install the page */
memset(page, 0, 0x10000);
x->vp_ind_base[i] = ((uint64_t)page) & VSD_ADDRESS_MASK;
x->vp_ind_base[i] |= SETFIELD(VSD_TSIZE, 0ull, 4);
x->vp_ind_base[i] |= SETFIELD(VSD_MODE, 0ull, VSD_MODE_EXCLUSIVE);
}
return true;
}
#else
static inline bool xive_provision_vp_ind(struct xive *x __unused,
uint32_t vp_idx __unused,
uint32_t order __unused)
{
return true;
}
#endif /* USE_INDIRECT */
#ifdef USE_BLOCK_GROUP_MODE
static void xive_init_vp_allocator(void)
{
/* Initialize chip alloc bits */
xive_chips_alloc_bits = ilog2(xive_block_count);
prlog(PR_INFO, "XIVE: %d chips considered for VP allocations\n",
1 << xive_chips_alloc_bits);
/* Allocate a buddy big enough for MAX_VP_ORDER allocations.
*
* each bit in the buddy represents 1 << xive_chips_alloc_bits
* VPs.
*/
xive_vp_buddy = buddy_create(MAX_VP_ORDER);
assert(xive_vp_buddy);
/* We reserve the whole range of VPs representing HW chips.
*
* These are 0x80..0xff, so order 7 starting at 0x80. This will
* reserve that range on each chip.
*
* XXX This can go away if we just call xive_reset ..
*/
assert(buddy_reserve(xive_vp_buddy, 0x80, 7));
}
static uint32_t xive_alloc_vps(uint32_t order)
{
uint32_t local_order, i;
int vp;
/* The minimum order is 2 VPs per chip */
if (order < (xive_chips_alloc_bits + 1))
order = xive_chips_alloc_bits + 1;
/* We split the allocation */
local_order = order - xive_chips_alloc_bits;
/* We grab that in the global buddy */
assert(xive_vp_buddy);
lock(&xive_buddy_lock);
vp = buddy_alloc(xive_vp_buddy, local_order);
unlock(&xive_buddy_lock);
if (vp < 0)
return XIVE_ALLOC_NO_SPACE;
/* Provision on every chip considered for allocation */
for (i = 0; i < (1 << xive_chips_alloc_bits); i++) {
struct xive *x = xive_from_pc_blk(i);
bool success;
/* Return internal error & log rather than assert ? */
assert(x);