Bug report: minstret counts with an offset

[flaviens]

Hi there!

I discovered a little bug in BOOM.
The riscv 1.12 privileged spec states:

Any CSR write takes effect after the writing instruction has otherwise completed.

However, this seems not to be respected by BOOM.

Example snippet

The stored value of t0 should be 0, however with BOOM it is 1. Spike, CVA6 and Rocket count without the offset that we observe on BOOM.

  .section ".text.init","ax",@progbits
  .globl _start
  .align 2
_start:

  li a0, 0x60000010

  csrrw zero, minstret, zero
  csrrw t0, minstret, zero

  sw t0, (a0)
  sw zero, (zero)

infinite_loop0:
  j infinite_loop0

RTL implications
Minor RTL modification.

What is the use case for changing the behavior?
RISC-V compliant instruction counting.

I'm using Chipyard 1.8.1.

Thanks!