Behavior of BOOM for WFI instructions

[nishanthsmurthy24]

Type of issue: question

Other information

This is the first few lines of Output Trace I obtained from the Chipyard Instantiation of BOOM.

rv64ui-p-simple.out from BOOM Configuration

using random seed 1690234558
This emulator compiled with JTAG Remote Bitbang client. To enable, use +jtag_rbb_enable=1.
Listening on port 43713
== Loading device model file '/root/chipyard/generators/testchipip/src/main/resources/dramsim2_ini/DDR3_micron_64M_8B_x4_sg15.ini' == 
== Loading system model file '/root/chipyard/generators/testchipip/src/main/resources/dramsim2_ini/system.ini' == 
===== MemorySystem 0 =====
CH. 0 TOTAL_STORAGE : 4096MB | 1 Ranks | 16 Devices per rank
DRAMSim2 Clock Frequency =666666666Hz, CPU Clock Frequency=100000000Hz
        27 [3] pc=[0x0000000000010040] inst=[0x00000517] x10 0x0000000000010040
        33 [3] pc=[0x0000000000010044] inst=[0xfc050513] x10 0x0000000000010000
        41 [3] pc=[0x0000000000010048] inst=[0x30551073]
        55 [3] pc=[0x000000000001004c] inst=[0x301022f3] x 5 0x800000000014112d
        69 [3] pc=[0x0000000000010050] inst=[0x4122d293] x 5 0xffffe00000000005
        70 [3] pc=[0x0000000000010054] inst=[0x0012f293] x 5 0x0000000000000001
        71 [3] pc=[0x0000000000010058] inst=[0x00028463]
        79 [3] pc=[0x000000000001005c] inst=[0x30301073]
        93 [3] pc=[0x0000000000010060] inst=[0x00800513] x10 0x0000000000000008                  // li    a0, 8
       101 [3] pc=[0x0000000000010064] inst=[0x30451073]                                         // csrw  mie, a0
       115 [3] pc=[0x0000000000010068] inst=[0x30052073]                                         // csrs  mstatus, a0
      3523 [3] pc=[0x000000000001006c] inst=[0x10500073]                                         // wfi
      3559 [3] pc=[0x0000000000010000] inst=[0x020005b7] x11 0x0000000002000000
      3567 [3] pc=[0x0000000000010004] inst=[0xf1402573] x10 0x0000000000000000
      3581 [3] pc=[0x0000000000010008] inst=[0x00050463]
      3584 [3] pc=[0x0000000000010010] inst=[0x00458613] x12 0x0000000002000004
      3585 [3] pc=[0x0000000000010014] inst=[0x00100693] x13 0x0000000000000001
      3586 [3] pc=[0x0000000000010018] inst=[0x00d62023]
      3587 [3] pc=[0x000000000001001c] inst=[0x00460613] x12 0x0000000002000008
      3611 [3] pc=[0x0000000000010020] inst=[0xffc62683] x13 0x0000000000000000

rv64ui-p-simple.out from Default Rocket Configuration

using random seed 1690222866
This emulator compiled with JTAG Remote Bitbang client. To enable, use +jtag_rbb_enable=1.
Listening on port 43329
== Loading device model file '/root/chipyard/generators/testchipip/src/main/resources/dramsim2_ini/DDR3_micron_64M_8B_x4_sg15.ini' == 
== Loading system model file '/root/chipyard/generators/testchipip/src/main/resources/dramsim2_ini/system.ini' == 
===== MemorySystem 0 =====
CH. 0 TOTAL_STORAGE : 4096MB | 1 Ranks | 16 Devices per rank
DRAMSim2 Clock Frequency =666666666Hz, CPU Clock Frequency=100000000Hz
C0:         19 [1] pc=[0000000000010040] W[r10=0000000000010040][1] R[r 0=0000000000000000] R[r 0=0000000000000000] inst=[00000517] auipc   a0, 0x0
C0:         20 [1] pc=[0000000000010044] W[r10=0000000000010000][1] R[r10=0000000000010040] R[r 0=0000000000000000] inst=[fc050513] addi    a0, a0, -64
C0:         21 [1] pc=[0000000000010048] W[r 0=0000000000000000][1] R[r10=0000000000010000] R[r 0=0000000000000000] inst=[30551073] csrw    mtvec, a0
C0:         26 [1] pc=[000000000001004c] W[r 5=800000000094112d][1] R[r 0=0000000000000000] R[r 0=0000000000000000] inst=[301022f3] csrr    t0, misa
C0:         29 [1] pc=[0000000000010050] W[r 5=ffffe00000000025][1] R[r 5=800000000094112d] R[r 0=0000000000000000] inst=[4122d293] srai    t0, t0, 18
C0:         30 [1] pc=[0000000000010054] W[r 5=0000000000000001][1] R[r 5=ffffe00000000025] R[r 0=0000000000000000] inst=[0012f293] andi    t0, t0, 1
C0:         31 [1] pc=[0000000000010058] W[r 0=0000000000000000][0] R[r 5=0000000000000001] R[r 0=0000000000000000] inst=[00028463] beqz    t0, pc + 8
C0:         32 [1] pc=[000000000001005c] W[r 0=0000000000000000][1] R[r 0=0000000000000000] R[r 0=0000000000000000] inst=[30301073] csrw    mideleg, zero
C0:         37 [1] pc=[0000000000010060] W[r10=0000000000000008][1] R[r 0=0000000000000000] R[r 0=0000000000000000] inst=[00800513] li      a0, 8
C0:         38 [1] pc=[0000000000010064] W[r 0=0000000000000000][1] R[r10=0000000000000008] R[r 0=0000000000000000] inst=[30451073] csrw    mie, a0
C0:         43 [1] pc=[0000000000010068] W[r 0=0000000a00001800][1] R[r10=0000000000000008] R[r 0=0000000000000000] inst=[30052073] csrs    mstatus, a0
C0:         48 [1] pc=[000000000001006c] W[r 0=0000000000000000][0] R[r 0=0000000000000000] R[r 0=0000000000000000] inst=[10500073] wfi
C0:         51 [0] pc=[0000000000010070] W[r 0=0000000000000000][0] R[r31=0000000000000008] R[r 0=0000000000000000] inst=[ffdff06f] j       pc - 0x4
C0:         70 [1] pc=[0000000000010000] W[r11=0000000002000000][1] R[r 0=0000000000000000] R[r 0=0000000000000000] inst=[020005b7] lui     a1, 0x2000
C0:         71 [1] pc=[0000000000010004] W[r10=0000000000000000][1] R[r 0=0000000000000000] R[r 0=0000000000000000] inst=[f1402573] csrr    a0, mhartid
C0:         74 [1] pc=[0000000000010008] W[r 0=0000000000000000][0] R[r10=0000000000000000] R[r 0=0000000000000000] inst=[00050463] beqz    a0, pc + 8
C0:         78 [1] pc=[0000000000010010] W[r12=0000000002000004][1] R[r11=0000000002000000] R[r 0=0000000000000000] inst=[00458613] addi    a2, a1, 4
C0:         79 [1] pc=[0000000000010014] W[r13=0000000000000001][1] R[r 0=0000000000000000] R[r 0=0000000000000000] inst=[00100693] li      a3, 1
C0:         80 [1] pc=[0000000000010018] W[r 0=0000000000000000][0] R[r12=0000000002000004] R[r13=0000000000000001] inst=[00d62023] sw      a3, 0(a2)
C0:         81 [1] pc=[000000000001001c] W[r12=0000000002000008][1] R[r12=0000000002000004] R[r 0=0000000000000000] inst=[00460613] addi    a2, a2, 4
C0:         87 [1] pc=[0000000000010020] W[r13=0000000000000000][0] R[r12=0000000002000008] R[r 0=0000000000000000] inst=[ffc62683] lw      a3, -4(a2)

What is the current behavior?
There is a huge latency between the execution of the CSRS instruction and the WFI instruction in BOOM Configuration (Cycle 115-3523).

This huge latency/stall is not observed on any Rocket Configuration (Cycle 48-51)

Please tell us about your environment:

This is my BOOM configuration on Chipyard

class SmallBoomConfig extends Config(
  new boom.common.WithBoomCommitLogPrintf ++                          // small boom config
  new boom.common.WithNSmallBooms(1) ++
  new chipyard.config.AbstractConfig)

In both BOOM and Rocket Documentation, the behavior of WFI instruction execution is not outlined.

[jerryz123]

WFI behavior can vary across implementations. Also, the cycle at which the interrupt arrives may vary across SoC configurations