bug report: A core with prefetcher will trigger a page fault when starting kernel.

[fangjiangff]

Type of issue: bug report

Impact: unknown

Development Phase: proposal

I tried to run programs on Xilinx KC705 with a medium Boom core with prefething. But I found that when enable prefetching, it is can't boot the OS due to triggering a page fault.

Here's my process:

1. In chipyard/generators/boom/src/main/scala/common/config-mixins.scala, I modified WithNMediumBooms by adding enablePrefetching = true to enable the Next-Line prefetcher.
2. Using Vivado 2021.2, I synthesized the medium Boom core with prefetcher and generated the bitstream. Burn the bitstream onto FPGA.
3. When starting kernel, a load page fault was triggered.

The serial port printouts are as follows:

[20:25:48.966] Starting kernel ...
……
[20:25:50.665] [    0.576346] Unable to handle kernel paging request at virtual address ffffffffffffffa0
[20:25:50.667] [    0.584870] Oops [#1]
[20:25:50.675] [    0.587248] Modules linked in:
[20:25:50.677] [    0.590466] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.18.18-dirty #1
[20:25:50.685] [    0.597158] Hardware name: freechips,rocketchip-vivado (DT)
[20:25:50.687] [    0.602812] epc : slab_unmergeable+0x10/0x46
[20:25:50.689] [    0.607318]  ra : find_mergeable+0xaa/0x106
[20:25:50.704] [    0.611664] epc : ffffffff800fb00e ra : ffffffff800fb0ee sp : ffffffd801683c80
[20:25:50.707] [    0.619006]  gp : ffffffff812cd430 tp : ffffffd8016f8000 t0 : 6574694c2d504455
[20:25:50.711] [    0.626328]  t1 : ffffffff8037cfa0 t2 : 206574694c2d5044 s0 : ffffffd801683c90
[20:25:50.718] [    0.633654]  s1 : 0000000000000440 a0 : ffffffffffffff98 a1 : 0000000000002000
[20:25:50.734] [    0.640980]  a2 : ffffffff812b3c20 a3 : 0000000000000240 a4 : 0000000000000000
[20:25:50.737] [    0.648298]  a5 : 0000000000000000 a6 : 0000000000000040 a7 : ffffffd8017e4000
[20:25:50.741] [    0.655614]  s2 : ffffffffffffff98 s3 : ffffffffffffffc0 s4 : 0000000000002000
[20:25:50.755] [    0.662930]  s5 : ffffffff81289660 s6 : 000000000002c000 s7 : 0000000000000007
[20:25:50.757] [    0.670248]  s8 : ffffffff81289610 s9 : 0000000000000008 s10: 0000000000002000
[20:25:50.763] [    0.677566]  s11: 0000000000000440 t3 : ffffffff812e001f t4 : ffffffff812e001f
[20:25:50.775] [    0.684892]  t5 : ffffffff812e0020 t6 : ffffffd801683a58
[20:25:50.776] [    0.690282] status: 0000000200000120 badaddr: ffffffffffffffa0 cause: 000000000000000d
[20:25:50.784] [    0.702004] ---[ end trace 0000000000000000 ]---
[20:25:50.793] [    0.707060] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b
[20:25:50.801] [    0.714892] ---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b ]---

I attempted to modify the mem_xcpt_valids signal in lsu.scala to ignore errors generated by the prefetcher. Is this approach reasonable?

  val mem_xcpt_valids = RegNext(widthMap(w =>
                     (pf_ld(w) || pf_st(w) || ae_ld(w) || ae_st(w) || ma_ld(w) || ma_st(w)) &&
                      !io.core.exception &&
                      !IsKilledByBranch(io.core.brupdate, exe_tlb_uop(w)) &&
                      !isPrefetch(dtlb.io.req(w).bits.cmd) )) //new added 

It works for the default Next-Line prefetcher. But after I changed to my custom prefetcher, I still can't start the kernel, it gets stuck. So I'm guessing that the fault caused by prefetching is still not handled correctly.

I desperately want to know how to fix this problem. Thank you.

my environment:

• Chipyard: 1.8.0 commit at 2d03d10
• BoomV3: commit at fac2c37
• U-Boot: 2022.01-dirty
• Linux : 5.18.18-dirty
• FPGA : Xillix kc705