issue about ocelot RTL generate

[menglinhan]

Hello, I want to generate ocelot RTL verilog. Now I meet some issues. When I check out 1.10.0 chipyard, and download ocelot to replace boom. Then run " make CONFIG=LargeBoomConfig" under "sim/verilator", the tool reported error as follow:
"chipyard/generators/boom/src/main/scala/exu/core.scala:1118:23: value set_vtype is not a member of chisel3.Bundle{val vconfig: freechips.rocketchip.rocket.VConfig; val vstart: chisel3.UInt; val vxrm: chisel3.UInt; val set_vs_dirty: chisel3.Bool; val set_vconfig: chisel3.util.Valid[freechips.rocketchip.rocket.VConfig]; val set_vstart: chisel3.util.Valid[chisel3.UInt]; val set_vxsat: chisel3.Bool}
[error] csr.io.vector.get.set_vtype := exe_units.vec_exe_unit.io.ovi.set_vtype"
Is this chipyard version issue? which version chipyard should I checkout if I want to generate ocelot RTL?