/
powerpc.json
252 lines (252 loc) · 6.9 KB
/
powerpc.json
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{
"platform": "powerpc",
"intrinsic_prefix": "_vec_",
"llvm_prefix": "llvm.ppc.altivec.",
"number_info": {
"unsigned": {
"kind" : "u",
"data_type_short": { "8": "b", "16": "h", "32": "w", "64": "d" }
},
"signed": {
"kind" : "s",
"data_type_short": { "8": "b", "16": "h", "32": "w", "64": "d" }
},
"float": {}
},
"width_info": {
"128": { "width": "" }
},
"intrinsics": [
{
"intrinsic": "perm",
"width": [128],
"llvm": "vperm",
"ret": "s32",
"args": ["0", "0", "s8"]
},
{
"intrinsic": "mradds",
"width": [128],
"llvm": "vmhraddshs",
"ret": "s16",
"args": ["0", "0", "0"]
},
{
"intrinsic": "cmpb",
"width": [128],
"llvm": "vcmpbfp",
"ret": "s32",
"args": ["f32", "f32"]
},
{
"intrinsic": "cmpeq{0.data_type_short}",
"width": [128],
"llvm": "vcmpequ{0.data_type_short}",
"ret": "s(8-32)",
"args": ["0", "0"]
},
{
"intrinsic": "cmpgt{1.kind}{1.data_type_short}",
"width": [128],
"llvm": "vcmpgt{1.kind}{1.data_type_short}",
"ret": "s(8-32)",
"args": ["0u", "1"]
},
{
"intrinsic": "cmpgt{1.kind}{1.data_type_short}",
"width": [128],
"llvm": "vcmpgt{1.kind}{1.data_type_short}",
"ret": "s(8-32)",
"args": ["0", "1"]
},
{
"intrinsic": "max{0.kind}{0.data_type_short}",
"width": [128],
"llvm": "vmax{0.kind}{0.data_type_short}",
"ret": "i(8-32)",
"args": ["0", "0"]
},
{
"intrinsic": "min{0.kind}{0.data_type_short}",
"width": [128],
"llvm": "vmin{0.kind}{0.data_type_short}",
"ret": "i(8-32)",
"args": ["0", "0"]
},
{
"intrinsic": "sub{0.kind}{0.data_type_short}s",
"width": [128],
"llvm": "vsub{0.kind}{0.data_type_short}s",
"ret": "i(8-32)",
"args": ["0", "0"]
},
{
"intrinsic": "subc",
"width": [128],
"llvm": "vsubcuw",
"ret": "u32",
"args": ["0", "0"]
},
{
"intrinsic": "add{0.kind}{0.data_type_short}s",
"width": [128],
"llvm": "vadd{0.kind}{0.data_type_short}s",
"ret": "i(8-32)",
"args": ["0", "0"]
},
{
"intrinsic": "addc",
"width": [128],
"llvm": "vaddcuw",
"ret": "u32",
"args": ["0", "0"]
},
{
"intrinsic": "mule{1.kind}{1.data_type_short}",
"width": [128],
"llvm": "vmule{0.kind}{1.data_type_short}",
"ret": "i(16-32)",
"args": ["0N", "1"]
},
{
"intrinsic": "mulo{1.kind}{1.data_type_short}",
"width": [128],
"llvm": "vmulo{0.kind}{1.data_type_short}",
"ret": "i(16-32)",
"args": ["0N", "1"]
},
{
"intrinsic": "avg{0.kind}{0.data_type_short}",
"width": [128],
"llvm": "vavg{0.kind}{0.data_type_short}",
"ret": "i(8-32)",
"args": ["0", "0"]
},
{
"intrinsic": "packs{0.kind}{1.data_type_short}",
"width": [128],
"llvm": "vpk{0.kind}{1.data_type_short}{0.kind}s",
"ret": "i(8-16)",
"args": ["0W", "1"]
},
{
"intrinsic": "packsu{1.kind}{1.data_type_short}",
"width": [128],
"llvm": "vpk{1.kind}{1.data_type_short}{0.kind}s",
"ret": "u(8-16)",
"args": ["0Ws", "1"]
},
{
"intrinsic": "packpx",
"width": [128],
"llvm": "vpkpx",
"ret": "s16",
"args": ["s32", "s32"]
},
{
"intrinsic": "unpackl{1.kind}{1.data_type_short}",
"width": [128],
"llvm": "vupkl{1.kind}{1.data_type_short}",
"ret": "s(16-32)",
"args": ["0N"]
},
{
"intrinsic": "unpackh{1.kind}{1.data_type_short}",
"width": [128],
"llvm": "vupkh{1.kind}{1.data_type_short}",
"ret": "s(16-32)",
"args": ["0N"]
},
{
"intrinsic": "madds",
"width": [128],
"llvm": "vmhaddshs",
"ret": "s16",
"args": ["0", "0", "0"]
},
{
"intrinsic": "msumu{1.data_type_short}m",
"width": [128],
"llvm": "vmsumu{1.data_type_short}m",
"ret": "u32",
"args": ["u(8-16)", "1", "u32"]
},
{
"intrinsic": "msummbm",
"width": [128],
"llvm": "vmsummbm",
"ret": "s32",
"args": ["s8", "u8", "s32"]
},
{
"intrinsic": "msumshm",
"width": [128],
"llvm": "vmsumshm",
"ret": "s32",
"args": ["s16", "s16", "s32"]
},
{
"intrinsic": "msum{0.kind}hs",
"width": [128],
"llvm": "vmsum{0.kind}hs",
"ret": "i32",
"args": ["0N", "0N", "0"]
},
{
"intrinsic": "sum2s",
"width": [128],
"llvm": "vsum2sws",
"ret": "s32",
"args": ["0", "0"]
},
{
"intrinsic": "sum4{0.kind}bs",
"width": [128],
"llvm": "vsum4{0.kind}bs",
"ret": "i32",
"args": ["0NN", "0"]
},
{
"intrinsic": "sum4shs",
"width": [128],
"llvm": "vsum4shs",
"ret": "s32",
"args": ["0N", "0"]
},
{
"intrinsic": "sums",
"width": [128],
"llvm": "vsumsws",
"ret": "s32",
"args": ["0", "0"]
},
{
"intrinsic": "madd",
"width": [128],
"llvm": "vmaddfp",
"ret": "f32",
"args": ["0", "0", "0"]
},
{
"intrinsic": "expte",
"width": [128],
"llvm": "vexptefp",
"ret": "f32",
"args": ["0"]
},
{
"intrinsic": "floor",
"width": [128],
"llvm": "vrfim",
"ret": "f32",
"args": ["0"]
},
{
"intrinsic": "loge",
"width": [128],
"llvm": "vlogefp",
"ret": "f32",
"args": ["0"]
}
]
}