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This issue is a tracker for adding baseline Morello support including a new CPU and platforms. It is just like any other AArch64 CPU/platform without any CHERI support. Currently, I have Morello ports of seL4 passing all sel4test on QEMU, FVP, and the Morello hardware board. This could build with GCC or LLVM/lld. Initial sel4bench numbers running on the board are attached. While this is a baseline for RFC-15 (as a dependency), it's independent from it whether there's future CHERI support or not. I'll gradually be submitting PRs for this issue and update it accordingly.
There are 4 major efforts for this issue:
Enable building/running with LLVM/lld.
This is not a blocker for baseline support as it could also build with GCC. But it's good to make sure the baseline could also build with LLVM/lld for future CHERI support.
This issue is a tracker for adding baseline Morello support including a new CPU and platforms. It is just like any other AArch64 CPU/platform without any CHERI support. Currently, I have Morello ports of seL4 passing all sel4test on QEMU, FVP, and the Morello hardware board. This could build with GCC or LLVM/lld. Initial sel4bench numbers running on the board are attached. While this is a baseline for RFC-15 (as a dependency), it's independent from it whether there's future CHERI support or not. I'll gradually be submitting PRs for this issue and update it accordingly.
There are 4 major efforts for this issue:
Enable building/running with LLVM/lld.
This is not a blocker for baseline support as it could also build with GCC. But it's good to make sure the baseline could also build with LLVM/lld for future CHERI support.
seL4 kernel port
sel4test
sel4bench
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