easy_z80_no_wdog.pld

GAL16V8    ;  Works with GAL16V8B and ATF16V8B
EASY_Z80   ;  Easy Z80

MREQ	IORQ	WR	M1	A2	A3	A4	A5	A6	GND
A7	RAMCSI	WDOG	MA19	PGENWR	PAGEWR	ROMCS	SIOCS	CTCCS	VCC

/ROMCS  = /MREQ * /MA19

/RAMCSI = /MREQ *  MA19

/CTCCS  = /IORQ * M1 *  A7 * /A6 * /A5 * /A4 *  A3 * /A2

/SIOCS  = /IORQ * M1 *  A7 * /A6 * /A5 * /A4 * /A3 * /A2

/PAGEWR = /IORQ * M1 * /A7 *  A6 *  A5 *  A4 *  A3 * /A2 * /WR 

/PGENWR = /IORQ * M1 * /A7 *  A6 *  A5 *  A4 *  A3 *  A2 * /WR 

WDOG    = M1

DESCRIPTION

This is the address decode logic for Easy Z80 single board.
It implements the following functions:
1. ROM chip select - ROMCS. This signal is activated for memory accesses to
   0x00000 - 0x7FFFF address range
2. RAM chip select - RAMCSI. This signal is activated for memory accesses to
   0x80000 - 0xFFFFF address range
3. CTC chip select - CTCCS. This signal is activated for I/O accesses to
   ports in 0x88-0x8B range
4. SIO chip select - SIOCS. This signal is activated for I/O accesses to
   ports in 0x80-0x83 range
5. Page register write - PAGEWR. This signal is activated by I/O writes
   to the ports in 0x78-0x7B range
6. Page enable register write - PGEN. This signal is activated by I/O writes
   to the ports in 0x7C-0x7F range
7. Watchdog signal - WDOG. This signal mirrors CPU /M1 signal, and therefore
   it is pulsed on every instruction fetch cycle