Fix Verilog backend regression introduced in f6bee8a

ucb-bar · Feb 12, 2014 · 0bbe501 · 0bbe501
1 parent a78d2d0
commit 0bbe501
Showing 1 changed file with 2 additions and 4 deletions.
diff --git a/src/main/scala/Reg.scala b/src/main/scala/Reg.scala
@@ -177,10 +177,8 @@ class Reg extends Delay with proc {
       ChiselError.error("reassignment to Reg");
     }
     val cond = Module.current.whenCond
-    if (Module.current.hasWhenCond) {
-      enable = if (isEnable) enable || cond else cond
-      isEnable = true
-    }
+    enable = if (isEnable) enable || cond else cond
+    isEnable = true
     updates += ((cond, src))
   }
   override def genMuxes(default: Node): Unit = {