change consumers into a set to make addConsumers in Node.scala fast

ucb-bar · Sep 23, 2014 · d7e9130 · d7e9130
1 parent a39c41a
commit d7e9130
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Showing 5 changed files with 14 additions and 15 deletions.
diff --git a/src/main/scala/Backend.scala b/src/main/scala/Backend.scala
@@ -301,7 +301,7 @@ abstract class Backend extends FileSystemUtilities{
 
     for ((name, i) <- inputs) {
       if (i.inputs.length == 0 && m != Driver.topComponent)
-        if (i.consumers.length > 0) {
+        if (i.consumers.size > 0) {
           if (Driver.warnInputs)
             ChiselError.warning({"UNCONNECTED INPUT " + emitRef(i) + " in COMPONENT " + i.component +
                                  " has consumers"})
@@ -315,10 +315,10 @@ abstract class Backend extends FileSystemUtilities{
 
     for ((name, o) <- outputs) {
       if (o.inputs.length == 0 && !o.component.isInstanceOf[BlackBox]) {
-        if (o.consumers.length > 0) {
+        if (o.consumers.size > 0) {
           if (Driver.warnOutputs)
             ChiselError.warning({"UNCONNECTED OUTPUT " + emitRef(o) + " in component " + o.component + 
-                                 " has consumers on line " + o.consumers(0).line})
+                                 " has consumers on line " + o.consumers.head.line})
           o.driveRand = true
         } else {
           if (Driver.warnOutputs)

diff --git a/src/main/scala/Cpp.scala b/src/main/scala/Cpp.scala
@@ -656,7 +656,7 @@ class CppBackend extends Backend {
       w match {
         case io: Bits =>
           if (io.dir == OUTPUT) {
-            res += "  " + emitRef(io.consumers(0)) + " = " + emitRef(c) + "->" + n + ";\n";
+            res += "  " + emitRef(io.consumers.head) + " = " + emitRef(c) + "->" + n + ";\n";
           }
       };
     }

diff --git a/src/main/scala/ModularCpp.scala b/src/main/scala/ModularCpp.scala
@@ -99,7 +99,7 @@ class ModularCppBackend extends CppBackend {
     val roots = new ArrayBuffer[Node]
     val walked = new ArrayBuffer[Node]
     for (node <- module.nodes) {
-      if (node.isIo && node.asInstanceOf[Bits].dir == OUTPUT && node.consumers.length == 0)
+      if (node.isIo && node.asInstanceOf[Bits].dir == OUTPUT && node.consumers.size == 0)
         roots += node
     }
 

diff --git a/src/main/scala/Node.scala b/src/main/scala/Node.scala
@@ -33,6 +33,7 @@ package Chisel
 import scala.collection.immutable.Vector
 import scala.collection.mutable.ArrayBuffer
 import scala.collection.mutable.Stack
+import scala.collection.mutable.LinkedHashSet
 import java.io.PrintStream
 
 import Node._;
@@ -143,9 +144,9 @@ abstract class Node extends nameable {
   // The semantics of width are sufficiently complicated that
   // it deserves its own class
   var width_ = Width()
-  val consumers = new ArrayBuffer[Node]; // mods that consume one of my outputs
-  val inputs = new ArrayBuffer[Node];
   var inferWidth: (=> Node) => Width = maxWidth
+  val inputs = ArrayBuffer[Node]()
+  val consumers = LinkedHashSet[Node]() // nodes that consume one of my outputs
 
   var nameHolder: nameable = null;
   val line: StackTraceElement =
@@ -300,7 +301,7 @@ abstract class Node extends nameable {
     writer.println("depth: " + depth)
     writer.println("width: " + width_)
     writer.println("index: " + emitIndex)
-    writer.println("consumers.length: " + consumers.length)
+    writer.println("consumers.size: " + consumers.size)
     writer.println("nameHolder: " + nameHolder)
     writer.println("line: " + line)
     for (in <- inputs) {
@@ -385,9 +386,7 @@ abstract class Node extends nameable {
       /* By construction we should not end-up with null inputs. */
       assert(i != null, ChiselError.error("input " + off
         + " of " + inputs.length + " for node " + this + " is null"))
-      if(!i.consumers.contains(this)) {
-        i.consumers += this;
-      }
+      i.consumers += this
     }
   }
 

diff --git a/src/main/scala/Verilog.scala b/src/main/scala/Verilog.scala
@@ -207,7 +207,7 @@ class VerilogBackend extends Backend {
                 portDec += emitRef(io.inputs(0));
               }
             } else if(io.dir == OUTPUT) {
-              if (io.consumers.length == 0) {
+              if (io.consumers.size == 0) {
                   // if (Driver.saveConnectionWarnings) {
                   //   ChiselError.warning("" + io + " UNCONNECTED IN " + io.component + " BINDING " + c.findBinding(io));
                   // } removed this warning because pruneUnconnectedsIOs should have picked it up
@@ -216,7 +216,7 @@ class VerilogBackend extends Backend {
                 var consumer: Node = c.parent.findBinding(io);
                 if (consumer == null) {
                   if (Driver.saveConnectionWarnings) {
-                    ChiselError.warning("" + io + "(" + io.component + ") OUTPUT UNCONNECTED (" + io.consumers.length + ") IN " + c.parent);
+                    ChiselError.warning("" + io + "(" + io.component + ") OUTPUT UNCONNECTED (" + io.consumers.size + ") IN " + c.parent);
                   }
                   portDec = "//" + portDec
                 } else {
@@ -525,7 +525,7 @@ class VerilogBackend extends Backend {
                 included = false
             }
             else if (io.dir == OUTPUT) {
-              if (io.consumers.length == 0 || m.parent.findBinding(io) == null || io.prune)
+              if (io.consumers.size == 0 || m.parent.findBinding(io) == null || io.prune)
                 included = false
             }
             if (included) wires += io
@@ -543,7 +543,7 @@ class VerilogBackend extends Backend {
                 included = false
             }
             else if (io.dir == OUTPUT) {
-              if (io.consumers.length == 0 || m.parent.findBinding(io) == null || io.prune)
+              if (io.consumers.size == 0 || m.parent.findBinding(io) == null || io.prune)
                 included = false
             }
             if (included) dumpvars += io