Merge pull request #246 from ucb-bar/wirewidthtypearithnamedparams

Wirewidthtypearithnamedparams

Makefile

@@ -19,7 +19,7 @@ smoke:
 publish-local:
 	$(SBT) $(SBT_FLAGS) publish-local
 
-check:
+check test:
 	$(SBT) $(SBT_FLAGS) scct:test
 
 clean:

src/main/scala/Assert.scala

@@ -44,6 +44,7 @@ class Assert(condIn: Bool, resetIn: Bool, val message: String) extends Delay {
 
 class BitsInObject(x: Node) extends UInt {
   inputs += x
+  inferWidth = widthOf(0)
   override lazy val isInObject: Boolean = true
 }
 
@@ -90,10 +91,21 @@ class PrintfBase(formatIn: String, argsIn: Seq[Node]) extends Node {
     msg
   }
 
-  inferWidth = (x: Node) => {
-    val argLength = formats.zip(inputs).map{case (a,b) => lengths(a)(b.width)}.sum
-    8*(format.length - 2*formats.length + argLength)
-  }
+  def argWidth: (=> Node) => Width = { (x) => {
+    if (x != null) {
+      var unknown = false
+      val argLength = formats.zip(inputs).map{case (a,b) => {
+        lengths(a)({ val w = b.widthW;if (w.isKnown) w.needWidth() else {unknown = true; 0}})
+      }}.sum
+      if (unknown)
+        Width()
+      else
+        Width(8*(format.length - 2*formats.length + argLength))
+    } else {
+      Width()
+    }
+  }}
+  inferWidth = argWidth
 
   override def isReg: Boolean = true
   override lazy val isInVCD: Boolean = false

src/main/scala/Bits.scala

@@ -287,20 +287,24 @@ abstract class Bits extends Data with proc {
   override def clone: this.type = {
     val res = this.getClass.newInstance.asInstanceOf[this.type];
     res.inferWidth = this.inferWidth
-    res.width_ = this.width_;
+    res.width_ = this.width_.clone()
     res.dir = this.dir;
     res
   }
 
   override def forceMatchingWidths {
-    if(inputs.length == 1 && inputs(0).width != width) {
-      inputs(0) = inputs(0).matchWidth(width)
+    if(inputs.length == 1 && inputs(0).widthW != widthW) {
+      inputs(0) = inputs(0).matchWidth(widthW)
     }
   }
 
-  override def matchWidth(w: Int): Node =
-    if (isLit && !litOf.isZ) Literal(litOf.value & ((BigInt(1) << w)-1), w)
+  override def matchWidth(w: Width): Node = {
+    if (w.isKnown && isLit && !litOf.isZ) {
+      val wi = w.needWidth()   // TODO 0WW
+      Literal(litOf.value & ((BigInt(1) << wi)-1), wi)
+    }
     else super.matchWidth(w)
+  }
 
   // Operators
   protected final def newUnaryOp(opName: String): this.type = {

src/main/scala/Bool.scala

@@ -60,11 +60,11 @@ class Bool extends UInt {
   override protected def colonEquals(src: Bits): Unit = src match {
     case _: Bool => super.colonEquals(src(0))
     case _ => {
-      if (src.getWidth > 1) {
-        throw new Exception("multi bit signal " + src + " converted to Bool");
-      }
-      if (src.getWidth == -1) {
+      val gotWidth = src.getWidth()
+      if (gotWidth < 1) {
         throw new Exception("unable to automatically convert " + src + " to Bool, convert manually instead");
+      } else if (gotWidth > 1) {
+        throw new Exception("multi bit signal " + src + " converted to Bool");
       }
       super.colonEquals(src(0)) // We only have one bit in *src*.
     }

src/main/scala/CSE.scala

@@ -82,7 +82,7 @@ object CSE {
   }
 
   def inputsEqual(x: Node, y: Node): Boolean = {
-    if (x.width != y.width || x.inputs.length != y.inputs.length)
+    if (x.widthW != y.widthW || x.inputs.length != y.inputs.length)
       return false
     for (i <- 0 until x.inputs.length)
       if (!(x.inputs(i) == y.inputs(i)))

src/main/scala/ChiselError.scala

@@ -104,6 +104,16 @@ object ChiselError {
     }
   }
 
+  // Print stack frames up to and including the "user" stack frame.
+  def printChiselStackTrace() {
+    val stack = Thread.currentThread().getStackTrace
+    val idx = ChiselError.findFirstUserInd(stack)
+    idx match {
+      case None => {}
+      case Some(x) => for (i <- 0 to x) println(stack(i))
+    }
+  }
+
   /** Prints error messages generated by Chisel at runtime. */
   def report() {
     if (!ChiselErrors.isEmpty) {

src/main/scala/Counter.scala

@@ -33,6 +33,8 @@ package Chisel
 import scala.collection.mutable.HashMap
 import scala.math.pow
 
+import Node._
+
 trait CounterBackend extends Backend {
   val firedPins = new HashMap[Module, Bool]
   val daisyIns = new HashMap[Module, UInt]
@@ -314,7 +316,7 @@ trait CounterBackend extends Backend {
       val m = queue.dequeue
 
       for (signal <- m.signals) {
-        val signalWidth = signal.width
+        val signalWidth = signal.needWidth()
         val signalValue = 
           if (decoupledPins contains signal) decoupledPins(signal) 
           else UInt(signal)
@@ -333,7 +335,7 @@ trait CounterBackend extends Backend {
           } else {
             val buffer = Reg(UInt(width = signalWidth))
             val xor = signalValue ^ buffer
-            xor.inferWidth = (x: Node) => signalWidth
+            xor.inferWidth = fixWidth(signalWidth)
             val hd = PopCount(xor)
             addReg(m, buffer, "buffer_%d".format(signal.cntrIdx), 
               Map(firedPins(m) -> signalValue)
@@ -453,7 +455,7 @@ abstract class CounterTester[+T <: Module](c: T, isTrace: Boolean = true) extend
     super.reset(n)
     if (t >= 1) {
       // reset prevPeeks
-      for (signal <- Driver.signals ; if signal.width > 1) {
+      for (signal <- Driver.signals ; if signal.needWidth() > 1) {
         prevPeeks(signal) = 0
       }
     }
@@ -539,7 +541,7 @@ abstract class CounterTester[+T <: Module](c: T, isTrace: Boolean = true) extend
     for (i <- 0 until n) {
       for (signal <- Driver.signals) {
         val curPeek = peekBits(signal)
-        if (signal.width == 1) {
+        if (signal.needWidth() == 1) {
           // increment by the signal's value
           counts(signal) += curPeek
         } else {
@@ -575,7 +577,7 @@ abstract class CounterTester[+T <: Module](c: T, isTrace: Boolean = true) extend
   }
 
   // initialization
-  for (signal <- Driver.signals ; if signal.width > 1) {
+  for (signal <- Driver.signals ; if signal.needWidth() > 1) {
     prevPeeks(signal) = 0
   }
 }