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Documentation for systemverilog plugin #368

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alaindargelas opened this issue Jul 17, 2022 · 0 comments
Open

Documentation for systemverilog plugin #368

alaindargelas opened this issue Jul 17, 2022 · 0 comments

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@alaindargelas
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  1. The -defer option should be documented explicitly as:
    All files compiled in an invocation of systemverilog -defer file1.v file2.v are compiled as a single compilation unit.
    Several compilation units can be created with separate invocations of "systemverilog -defer ..."

I would have called the option -unit instead of -defer, Compilation units are understood by the Verilog community.

  1. Can you give examples on how one pass include paths (-I, +incdir) , library paths (-y), library file extension (+libext+) to the read_systemverilog command? The documentation only talks about passing systemverilog files.
mglb pushed a commit to antmicro/yosys-f4pga-plugins that referenced this issue Apr 3, 2023
…les/sv2v-eb42042

Bump sv2v from `2e43dfe` to `eb42042`
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