ql-qlf plugins: -no_adder flag affects cell parameters in output blif

[coolbreeze413]

From this section:

yosys-f4pga-plugins/ql-qlf-plugin/synth_quicklogic.cc

Line 535 in 77fb7b1

if (inferAdder) {

The logic is causing the cell parameters in output blif to not be written if -no_adder flag is passed in to synth_quicklogic.
We are not sure of the reason behind this logic.
Should this logic be removed to always pass the cell parameters to blif?

This affects RAM scenarios, where the MODE_BITS are not appearing in the output blif, in case the -no_adder is set.