SystemVerilog plugin: empty wire name assertion

[meiniKi]

When reading the picorv32 design through the SystemVerilog plugin, yosys runs into an assertion
ERROR: Assert `!wire->name.empty()' failed in kernel/rtlil.cc:2017.
Reading the same design with read_verilog does work.

I'm using the following setup:

FROM ubuntu:22.04
ARG DEBIAN_FRONTEND=noninteractive
RUN apt-get update && apt-get install -y git wget libreadline-dev libtcl

WORKDIR /test
RUN git clone https://github.com/litex-hub/pythondata-cpu-picorv32.git
WORKDIR /test/pythondata-cpu-picorv32
RUN git checkout tags/2022.12
WORKDIR /test
RUN wget https://github.com/antmicro/yosys-systemverilog/releases/download/67941bc-2022-10-10/yosys-uhdm-integration-67941bc-Ubuntu-20.04-focal-x86_64.tar.gz
RUN tar -xvzf yosys-uhdm-integration-67941bc-Ubuntu-20.04-focal-x86_64.tar.gz

ENTRYPOINT ["/bin/bash"]

Reading with read_verilog:

image/bin/yosys -p "read_verilog -sv /test/pythondata-cpu-picorv32/pythondata_cpu_picorv32/verilog/picorv32.v"

[...]
Generating RTLIL representation for module `\picorv32_wb'.
Successfully finished Verilog frontend.
[...]

Reading with read_systemverilog:

image/bin/yosys -p "plugin -i systemverilog; read_systemverilog /test/pythondata-cpu-picorv32/pythondata_cpu_picorv32/verilog/picorv32.v"

[...]
Generating RTLIL representation for module `$paramod$08824af6197f5f0eeae5e64f76c37c845b98bfe8\picorv32'.
ERROR: Assert `!wire->name.empty()' failed in kernel/rtlil.cc:2017.