Not supported blocking and non-blocking assignments to the same array

[iv2nl0b9v]

Repro

module my_module (
    input wire clk,
    input logic in,
    output logic [1:0] out
);

  assign out[0] = '0;  // blocking
  always_ff @(posedge (clk)) begin
    out[1] <= in;  // non-blocking
  end

endmodule : my_module

UHDM fails to convert it although I think it is a valid Verilog.