Not supported SystemVerilog bit vector functions

[iv2nl0b9v]

Repro

module count_ones (
  input  logic [4:0] in,
  output logic [4:0] out
);
assign out = $countones(in);
endmodule : count_ones

UHDM converter doesn't seem to support SV bit vector functions: https://circuitcove.com/system-tasks-vector/
Not sure if it's intended.

[kgugala]

hi @iv2nl0b9v the systemverilog plugin has been moved to https://github.com/chipsalliance/synlig repository. Can you check if the issue you're reporting is present there? If, please report this problem there