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Add support for SystemRDL source files #47

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RasmusGOlsen opened this issue Jun 18, 2023 · 7 comments
Open

Add support for SystemRDL source files #47

RasmusGOlsen opened this issue Jun 18, 2023 · 7 comments
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Enhancement New feature or request Question Further information is requested

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@RasmusGOlsen
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Can you add support for the register description language SystemRDL?

Here is a link to the standard https://www.accellera.org/downloads/standards/systemrdl.
There is also a great open-source community with a compiler and additional applications https://github.com/SystemRDL.

@Paebbels
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@RasmusGOlsen thanks for the interest in the project and proposing this feature. Also thanks for pull-request #48.

There I see a pySRDLModel.py file implementing at least the version numbers of SystemRDL.

This file would be shipped and installed underneath pyEDAA.ProjectModel, that's not where it should go...

Can can offer 2 solutions:

  1. The GitHub organisation SystemRDL creates a pySRDLModel repository or
  2. I can offer a pySRDLModel under the HDL organisation, or
  3. I can also offer a pySRDLModel under the EDA² organisation.

I think the first solution is the better choice. The repository doesn't need to be complicated and could be a clone of pySVModel. It would offer a separate repository and a matching PyPI package.

If you are an owner of SystemRDL, you could set me up as a maintainer for that repository and I'll take care of the initial setup from for code, documentation page, license, packaging etc.

@RasmusGOlsen
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Yes, I agree that the pySRDLModel should be its own repository. I'm not the owner of the SystemRDL organization, so I don't have any mandate to create it. I can see that the pyVHDLModel is under the HDL organization and the pySVModel is under the EDA2. When I was searching for the models I first looked at the EDA2 organization, for me that would make the most sense.

@Paebbels
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Paebbels commented Jun 18, 2023 via email

@Paebbels
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I can see that the pyVHDLModel is under the HDL organization and the pySVModel is under the EDA2.

Just one tiny correction, pyVHDLModel is under VHDL, not HDL (but I have access to both organisations).

For pySVModel we don't have a host, so it's currently at EDA². Independent of the GitHub location, the package name at PyPI is reserved.

@Paebbels Paebbels added Enhancement New feature or request Question Further information is requested labels Jun 18, 2023
@Paebbels
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Paebbels commented Jun 18, 2023

@Paebbels
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#48 got merged.

@Paebbels
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Paebbels commented Aug 1, 2023

I did some updates and bugfixes to SystemRDL introduced by copy&paste from SystemVerilog.

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Labels
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