Questions about the design and fileset in the project module

[RasmusGOlsen]

I like the idea of an abstract project model. I have difficulties understanding the concept of how designs and file sets are to be used in the project model and what the difference between a design and a file set is.

• Can you give some examples of what a design is?
• Can designs have "sub" designs?
• Are designs e.g. top-level Verilog modules and VHDL entities?
• Are file sets a "sub" design or is it a way to e.g. specify a Verilog compilation unit?
• How do you select file sets or files for different workflows like synthesis and simulations?

[Paebbels]

See Overall Hierarchy for an example.

Can you give some examples of what a design is?

In AMD Vivado you can have multiple parallel designs sharing some or almost all files (filesets) but using different top-levels.

The project model is designs in a way, if no design is specified a default design is used as if there is no design level between project and file sets.

The main idea is sharing files and filesets in e.g. generic VHDL designs. As an example I made one a design for Stratix II, Stratix IV, Stratix V, Virtex 5, Virtex 6, all 7-Series devices, where just the top-levels, 2 packages and the physical layer was exchanged, but all using 95% of same VHDL sources.

Can designs have "sub" designs?

No, designs are flat and the next level below a project.

Filesets can have sub-filesets and sub-filesets can be referenced by multiple parent-filesets.

Are designs e.g. top-level Verilog modules and VHDL entities?

A design has a reference to the top-level, so e.g. for VHDL <libraryname>.<entityname>. Similar for Verilog.

Are file sets a "sub" design or is it a way to e.g. specify a Verilog compilation unit?

A fileset can be an IP core, library (OSVVM, PoC, ...) or subsystem in a bigger design. E.g. an XCI (Xilinx IP Core Instance) references multiple VHDL or Verilog source files. Thus, filesets can have a relative or absolute path identifying the location of listed files or futher filesets. An XCI can reference other XCIs.

How do you select file sets or files for different workflows like synthesis and simulations?

Until now, a workflow is not implemented. This is not the goal of ProjectModel, but it's covered by the whole EDA² stack. Have a look here: https://edaa-org.github.io/

ProjectModel is layer 6:

I also worked already on layers:

0. Installation
   Specify where are tools installed especially if multiple variants and versions exist.
1. CLI abstraction
   Abstract how tools are called and executed on command line independent the operating system. It provides a unified way in setting command line arguments.
2. EDA tool abstraction
   Abstract how EDA tools are called independent of the vendor. E.g. to analyze a VHDL file for VHDL-2008.
3. ⚠️ this is missing but I have a prototype.
4. My model implementation of the VHDL language used by GHDLs Python interface. See pyGHDL.DOM.
5. Data models e.g. for UCIS coverage data. E.g. sponsored by Aldec Inc.
6. This project
7. ⚠️ a file format to put all parts together - missing, but was parts of my old pyIPCMI framework.
8. Idea by @umarcor to provide a webinterface (e.g. design inspection and report browsing)
9. Idea by @umarcor to provide a GUI

[RasmusGOlsen]

So if I understand you correctly a file set is a reusable collection of source files. That could be as big as a complete design to as small as a simple clock domain crossing, a package, a library, IP, VIP, etc.

[Paebbels]

So if I understand you correctly a file set is a reusable collection of source files. That could be as big as a complete design to as small as a simple clock domain crossing, a package, a library, IP, VIP, etc.

Yes 😃

[umarcor]

For completeness, in relation to 8 and 9, see:

• https://umarcor.github.io/hwstudio/
  • Try Right click -> Mode -> Tiles.
  • Then, Right click -> Mode -> Graph.
• https://umarcor.github.io/hwstudio/doc/#_structure

Note that the diagram was done before creating EDAA. So, the run and containers blocks that are separated from pyEDAA in pyOSVB should be redrawn. Nowadays, pyOSVB should be removed from the diagram and replaced with pyEDAA.

See also:

• https://github.com/umarcor/osvb#proofs-of-concept
• https://umarcor.github.io/osvb/apis/project/OSVDE.html

OSVDE is based on pyVHDLmodel and pyGHDL.

Note that both Hardware Studio and OSVDE are just proofs of concept, an horizon to drive the development of all these utility projects.

There is also https://umarcor.github.io/osvb/apis/project/DocGen.html, related to Sphinx. I believe that @Paebbels did several improvements in that regard in the last year, so that's probably superseeded by https://github.com/VHDL/VHDLDomain, but I did not have time to update OSVB docs accordingly.

[umarcor]

There is also:

• https://antmicro.com/blog/2023/03/pipeline-manager-for-kenning/
• https://github.com/antmicro/kenning-pipeline-manager
• https://github.com/antmicro/fpga-topwrap
  • https://antmicro.github.io/fpga-topwrap/

fpga-topwrap is written in Python and it currently uses hdlConvertor (https://github.com/antmicro/fpga-topwrap/blob/main/requirements.txt#L9). It might be adapted to use pyEDAA instead.

[RasmusGOlsen]

Thank you for the information, that was a lot to go through. There are a lot of good ideas. I don't know what the main goal is. I would like a universal HDL development framework. I think the idea behind the Edealize project provides a key component for that, but the EDAM data structure is too simple. It would be better to replace that with a generic project model (like this project), to enable a generic experience at the tool layer. A generic project model would also enable companies to write their own project specification parser and quickly migrate their existing code base to a universal HDL developing framework.

[umarcor]

@RasmusGOlsen, that's precisely the main goal of EDAA and particularly ProjectModel. That's why it's organised into "abstraction" layers, which can be used all together, but it also allows to only use some of them. See https://umarcor.github.io/osvb/apis/core.html and https://umarcor.github.io/osvb/apis/tool.html. That was written before we created EDAA. Then, https://edaa-org.github.io/Context.html.

Edalize is one of the many projects that might provide "workflows" based on EDAA: https://edaa-org.github.io/workflows/index.html. It could use layers 0, 1 and 2 of EDAA, but use different layers for 3 (edalize) and 7 (fusesoc). To be more specific, for instance, https://github.com/olofk/edalize/blob/main/scripts/el_docker might use https://github.com/edaa-org/pyEDAA.CLITool/blob/main/pyEDAA/CLITool/Docker.py. Or, there might be a .core loader, similarly to the currently available OSVVM and Vivado loaders.

See also What problem(s) is EDA² going to solve?, What is EDA² not trying to solve? and What is the target audience of EDA²?.

[Paebbels]

I don't know what the main goal is.

There are 2 parts to it:

1. Reorganize the code, ideas, algorithms that have been in PoC Library / pyIPCMI (IP Core Management Infrastructure) for years and provide them as individual layers. Some are abstract so users can adapt, others are precise. You can see in ProjectModel, it's abstract and generic, but also provides readers for Vivado *.prj or OSVVM's *.pro to create an instance of the model.
   Hence this is for other framework developers to share code and reduce maintenance of data structures and algorithms shared among all Python-based EDA frameworks.
2. Offer a stack of layers and some glue-logic to combine all of them to replace the old monolithic pyIPCMI with a usable EDA framework.
   This is for end users.

I would like a universal HDL development framework.

We too :)
Would you like to join?

I think the idea behind the Edealize project provides a key component for that, but the EDAM data structure is too simple.

Edalize and FuseSoC are too simple. It doesn't reflect what's needed. The data structures are a mess and the code base is even worse...

[Paebbels]

Btw. see our logo: individual layers, but some form a vertical stack.

[RasmusGOlsen]

@Paebbels if you think I can contribute to the project I would like to help. I definitely got some inspiration and ideas reading though the information provided here.

[Paebbels]

Your questions and answers demonstrate to me, you're thinking in the same direction like me and @umarcor :). We can organize a Zoom meeting and see what your ideas and goals are and how it could fit to the EDA² idea or if it's something we didn't cover yet.

We're open for more man-power independent if it's new formats, adapters, test cases, documentation, examples or even a new (sub-)layer :).

You can also find me on Gitter as Paebbels.

[RasmusGOlsen]

Your questions and answers demonstrate to me, you're thinking in the same direction like me and @umarcor :). We can organize a Zoom meeting and see what your ideas and goals are and how it could fit to the EDA² idea or if it's something we didn't cover yet.

Sure we can arrange a meeting.

[RasmusGOlsen]

I'm still not sure how to use the FileSet in practice. It's unclear to me how to use it in combination with Verilog compile units and Verilog and VHDL libraries.

It seems that a FileSet must compile all its files to the same library since the library attribute (_vhdlLibrary) is defined in the FileSet and not the File class. This will prohibit files in the FileSet for both VHDL and Verilog to be compiled into different libraries. I'm not sure if it would make more sense to add the library attribute to the HDLSourceFile class instead of the FileSet. Also, the library attributes should not be VHDL specific since Verilog sources also are compiled into libraries.

[Paebbels]

The property VHDL library is looked up recursively from bottom to top. It can be defined on a file level, if not found it's looked up on fileset level. If filesets are nested, it goes upwards the chain of nested filesets. If still not found, it looks at design-level and then finally project-level.

The default lookup order is defined in the Attribute class, thus it can be overwritten by a derived attribute.

A VHDL library association is a property to VHDL files (see VHDLSourceFile), so it's defined here https://github.com/edaa-org/pyEDAA.ProjectModel/blob/main/pyEDAA/ProjectModel/__init__.py?ts=2#L366

Verilog files are not part VHDL libraries. As far as I know, Verilog has no grouping / namespace mechanism, right? Verilog modules are referenced in VHDL by components as a stub definition (dummy interface of a black-box), which is later bound in elaboration phase to a Verilog module. This technique is used for mixed-language designs. It works also for AHDL, (EDIF) netlists, design check points (netlists in a zip file), ...

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What tool compiles Verilog sources into VHDL libraries?
Is direct entity instantiation allowed?